SU493164A1 - Associative storage device - Google Patents

Description

(54) ASSOCIATIVE STORAGE DEVICE

Claims (1)

This invention relates to memory devices. A associative memory device (CAM) is known, containing groups of addressable storage modules, the total address of which is connected to the outputs of the corresponding interrogator. However, the known device has a large amount of equipment caused by the inefficient use of address storage modules with a large capacity of these modules. The inefficiency of the known device is due to the fact that the number of address shchk needed to write to the - to the bit code signs, is 2, since this code is recorded in the elements of the ra; the adjacent line associated with the corresponding detector, in the form of a unit against the background of zeros (in each module). At the same time, the number of the address line along which the entries are recorded is determined by the code of the corresponding associative word. The purpose of the invention is to reduce the amount of equipment. The described ABC is distinguished from the known one by the fact that it contains output decoders, the inputs of which are connected via matching schemes to the corresponding one nominal bit-iins of the address storage modules of each group, and the first outputs of the output decoders are connected to the input; device priority scheme. The drawing shows a block diagram of the device. The device consists of a poll register, the outputs of which are connected via decoders 2 polls with address buses 3 of the corresponding address memory modules 4, combine}: 1, the common buses 3 into groups. The discharge buses of 5 modules of the same group, associated with different decoder 2 polls, through circuits 6 and 7, coincide by zero and one are connected to the inputs of the output decoders 8, perform their function as detectors. A priority circuit E is connected to the first outputs of the decoders 8. The operation of the device consists in the following. Before writing down a new associative (.. what is common for sh. Travel pepshfrator 8,; pooi with modules 4 with ore elements, cBflr.vnftiif ie with b1brang11 hell of curriculum 3, bullet code. Assotiate code enters the poll register 1 and according to this code, it is awaited on one address bus 3 on the first decrypt}} 2 polls. E:; if in any set of modules 4 associated with idle output decoder 8, all elements on the excited address buses 3 are written with zeros, then the FTO outputs of all the 6 coincidence circuits connected to this decryption processor coincidence signals, as a result of which the first output of the isoframer 8 is excited. In the module 4 cell, connected to this output, all free P-bit indicative combinations (or one boundary) 1a combination are indicated. In accordance with one of these combinations, bit numbered 5 bits, which are associated with the selected decoder 8, are excited, and unit codes are recorded at the intersection of the selected address and bit buses. After that, this combination is excluded from the number of free ones, i.e., zeros are written into the corresponding cell elements of the module. If there are several free output decoders 8, then the recording cell (and the corresponding decoder 8) are determined using the priority scheme 9 executed by any known in a manner analogous to prc priority setting schemes of a multi-valued sample. During polling, one address bus 3 is excited for each decoder 2 polls. in accordance with the polling code on register 1. If, in either a set of modules 4 connected to one decoder 8, combinations written in modules that correspond to different decoders 2 match, then according to this combination, exactly half of the circuits 6 and 7 matches of this decoder 8. As a result, a match signal appears at the output of the selected decoder 8, and the output number is determined by the selected combination. Since the sample go m11 / 1CH11.HH, t. and LZU are recorded only) by the river Ülkch Kiezieg with a layer, then n of the rest of 1) PTF) 1H1 prlx 8 excitement - with less than r the olovypes of schemes 6 and 7 of the joint program. Consequently, at least in one of the bits of the indication of a code, the power could not be (3, both circuit 6 matches and circuit 7 matches, i.e., one of the same) 1 can be excited in non-defective decals. in the polling mode, the first outlets of the encoders 8 are blocked, since the free cells may give a parasitic coincidence signal. If during the recording it turns out that all the CAM cells are over 1 you, then O1 determines the location of the associative word that can be erased, and the corresponding indicative combination is remembered. Since no more than half of all memory elements are used to record associative features, Next, it checks whether the new word can be written to the ABC. If the check is successful, then the selected combination is released at the intersection of the selected address and bit buses. Otherwise, the rewriting procedure continues until a new word can be written. An associative memory device containing groups of addressable storage modules whose common address buses are connected to the outputs of the corresponding interrogation coders, the inputs of which are connected to the corresponding outputs of the interrogation register, characterized in that, in order to reduce the number of equipment, it contains output decryptors , whose inputs through the coincidence circuits are connected to the corresponding homogeneous bit buses of the address storage modules of each group, and the first outputs of the output are The emitters are connected to the priority scheme entered into the device. i m mmmmm mmmmmmmi;