FR2260141A1 - Data transfer control for data processor - is used between periodic and non-periodic units employing buffer memory - Google Patents

Data transfer control for data processor - is used between periodic and non-periodic units employing buffer memory

Info

Publication number
FR2260141A1
FR2260141A1 FR7403489A FR7403489A FR2260141A1 FR 2260141 A1 FR2260141 A1 FR 2260141A1 FR 7403489 A FR7403489 A FR 7403489A FR 7403489 A FR7403489 A FR 7403489A FR 2260141 A1 FR2260141 A1 FR 2260141A1
Authority
FR
France
Prior art keywords
periodic
buffer memory
transfer control
data transfer
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7403489A
Other languages
French (fr)
Other versions
FR2260141B1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull SA
Original Assignee
Societe Industrielle Honeywell Bull
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Societe Industrielle Honeywell Bull filed Critical Societe Industrielle Honeywell Bull
Priority to FR7403489A priority Critical patent/FR2260141A1/en
Publication of FR2260141A1 publication Critical patent/FR2260141A1/en
Application granted granted Critical
Publication of FR2260141B1 publication Critical patent/FR2260141B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/12—Indexing scheme relating to groups G06F5/12 - G06F5/14
    • G06F2205/126—Monitoring of intermediate fill level, i.e. with additional means for monitoring the fill level, e.g. half full flag, almost empty flag

Abstract

The buffer memory (40) comprises a number of registers arranged in order, with addressing means allowing data to be written-in on read-out and then transmitted between the two units, under the control of operating codes provided by one of the two units. Preferably the addressing means comprises two counters (MP, PP) which respectively record the data transferred between the non-periodic unit and the buffer memory (40), and between the latter and the periodic unit. A third counter is used for recording the difference between the contents of the other two counters (MP, PP) to indicate at any time the number of free memory locations.
FR7403489A 1974-02-01 1974-02-01 Data transfer control for data processor - is used between periodic and non-periodic units employing buffer memory Granted FR2260141A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7403489A FR2260141A1 (en) 1974-02-01 1974-02-01 Data transfer control for data processor - is used between periodic and non-periodic units employing buffer memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7403489A FR2260141A1 (en) 1974-02-01 1974-02-01 Data transfer control for data processor - is used between periodic and non-periodic units employing buffer memory

Publications (2)

Publication Number Publication Date
FR2260141A1 true FR2260141A1 (en) 1975-08-29
FR2260141B1 FR2260141B1 (en) 1977-09-16

Family

ID=9134379

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7403489A Granted FR2260141A1 (en) 1974-02-01 1974-02-01 Data transfer control for data processor - is used between periodic and non-periodic units employing buffer memory

Country Status (1)

Country Link
FR (1) FR2260141A1 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2399064A1 (en) * 1977-07-25 1979-02-23 Ibm BUFFER MEMORY UNIT IN A DATA PROCESSING SYSTEM
FR2406251A1 (en) * 1977-08-04 1979-05-11 Honeywell Inf Systems IMPROVEMENTS TO A DATA TRANSFER CONTROL SYSTEM
FR2486290A1 (en) * 1980-07-04 1982-01-08 Hitachi Ltd FAST DATA TRANSMISSION DEVICE HAVING A DIRECT MEMORY ACCESS CONTROL CIRCUIT
WO1984000835A1 (en) * 1982-08-13 1984-03-01 Western Electric Co First-in, first-out (fifo) memory configuration for queue storage
EP0165915A2 (en) * 1984-06-21 1985-12-27 Cray Research, Inc. Peripheral interface system
FR2638870A1 (en) * 1988-11-09 1990-05-11 Mitsubishi Electric Corp INPUT / OUTPUT CHANNEL APPARATUS

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2399064A1 (en) * 1977-07-25 1979-02-23 Ibm BUFFER MEMORY UNIT IN A DATA PROCESSING SYSTEM
FR2406251A1 (en) * 1977-08-04 1979-05-11 Honeywell Inf Systems IMPROVEMENTS TO A DATA TRANSFER CONTROL SYSTEM
FR2486290A1 (en) * 1980-07-04 1982-01-08 Hitachi Ltd FAST DATA TRANSMISSION DEVICE HAVING A DIRECT MEMORY ACCESS CONTROL CIRCUIT
WO1984000835A1 (en) * 1982-08-13 1984-03-01 Western Electric Co First-in, first-out (fifo) memory configuration for queue storage
US4507760A (en) * 1982-08-13 1985-03-26 At&T Bell Laboratories First-in, first-out (FIFO) memory configuration for queue storage
EP0165915A2 (en) * 1984-06-21 1985-12-27 Cray Research, Inc. Peripheral interface system
EP0165915A3 (en) * 1984-06-21 1988-12-07 Cray Research, Inc. Peripheral interface system
FR2638870A1 (en) * 1988-11-09 1990-05-11 Mitsubishi Electric Corp INPUT / OUTPUT CHANNEL APPARATUS

Also Published As

Publication number Publication date
FR2260141B1 (en) 1977-09-16

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