FR2081017A2 - Fabrication of a semiconductor device - Google Patents

Fabrication of a semiconductor device

Info

Publication number
FR2081017A2
FR2081017A2 FR7105551A FR7105551A FR2081017A2 FR 2081017 A2 FR2081017 A2 FR 2081017A2 FR 7105551 A FR7105551 A FR 7105551A FR 7105551 A FR7105551 A FR 7105551A FR 2081017 A2 FR2081017 A2 FR 2081017A2
Authority
FR
France
Prior art keywords
silicon
layer
semiconductor
configuration
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7105551A
Other languages
English (en)
French (fr)
Other versions
FR2081017B2 (enrdf_load_stackoverflow
Inventor
E Kooi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from NL666614016A external-priority patent/NL153374B/xx
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of FR2081017A2 publication Critical patent/FR2081017A2/fr
Application granted granted Critical
Publication of FR2081017B2 publication Critical patent/FR2081017B2/fr
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401Combinations of FETs or IGBTs with BJTs
    • H10D84/403Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
FR7105551A 1966-10-05 1971-02-18 Fabrication of a semiconductor device Granted FR2081017A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL666614016A NL153374B (nl) 1966-10-05 1966-10-05 Werkwijze ter vervaardiging van een halfgeleiderinrichting voorzien van een oxydelaag en halfgeleiderinrichting vervaardigd volgens de werkwijze.
NL7002384.A NL159817B (nl) 1966-10-05 1970-02-19 Werkwijze ter vervaardiging van een halfgeleiderinrichting.

Publications (2)

Publication Number Publication Date
FR2081017A2 true FR2081017A2 (en) 1971-11-26
FR2081017B2 FR2081017B2 (enrdf_load_stackoverflow) 1976-03-19

Family

ID=26644100

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7105551A Granted FR2081017A2 (en) 1966-10-05 1971-02-18 Fabrication of a semiconductor device

Country Status (5)

Country Link
AT (1) AT339959B (enrdf_load_stackoverflow)
DE (1) DE2105178C3 (enrdf_load_stackoverflow)
FR (1) FR2081017A2 (enrdf_load_stackoverflow)
NL (1) NL159817B (enrdf_load_stackoverflow)
SE (1) SE372139B (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2132347A1 (enrdf_load_stackoverflow) * 1971-04-03 1972-11-17 Philips Nv
FR2308204A1 (fr) * 1975-04-16 1976-11-12 Ibm Procede de fabrication de regions de circuit integre definies par une isolation dielectrique encastree

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3254277A (en) * 1963-02-27 1966-05-31 United Aircraft Corp Integrated circuit with component defining groove
US3411051A (en) * 1964-12-29 1968-11-12 Texas Instruments Inc Transistor with an isolated region having a p-n junction extending from the isolation wall to a surface
FR1594694A (enrdf_load_stackoverflow) * 1967-10-28 1970-07-17

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3386865A (en) * 1965-05-10 1968-06-04 Ibm Process of making planar semiconductor devices isolated by encapsulating oxide filled channels
NL153374B (nl) * 1966-10-05 1977-05-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting voorzien van een oxydelaag en halfgeleiderinrichting vervaardigd volgens de werkwijze.
US3488564A (en) * 1968-04-01 1970-01-06 Fairchild Camera Instr Co Planar epitaxial resistors
US3649386A (en) * 1968-04-23 1972-03-14 Bell Telephone Labor Inc Method of fabricating semiconductor devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3254277A (en) * 1963-02-27 1966-05-31 United Aircraft Corp Integrated circuit with component defining groove
US3411051A (en) * 1964-12-29 1968-11-12 Texas Instruments Inc Transistor with an isolated region having a p-n junction extending from the isolation wall to a surface
FR1594694A (enrdf_load_stackoverflow) * 1967-10-28 1970-07-17

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2132347A1 (enrdf_load_stackoverflow) * 1971-04-03 1972-11-17 Philips Nv
FR2308204A1 (fr) * 1975-04-16 1976-11-12 Ibm Procede de fabrication de regions de circuit integre definies par une isolation dielectrique encastree

Also Published As

Publication number Publication date
DE2105178A1 (de) 1971-09-02
NL159817B (nl) 1979-03-15
AT339959B (de) 1977-11-25
FR2081017B2 (enrdf_load_stackoverflow) 1976-03-19
ATA130671A (de) 1977-03-15
DE2105178C3 (de) 1983-12-22
SE372139B (enrdf_load_stackoverflow) 1974-12-09
NL7002384A (enrdf_load_stackoverflow) 1971-08-23
DE2105178B2 (de) 1979-07-12

Similar Documents

Publication Publication Date Title
NL153374B (nl) Werkwijze ter vervaardiging van een halfgeleiderinrichting voorzien van een oxydelaag en halfgeleiderinrichting vervaardigd volgens de werkwijze.
ES321208A1 (es) Un metodo de producir un dispositivo semiconductor.
ES360408A1 (es) Un dispositivo semiconductor.
FR2194047B1 (enrdf_load_stackoverflow)
FR2081017A2 (en) Fabrication of a semiconductor device
JPS5666065A (en) Semiconductor memory unit
JPS5533075A (en) Mesa semiconductor device
JPS5220769A (en) Longitudinal semi-conductor unit
JPS523383A (en) Manufacturing method of semiconductor device electrode
JPS56165358A (en) Semiconductor device
ES393039A2 (es) Un metodo de fabricar un dispositivo semiconductor.
JPS57100719A (en) Manufacture of semiconductor device
JPS5618466A (en) Manufacture of semiconductor device
JPS52117063A (en) Preparation of ohmic ontact layer in semiconductor device
GB916379A (en) Improvements in and relating to semiconductor junction units
JPS5637677A (en) Silicon planar type thyristor
ES408908A1 (es) Un metodo de fabricar un dispositivo semiconductor.
JPS5253680A (en) Semiconductor device
JPS5276888A (en) Semiconductor device
JPS5630732A (en) Mounting method of semiconductor pellet
JPS5429587A (en) Semiconductor device
JPS526081A (en) Semiconductor wafer
JPS5232682A (en) Manufacturing process of semiconductor device
GB1107343A (en) Microminiaturised, integrated circuit arrangement
JPS5667970A (en) Gate turn-off thyristor