AT339959B - Verfahren zum herstellen einer integrierten monolithischen halbleiteranordnung mit versenkter isolierschicht - Google Patents
Verfahren zum herstellen einer integrierten monolithischen halbleiteranordnung mit versenkter isolierschichtInfo
- Publication number
- AT339959B AT339959B AT130671A AT130671A AT339959B AT 339959 B AT339959 B AT 339959B AT 130671 A AT130671 A AT 130671A AT 130671 A AT130671 A AT 130671A AT 339959 B AT339959 B AT 339959B
- Authority
- AT
- Austria
- Prior art keywords
- producing
- insulating layer
- semiconductor arrangement
- monolithic semiconductor
- integrated monolithic
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0635—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors and diodes, or resistors, or capacitors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL666614016A NL153374B (nl) | 1966-10-05 | 1966-10-05 | Werkwijze ter vervaardiging van een halfgeleiderinrichting voorzien van een oxydelaag en halfgeleiderinrichting vervaardigd volgens de werkwijze. |
NL7002384A NL159817B (nl) | 1966-10-05 | 1970-02-19 | Werkwijze ter vervaardiging van een halfgeleiderinrichting. |
Publications (2)
Publication Number | Publication Date |
---|---|
ATA130671A ATA130671A (de) | 1977-03-15 |
AT339959B true AT339959B (de) | 1977-11-25 |
Family
ID=26644100
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT130671A AT339959B (de) | 1966-10-05 | 1971-02-16 | Verfahren zum herstellen einer integrierten monolithischen halbleiteranordnung mit versenkter isolierschicht |
Country Status (5)
Country | Link |
---|---|
AT (1) | AT339959B (de) |
DE (1) | DE2105178C3 (de) |
FR (1) | FR2081017A2 (de) |
NL (1) | NL159817B (de) |
SE (1) | SE372139B (de) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL170901C (nl) * | 1971-04-03 | 1983-01-03 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting. |
US4044454A (en) * | 1975-04-16 | 1977-08-30 | Ibm Corporation | Method for forming integrated circuit regions defined by recessed dielectric isolation |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3254277A (en) * | 1963-02-27 | 1966-05-31 | United Aircraft Corp | Integrated circuit with component defining groove |
US3411051A (en) * | 1964-12-29 | 1968-11-12 | Texas Instruments Inc | Transistor with an isolated region having a p-n junction extending from the isolation wall to a surface |
US3386865A (en) * | 1965-05-10 | 1968-06-04 | Ibm | Process of making planar semiconductor devices isolated by encapsulating oxide filled channels |
NL153374B (nl) * | 1966-10-05 | 1977-05-16 | Philips Nv | Werkwijze ter vervaardiging van een halfgeleiderinrichting voorzien van een oxydelaag en halfgeleiderinrichting vervaardigd volgens de werkwijze. |
NL6815286A (de) * | 1967-10-28 | 1969-05-01 | ||
US3488564A (en) * | 1968-04-01 | 1970-01-06 | Fairchild Camera Instr Co | Planar epitaxial resistors |
US3649386A (en) * | 1968-04-23 | 1972-03-14 | Bell Telephone Labor Inc | Method of fabricating semiconductor devices |
-
1970
- 1970-02-19 NL NL7002384A patent/NL159817B/xx unknown
-
1971
- 1971-02-04 DE DE19712105178 patent/DE2105178C3/de not_active Expired
- 1971-02-16 AT AT130671A patent/AT339959B/de not_active IP Right Cessation
- 1971-02-16 SE SE197871A patent/SE372139B/xx unknown
- 1971-02-18 FR FR7105551A patent/FR2081017A2/fr active Granted
Also Published As
Publication number | Publication date |
---|---|
DE2105178B2 (de) | 1979-07-12 |
DE2105178A1 (de) | 1971-09-02 |
NL7002384A (de) | 1971-08-23 |
FR2081017B2 (de) | 1976-03-19 |
NL159817B (nl) | 1979-03-15 |
FR2081017A2 (en) | 1971-11-26 |
DE2105178C3 (de) | 1983-12-22 |
ATA130671A (de) | 1977-03-15 |
SE372139B (de) | 1974-12-09 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ELA | Expired due to lapse of time | ||
UEP | Publication of translation of european patent specification | ||
REN | Ceased due to non-payment of the annual fee |