FR2011063A1 - - Google Patents
Info
- Publication number
- FR2011063A1 FR2011063A1 FR6919922A FR6919922A FR2011063A1 FR 2011063 A1 FR2011063 A1 FR 2011063A1 FR 6919922 A FR6919922 A FR 6919922A FR 6919922 A FR6919922 A FR 6919922A FR 2011063 A1 FR2011063 A1 FR 2011063A1
- Authority
- FR
- France
- Prior art keywords
- layer
- circuit
- aluminium
- connections
- elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
- H10D84/901—Masterslice integrated circuits comprising bipolar technology
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/086—Emitter coupled logic
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US73776068A | 1968-06-17 | 1968-06-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| FR2011063A1 true FR2011063A1 (enExample) | 1970-02-27 |
Family
ID=24965207
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR6919922A Withdrawn FR2011063A1 (enExample) | 1968-06-17 | 1969-06-16 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US3558992A (enExample) |
| DE (1) | DE1764567B2 (enExample) |
| FR (1) | FR2011063A1 (enExample) |
| GB (1) | GB1251454A (enExample) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3702427A (en) * | 1971-02-22 | 1972-11-07 | Fairchild Camera Instr Co | Electromigration resistant metallization for integrated circuits, structure and process |
| US3795975A (en) * | 1971-12-17 | 1974-03-12 | Hughes Aircraft Co | Multi-level large scale complex integrated circuit having functional interconnected circuit routed to master patterns |
| US3877051A (en) * | 1972-10-18 | 1975-04-08 | Ibm | Multilayer insulation integrated circuit structure |
| CA997481A (en) * | 1972-12-29 | 1976-09-21 | International Business Machines Corporation | Dc testing of integrated circuits and a novel integrated circuit structure to facilitate such testing |
| GB1440512A (en) * | 1973-04-30 | 1976-06-23 | Rca Corp | Universal array using complementary transistors |
| CA1024661A (en) * | 1974-06-26 | 1978-01-17 | International Business Machines Corporation | Wireable planar integrated circuit chip structure |
| JPS5851425B2 (ja) * | 1975-08-22 | 1983-11-16 | 株式会社日立製作所 | ハンドウタイソウチ |
| JPS5444881A (en) * | 1977-09-16 | 1979-04-09 | Nec Corp | Electrode wiring structure of integrated circuit |
| JPS5662352A (en) | 1979-10-26 | 1981-05-28 | Hitachi Ltd | Semiconductor integrated circuit device for acoustic amplification circuit |
| US4467400A (en) * | 1981-01-16 | 1984-08-21 | Burroughs Corporation | Wafer scale integrated circuit |
| US4458297A (en) * | 1981-01-16 | 1984-07-03 | Mosaic Systems, Inc. | Universal interconnection substrate |
| EP0098173B1 (en) * | 1982-06-30 | 1990-04-11 | Fujitsu Limited | Semiconductor integrated-circuit apparatus |
| US4746966A (en) * | 1985-10-21 | 1988-05-24 | International Business Machines Corporation | Logic-circuit layout for large-scale integrated circuits |
| JPH0817227B2 (ja) * | 1987-04-30 | 1996-02-21 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | 個性化可能な半導体チップ |
| US4880754A (en) * | 1987-07-06 | 1989-11-14 | International Business Machines Corp. | Method for providing engineering changes to LSI PLAs |
| JPH03218668A (ja) * | 1989-11-24 | 1991-09-26 | Nec Ic Microcomput Syst Ltd | 半導体集積回路装置 |
| US5322812A (en) * | 1991-03-20 | 1994-06-21 | Crosspoint Solutions, Inc. | Improved method of fabricating antifuses in an integrated circuit device and resulting structure |
-
1968
- 1968-06-17 US US737760A patent/US3558992A/en not_active Expired - Lifetime
- 1968-06-27 DE DE19681764567 patent/DE1764567B2/de active Pending
-
1969
- 1969-06-09 GB GB1251454D patent/GB1251454A/en not_active Expired
- 1969-06-16 FR FR6919922A patent/FR2011063A1/fr not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| US3558992A (en) | 1971-01-26 |
| DE1764567A1 (de) | 1972-01-27 |
| GB1251454A (enExample) | 1971-10-27 |
| DE1764567B2 (de) | 1972-09-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| GB1251454A (enExample) | ||
| US4410905A (en) | Power, ground and decoupling structure for chip carriers | |
| GB1362136A (en) | Transistor package | |
| GB1316697A (en) | Semiconductor devices | |
| DE3482719D1 (de) | Halbleiterelement und herstellungsverfahren. | |
| JPS6427235A (en) | Device for interconnection of multiplex integrated circuits | |
| GB1147469A (en) | Semiconductor devices, integrated circuits and methods for making same | |
| GB1135555A (en) | Improvements in or relating to semiconductor devices | |
| US4591895A (en) | CMOS circuit with separate power lines to suppress latchup | |
| JPH0576783B2 (enExample) | ||
| JPS60137050A (ja) | 半導体装置 | |
| JPS63304645A (ja) | 半導体集積回路 | |
| JPH03106043A (ja) | 半導体装置 | |
| JPS6081852A (ja) | 半導体装置 | |
| GB1099930A (en) | Improvements in or relating to semiconductor devices | |
| GB1365261A (en) | Interconnections for integrated arrangements | |
| JPS58109254U (ja) | フエ−スダウン接続形チツプ用チツプキヤリヤ− | |
| JPH01109739A (ja) | 半導体集積回路 | |
| JPS6088549U (ja) | アナログ・デイジタル混在集積回路 | |
| JPS59185833U (ja) | 半導体装置 | |
| JPS6313371A (ja) | 半導体装置 | |
| JPS59165440A (ja) | 集積回路パツケ−ジ | |
| JPS5929051U (ja) | 半導体装置 | |
| JPS60149136U (ja) | 集積回路素子 | |
| JPS62274654A (ja) | 入力保護装置 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| ST | Notification of lapse |