FI94697C - Menetelmä digitaalisessa tietoliikennejärjestelmässä suoritettavan puskuroinnin toteuttamiseksi sekä puskuri - Google Patents
Menetelmä digitaalisessa tietoliikennejärjestelmässä suoritettavan puskuroinnin toteuttamiseksi sekä puskuri Download PDFInfo
- Publication number
- FI94697C FI94697C FI934544A FI934544A FI94697C FI 94697 C FI94697 C FI 94697C FI 934544 A FI934544 A FI 934544A FI 934544 A FI934544 A FI 934544A FI 94697 C FI94697 C FI 94697C
- Authority
- FI
- Finland
- Prior art keywords
- buffer
- data
- synchronization
- bit
- memory
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/16—Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
- H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Information Transfer Systems (AREA)
- Communication Control (AREA)
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FI934544A FI94697C (fi) | 1993-10-14 | 1993-10-14 | Menetelmä digitaalisessa tietoliikennejärjestelmässä suoritettavan puskuroinnin toteuttamiseksi sekä puskuri |
AU78153/94A AU7815394A (en) | 1993-10-14 | 1994-10-13 | A buffering method and a buffer |
PCT/FI1994/000462 WO1995010897A1 (fr) | 1993-10-14 | 1994-10-13 | Procede de mise en memoire tampon et memoire tampon associee |
GB9607820A GB2297464B (en) | 1993-10-14 | 1994-10-13 | A buffering method and a buffer |
DE4497707A DE4497707B4 (de) | 1993-10-14 | 1994-10-13 | Pufferungsverfahren und Puffer |
DE4497707T DE4497707T1 (de) | 1993-10-14 | 1994-10-13 | Pufferungsverfahren und Puffer |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FI934544A FI94697C (fi) | 1993-10-14 | 1993-10-14 | Menetelmä digitaalisessa tietoliikennejärjestelmässä suoritettavan puskuroinnin toteuttamiseksi sekä puskuri |
FI934544 | 1993-10-14 |
Publications (4)
Publication Number | Publication Date |
---|---|
FI934544A0 FI934544A0 (fi) | 1993-10-14 |
FI934544A FI934544A (fi) | 1995-04-15 |
FI94697B FI94697B (fi) | 1995-06-30 |
FI94697C true FI94697C (fi) | 1995-10-10 |
Family
ID=8538782
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FI934544A FI94697C (fi) | 1993-10-14 | 1993-10-14 | Menetelmä digitaalisessa tietoliikennejärjestelmässä suoritettavan puskuroinnin toteuttamiseksi sekä puskuri |
Country Status (5)
Country | Link |
---|---|
AU (1) | AU7815394A (fr) |
DE (2) | DE4497707B4 (fr) |
FI (1) | FI94697C (fr) |
GB (1) | GB2297464B (fr) |
WO (1) | WO1995010897A1 (fr) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SE515563C2 (sv) * | 1995-01-11 | 2001-08-27 | Ericsson Telefon Ab L M | Dataöverföringssystem |
DE19529966A1 (de) * | 1995-08-14 | 1997-02-20 | Thomson Brandt Gmbh | Verfahren und Schaltungsanordnung zur Resynchronisation einer Speicherverwaltung |
FR2746987A1 (fr) * | 1996-03-29 | 1997-10-03 | Philips Electronics Nv | Convertisseur analogique/numerique a frequence d'echantillonnage elevee |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4710920A (en) * | 1986-06-19 | 1987-12-01 | General Datacomm, Inc. | Bit interleaved multiplexer system providing byte synchronization for communicating apparatuses |
FI94812C (fi) * | 1993-05-18 | 1995-10-25 | Nokia Telecommunications Oy | Menetelmä ja laite tasauspäätöksen aikaansaamiseksi synkronisen digitaalisen tietoliikennejärjestelmän solmupisteessä |
-
1993
- 1993-10-14 FI FI934544A patent/FI94697C/fi active
-
1994
- 1994-10-13 WO PCT/FI1994/000462 patent/WO1995010897A1/fr active Application Filing
- 1994-10-13 GB GB9607820A patent/GB2297464B/en not_active Expired - Fee Related
- 1994-10-13 AU AU78153/94A patent/AU7815394A/en not_active Abandoned
- 1994-10-13 DE DE4497707A patent/DE4497707B4/de not_active Expired - Fee Related
- 1994-10-13 DE DE4497707T patent/DE4497707T1/de active Pending
Also Published As
Publication number | Publication date |
---|---|
FI94697B (fi) | 1995-06-30 |
FI934544A0 (fi) | 1993-10-14 |
GB2297464B (en) | 1997-12-10 |
DE4497707B4 (de) | 2004-12-23 |
DE4497707T1 (de) | 1996-10-31 |
WO1995010897A1 (fr) | 1995-04-20 |
GB9607820D0 (en) | 1996-06-19 |
AU7815394A (en) | 1995-05-04 |
FI934544A (fi) | 1995-04-15 |
GB2297464A (en) | 1996-07-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4415984A (en) | Synchronous clock regenerator for binary serial data signals | |
CA2088156C (fr) | Methode et dispositif de transfert de donnees entre signaux sonet de frequences differentes | |
JPS60219891A (ja) | デジタル交換システム | |
US4330856A (en) | Digital signal transmission system including means for converting asynchronous signals to the operating speed of a transmission line | |
EP0311448B1 (fr) | Multiplexeur numérique | |
JPH04222133A (ja) | 異なるビット速度のディジタルビット列を時分割多重化することにより多重化されたディジタルビット列の交差接続装置用のスイッチング要素 | |
US4713804A (en) | Method and device for converting digital channel multiframes into packet multiframes | |
FI94697C (fi) | Menetelmä digitaalisessa tietoliikennejärjestelmässä suoritettavan puskuroinnin toteuttamiseksi sekä puskuri | |
US8385472B2 (en) | Context-sensitive overhead processor | |
JPS582497B2 (ja) | 信号速度補償装置 | |
US5325404A (en) | Synchronization device for performing synchronous circuit switching functions thru an asynchronous communication node | |
CA2021348C (fr) | Circuit de stockage elastique | |
US7139293B1 (en) | Method and apparatus for changing the data rate of a data signal | |
US5715249A (en) | ATM cell format converter using cell start indicator for generating output cell pulse | |
GB1536337A (en) | Error detection in digital systems | |
RU2180992C2 (ru) | Переключатель с однобитовым разрешением | |
US6973101B1 (en) | N-way simultaneous framer for bit-interleaved time division multiplexed (TDM) serial bit streams | |
US7308004B1 (en) | Method and apparatus of multiplexing and demultiplexing communication signals | |
GB1560205A (en) | Signal transfer system for the division switching centres | |
JPH03198544A (ja) | パリティ計数回路 | |
JPS6141186B2 (fr) | ||
KR920001548B1 (ko) | 북미방식 표준 프레임 구조를 갖는 디지탈 통신망의 채널 데이타 송수신 장치 및 방법 | |
GB1452335A (en) | Memory system | |
JP3010634B2 (ja) | フレーム同期多重処理方式 | |
EP0977390A2 (fr) | Circuit pour extraction et insertion d'octets de contrôle dans des trames SDH |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
BB | Publication of examined application |