GB1560205A - Signal transfer system for the division switching centres - Google Patents

Description

(54) SIGNAL TRANSFER SYSTEM FOR TIME DIVISION SWITCH ING CENTRES (71) We, INTERNATIONAL STAN DARD ELECTRIC CORPORATION, a Corporation organised and existing under the Laws of the State of Delaware, United States of America, of 320 Park Avenue, New York 22, State of New York, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to a signal transfer system for TDM switching centres, and especially to a "line" signalling transfer system between at least one multiplex highway having access to a time division switching centre and at least one multiregister in this centre.

Setting up, holding and releasing of telephone calls, in particular, requires signal transmission between switching centres. In this respect, a distinction is usually made between "line" signalling which includes exchanges of signals relating to the state of the call or of the channels it uses between the centres, and "register" signalling which includes exchanges of signals concerning the call destination (called number, class of call, etc....) and its routing situation (congestion, busy, free, etc....). In fact, this distinction is far from being general and depends on the telephone networks. It appears in a typical way in the networks using multifrequency signalling. Indeed, register signalling is exchanged as voice frequency signals during the call setting period, line signalling concerns all the other signals exchanged during the whole time of the call.

Line signalling is usually exchanged between units permanently connected to the call channel, while register signalling requires complex units which are connected to the channel only on a temporary basis.

When the call uses a pulse code modulation (PCM) multiplex highway, line signalling is transmitted by a signalling channel, while the register signalling uses the speech channel.

The PCM highway of the 30 channel CEPT type is based on a 125 ,us recurring frame divided into 32 equal time slots. Each time slot permits transmission of 8 binary digits or bits. The first time slot of each frame is used for frame synchronization, and the 17th time slot is used for the signalling channel. The other 30 time slots correspond to 30 speech channels. In the case of channel-tochannel signalling, the 17th time slots of 16 consecutive frames forming a multiframe permit transmission of the 30 speech channel line signalling. Out of the 16 8-bit combinations supplied by these 17th time slots of the multiframe, the first is used for multiframe synchronization, the other 15 each carry line signalling of two distinct speech channels and thus permit transmission of 4 bits per speech channel.

In a TDM switching centre at which such a highway arrives, line signalling can be collected and injected at the centre inputs by a line signaller controller serving as an interface between the PCM highways and the switching centre central control unit. Register signalling, however, calls for a multiregister. At the call setting stage, a speech channel is connected through the centre to an access of multiregister which receives and sends the VF signals (in PCM form) of the register signalling and thus in this respect serve as an interface between the speech channel and the central unit. An object of the invention is to provide an improved signal transfer system of the above type.

According to the invention there is provided a signal transfer system for a time division switching centre, including at least one PCM multiplex highway carrying a signalling channel and speech channels, a line signalling controller associated with that highway having a signalling memory arranged to store line signalling information received from the signalling channel in a cell peculiar to each speech channel, at least one multiregister for receiving the register signalling of a speech channel which is connected to it in the register phase of a connection, a connection network permitting selective connection of the speech channels to one another and to the multiregister, and a central control unit having access to the signalling controller, to the multiregister and to the connection network, wherein the transfer system transfers the line signalling of a speech channel in register phase from the signalling controller to the multiregister, and wherein the transfer system comprises in the line signalling controller, a marking memory with one cell per speech channel arranged for storing a bit supplied by the central unit, wherein said stored bits each have a specific value when the speech channel is in register phase, wherein means is provided for reading, in relation to a bit time slot of each speech channel, the signalling memory cell and the marking memory cell peculiar to a speech channel, wherein switching means is controlled by the bit from the marking memory cell, when it has the said specific value, to switch onto the multiplex highway instead of a bit from the speech channel, a line signalling bit coming from the signalling memory cell and wherein the multiregister includes means for selecting the said signalling bit in the information transmitted by the corresponding speech channel, so that the multiregister receives in this way at the same time for this speech channel the line signalling and the register signalling information.

Such a system permits transfer in both directions the line signalling of a speech channel at the register signalling stage - in other words in register phase - between the corresponding signalling channel and the multiregister, so that the multiregister is the only interface in the signalling exchanges concerning this speech channel. This causes a simplification of signal processing in the central unit which has only one interlocutor instead of two. A greater flexibility in the distribution of the signalling functions follows from this, since the multiregister, having all the signalling information can then be granted greater autonomy.

Since the signalling channel carries several line signalling bits for the speech channel in the multiframe time, while the transfer made by the above-mentioned means concerns one signalling bit per frame, additional means are provided for successive transfer of the line signalling bits. In a preferred form of embodiment these additional means are arranged to constitute a 16-bit line signalling transfer message, i.e. having as many bits as the multiframe has frames, this message containing the line signalling bits as well as the format bits facilitating identification.

Embodiments of the invention will now be described with reference to the accompanying drawings which show: Figure 1 is a simplified diagram of a time division switching centre to which the invention can be applied.

Figure 2 is an explanatory diagram of the principle of the transfer system of the invention.

Figure 3 is a schematic diagram of an embodiment of the invention.

Figure 4 is a schematic diagram of arrangements to be added to circuit CJ of Figure 3 to deal with 16 bit message line signalling transfer.

Figure 5 is a schematic diagram of arrangements to be added to multiregister MR of Figure 3 for receiving messages formed by the arrangements of Figure 4.

Figure 1 shows a time division switching centre in which the present invention is usable. The PCM highways are connected to this centre, which sets up calls between the TDM channels carried by these highways.

Each highway jme comprises a digital transmission channel for each transmission direction. It is connected in the switching centre to an individual highway equipment JE which solves the synchronization problems so that, at the level of equipment JE, two transmission channels, incoming and outgoing, appear as synchronized on a local reference frame.

The highway equipment is connected to a highway control circuit CJ itself connected by a linkcje to a central unit UC. The central unit UC controls directly or indirectly all the operations performed in the switching centre, whether they concern setting up, holding, releasing of calls, signalling exchanges or all accessory functions. It is a stored program digital processor. The circuit CJ can be regarded as a peripheral sub-unit of central unit UC giving the central unit access to the PCM highways.

In signalling matters, circuit CJ comprises means for receiving from the equipment JE the incoming line signalling information from highway jme, means for storing this information and means for transmitting it to the central unit UC. It also comprises means for receiving from the central unit UC line signalling information to transmit, means for storing this information and means for retransmitting it on the outgoing channel of highway jme. For line signalling, circuit CJ therefore acts as a line signalling controller, interface equipment between the external highway jme and the central unit UC.

The equipment JE is connected by a bothway internal highway jmi to the connecting network RCX. Other internal highways (jmi jmr) are connected to the network RCX.

This network is controlled by the central unit UC through link crx and, according to the orders it receives from the central unit UC, it sets up bothway connections between the channels of highways.

The switching centre also comprises at least a multiregister highway equipment JMR coupled to network RCX by the both- way internal highway jmr. This equipment plays approximately the same role as the equipment JE, although in a simplified form, since it has no access to an external highway.

It is connected to a multiregister MR, itself connected to the central unit UC by a link cmr.

The essential function of multiregister MR is register signalling exchange. A time division channel of a highway such asjme, when it is seized to set up a call, which gives rise to an exchange of signals in the framwork of line signalling, is connected to a channel of highwayjmr. Equipment JMR gives multireregister MR access to this channel for sending and receiving the register signalling. In these register signalling. In these register signaling operations, multiregister MR plays a role of interface between the central unit UC and each of the channels of highway jmr.

Register signalling is usually done by transmission of voice frequency signals on the speech channel. On the bothway channel of highwayjmr, these signals are transmitted as PCM samples. Multiregister MR therefore has the function, for each of the channels of highway jmr, of generating and transmitting these PCM samples and of recognizing the VF signals to which they correspond, to specify their reception to the central unit UC.

During this time, line signalling is continued.

When register signalling exchanges concerning a TDM channel of an external highway are terminated, this channel is disconnected from the channel of highway jmr to which is was connected, and thus from multireregister MR; it can then be connected to a channel of another external highway (or the same one) for call setting. The call will no longer be controlled except by signal exchanges made in the framework of line signalling.

Thus the central unit UC exchanges line signalling with external highways by highway control circuits (CJ) and register signalling through multiregister(s) (MR). As shown previously, it is desirable that at all times the central unit has only one signalling exchange path for each call channel.

For this purpose, in the present system means is used when a TDM channel of an external highway is connected to an access of a multiregister to send the line signalling of this channel of the highway to the highway to the multiregister and reciprocally. Thus, the multiregister will be the only interface between the central unit and the TDM channel as long as this is in register phase.

We now refer to Figure 2 to describe the principle of signalling information transfer.

The upper line TT shows the slicing of time t in order to constitute a TDM frame of 32 time slots of equal lengths called ITO to IT31. The frame time is 125,u and that of each time slot is 3.9 ,us. In the case of the CEPT type PCM highway slot ITO is reserved for frame synchronization and IT16 is used for signalling information transmission. The other 30 slots are each used as a speech channel medium. The following line IT16/IT17 of Figure 2 shows the time slicing t which permits in each slot to transmit 8 bits successively called bl to b8; they concern only IT16 and IT17.

Lines TTO to TT15 show the information transmitted by IT16 and IT17 during 16 successive frames forming a multiframe. IT16 reserved for line signalling is considered first.

In the case of channel-by-channel signalling to which this invention applies, IT16 successively carries, in frame TTO, a synchronizing combination "OOOOwxyz" then, in frames TTO to TT15, the line signalling information of the 30 speech channels, at the rate of two groups of 4 bits corresponding to two channels of ranks i and i + 16 per IT16, i being the number of the frame in the multiframe.

The four signalling bits of each channel are designated by the letters A, B, C, D followed by the number of the speech channel to which they are assigned.

Referring also to Figure 1, the control circuit CJ, in the signalling reception function, should sample in equipment JE the information supplied by IT16, identify the framing combination "0000wxyz" then store in a 30 cell signalling memory the 30 groups of 4 bits that follow the synchronizing combination.

The line signalling information is thus kept at the disposal of the central unit UC which can request it only once per multiframe, i.e. once every 2 ms.

The principle consists in providing means for transferring signalling information of the channels in register phase in the direction of the multiregister by one of the bit slots of the speech channel. As an example, we consider the speech channel carried by IT17. The transfer is made by bit b8 of this IT17. As shown by lines TT0 to TT15 of Figure 2, 16 bits can thus be transferred in the slot IT17 of the 16 frames of the signalling multiframe. If the signalling channel carried by slot IT16 supplies only one bit per multiframe, this bit can be transferred in a repetive way, 16 times per multiframe by bit b8 of IT17. Since it supplies several bits, however, a cyclic transfer of the bits received (A, B, C, D, A, B, etc.

...) can be foreseen. In preference we transfer a 16-bit message comprising format bits, others which are available for other purposes and the four signalling bits received in the multiframe.

In Figure 2, this message is shown under the slot corresponding to bit b8 of IT17. It comprises 0's, in frames TT0, TT1, etc. 1's in TT8, etc.... and the four signalling bits A17, C17, D17 of the channel carried by IT17, as they have been received in IT16 of frame TT1 and stored in the signalling memory; they are transferred in frames TT12 to Tut15.

Multiregister MR receives this message, and identifies its various parts and especially bits A17 to D17 that it can store in a cell of a signalling memory in order to place them at the disposal of the central unit UC.

If now signalling transmission is considered instead of signalling reception, the principle still applies, by similar means, the direction of transmission being reversed. The central unit supplies to the multiregister the four bits to be transmitted. This multiregister composes and transmits a 16 bit message using bit b8 of the speech channel, in the outgoing direction. These bits arrive in equipment JE in IT17; there they are sampled by transfer means which writes the four line signalling bits in the signalling memory cell assigned to this IT17 for them to be sent onto junctionjmr during IT16 of frame TT1.

The transfer of the line signalling on bit b 8 of the speech channel does not hinder register signalling. Indeed this bit b8 is the least significant bit of the combination transmitted by each IT. Now, the register signalling gives rise to narrow band VF signal transmission, whose samples can, with no great loss of performance, be represented by combinations coded at only 7 bits per 8 bit coding and with abandon of the least significant bit. Thus in register phase the multiregister simultaneously carries out register signalling exchanges on bits bl to b7 of the speech channel and line signalling exchanges on bitb8 as briefly described.

We now describe with reference to Figure 3 the essential means provided for implementing this line signalling transfer. Figure 3 shows only the means used in the receiving direction, similar means being provided in the transmission direction.

Highways jme, jmi, jmr, equipment JE, JRM, circuit CJ, network RCX and multiregister MR of Figure 1 are seen in Figure 3.

In circuit CJ, a signalling memory MSR and a marking memory MKJ are shown.

Memory MSR has at least one cell per speech channel of highwayjme. Each cell is provided for recording signalling information received from highway jme and assigned to a specific speech channel. This information reaches the highway by link rsj and is recorded due to an order referenced IT16, TTi. This order, coming from a clock (not shown) like all the other orders of the same type relating to time division slicing, specifies that the information supplied on link rsj during IT16 should be recorded in two addresses derived from row TTi of the frame in the multiframe. It will be remembered that an IT16 of frame TTi supplies signalling information from two speech channels carried by ITi and ITi + 16.Hence the control circuits of memory MSR are to write in successively the first four bits of IT16 in address cell i, then the next four bits in address cell i + 16.

The signalling information stored in this way is available for the central unit which can read it by link cje by sending an appropriate order on line cl (address, reading order) and receive the information read on line Pi. In addition, memory MSR is read at each IT due to an order ITn, b8 supplied during bit b8 of the IT, the address being the frame.

The signalling information read is supplied on the conductor bts.

Memory MKJ has one cell per speech channel of highwayjme. Each cell contains at least one bit written in by central unit UC via line ml of link cje (address, writing order and information to be written). Normally, this bit has the value 0, but the central unit UC writes a 1 when the speech channel is connected to the multiregister MR. It writes an O again when the speech channel is disconnected from the multiregister. Memory MKJ is read at each IT, due to order ITn, b 8, at the same time as memory MSR. The marking bit thus obtained is transmitted on conductor sts: it is 1 only for speech channels in register phase and during the time slot reserved for bit b8.

Normally, conductorsts is at level 0, AND gate pts is inhibited, and NOT circuit its supplies a signal which unblocks gate ptd. The output on the exchange side of equipment JE is therefore connected by AND gateptd and OR gate pm, to the receiving channel of the internal highway jmi and to network RCX.

Thus for any channel not in register phase, the signalling transfer means has no effect, as the output of equipment JE remains connected to the internal highway jmi and to network RCX.

However, for a speech channel in register phase, during the ITn carrying this channel, but only during the period reserved for bit b 8 of this IT, conductor sts is set to level l. Then the NOT circuit its blocks gateptd, while gate pts is unblocked. The signalling information from memory MSR and present at this moment on conductor bts is thus transmitted by gatespts and pom on highwayjmi. It takes the place of bit b8 of the combination supplied in this ITn by equipment JE, coming from highway jme, this in application of the above described principle.

In multiregister MR a signalling memory MSL and a register signalling processing circuit TMSE are shown. The latter does not form part of the invention and will not be described. With respect to it only links le and ce have been mentioned by which central unit UC obtains knowledge of the signals received within the framework of the register signalling. Memory MSL possesses, like memory MSR, one cell per TDM channel, but for channels of highway jmr. The channels connected to the multiregister MR are all in register phase and the transfer of line signalling is in operation; there is therefore no need for a marking memory.

During the period corresponding to bit b8 of each IT of highway jmr, an order ITp, b8 (address, writing order) causes recording of the line signalling information transferred as described above, and appearing on conductor rse in the appropriate memory cell.

Central unit UC obtains knowledge of this information, by lines Is and cs, just as in memory MSL. This information can be added to that supplied, for the same TDM channel, by circuit TMSE. In addition, since multiregister MR has at the same time at its disposal line and register signals, it can combine them itself to present them to the UC in an integrated way, or even carry out certain processing or signalling operations, autonomously, without using the central unit. This forms part of the advantages provided by the invention.

The arrangement described with reference to Figure 3 permits therefore, in the external highway-multiregister direction, transferring the line signalling in register phase by simple means since they comprise only a memory with one bit per time division channel, some gates at the level of the PCM highway and a line signalling store in the multiregister. It has been noted that the signalling transfer between memories MSR and MSL is performed at the rate of one bit per frame with no other details. This can suffice if the line signalling recorded in memory MSR only comprises one bit per multiframe. This bit is then transferred 16 times in this way, which is redundant but costs nothing.It would also be quite possible to transfer in this way two bits in alternation, by providing a frame by frame alternate circuit at the output of memory MSR and input of memory MSL and even to do a time division multiplexing of the four line signalling bits of the CEPT, for instance.

Preferably this transfer of several bits of line signalling per speech channel is effected in a message made up for instance according to the format described in relation to Figure 2, i.e. a 16 bit message transmitted in a 16 frame multiframe, at the rate of one bit per frame using bit b8 of each IT assigned to the speech channel in question. The means required for this purpose are described, as an example, by Figure 4 which shows only the supplementary means added in circuit CJ of Figure 3 and by Figure 5 which shows only the supplementary means to be added to multiregister MR of Figure 3.

In circuit CJ, as can be seen on Figure 4, these means comprise a counter CT and a multiplexer MUX. Counter CT, cleared by a signal TTO at the beginning of the multif rame then increments at each ITO. It has four stages ct 0/2 and ct 3 and counts the 16 frames of the multiframe. Multiplexer MUX is a circuit which connects one of its inputs located on the left to its sole output located on the right according to address adt which it receives from stagesct 0/2 of counter CT and providing it also receives an enabling signal val from stage ct3 of counter CT.

In this case, signalling memory MSR (Fig.

3) has four outputs and supplies to bit b 8 of each IT, the four signalling bits received for the benefit of the channel carried by this IT.

The multiplexer MUX inserts itself between these four outputs and conductor bts serving for the line signalling transfer (see again Figure 3). The operation corresponds to the message already described with respect to Figure 2: 0000 0000 1111 ABCD This format is determined by counter CT.

During the first eight frames of the multiframe, stage ct3 of counter CT remains at 0.

Multiplexer MUX is not enabled, and conductor bts remains at 0. For any channel in register phase the transferred signalling bit is 0. Signalling messages thus start by 8 bits 0.

Then, stage ct3 passes to 1 and enables the multiplexer which then connects, frame by frame, conductor bts first of all to the four inputs connected to level 1, then to the four inputs connected in sequence to the outputs supplying signalling bits A, B, C, D of memory MSR. Due to this, for any signalling channel in register phase, the transferred signalling message continues by four I's, then by signalling bits A, B, C, D.

In the multiregister MR, the additional means provided, according to Figure 5, comprise a memory MKS recording a 16 bit word per time division channel, a shift register RFS and some gates. For each TDM channel, memory MKS is read by the order of a signal ITp,b7 (address, reading order) and the information read is written in register RFS by order b7. During the period corresponding to bit b 8 which immediately follows this reading, signal b8 orders input of the bit present on conductor rse (see Figure 3) in register RFS, by shifting one step to the left. Then, by the order of signal ITp,bl (same address as the reading temporarily saved by means not shown, writing order) the contents of register RFS are recorded in the previously read location.These means permit updating, in register RFS, for each channel of highway jmr, when the bit 8 carrying the line signalling reaches multiregister MR, a state of the last 16 signalling bits received. Once every 16 frames, register RFS contains, for a given channel, a complete signalling transfer message. The control gate pcf, of the OR type receiving 8 bits 0 supplies a level 0 supplies a level 0 and NOT circuit idf which follows at level 1. Gatepct of AND type supplies a level 1 which unblocks a gate pcl controlling the transmission of signal bl (bit bl of the next TDM channel) serving for a writing order in memory MSL. The address is ITp', that of the channel whose IT has just ended. The information to be written in is supplied by the four righthand stages of register RFS and is formed of the four signalling bits A, B, C, D.

Thus, the line signalling information transferred as has been described, is written in memory MSL, at the disposal of the central unit UC, or for the purpose of any processing in multiregister MR as was previously shown with respect to Figure 3.

The transfer of line signalling in the other transmission direction calls for similar means, those of figure 4 coming to complete multiregister MR (Figure 3), with respect to an outgoing signalling memory similar to MSL, in which the signals to be transmitted are prepared and those of Figure 5 coming to complete control circuit CJ, with respect to a line signalling sending memory similar to MSR, in which the signalling bits to be transmitted on the external highway jme will be written.

The preceding description is only by way of example and numerous alternatives can be foreseen. To mention only a few, the operational mode of the memories depends on the technology chosen, and this also applies for the switching operations concerned, i.e.

types of gates and logic levels. The compromise between the memory and logic means can be modified for performing certain functions, thus the arrangement of Figure 5 which requires a 16 bit time division channel memory, but few logic circuits, could be replaced by a smaller memory recording a time division channel message receiving sequential, at the cost of more sophisticated logic circuits responsible for advancing this sequential according to the signals received. All the data, codes and formats given can finally vary according to the application.

WHAT WE CLAIM IS: 1. A signal transfer system for a time division switching centre, including at least one PCM multiplex highway carrying a signalling channel and speech channels, a line signalling controller associated with that highway having a signalling memory arranged to store line signalling information received from the signalling channel in a cell peculiar to each speech channel, at least one multiregister for receiving the register signalling of a speech channel which is connected to it in the register phase of a connection, a connection network permitting selective connection of the speech channels to one another and to the multiregister, and a central control unit having access to the signalling controller, to the multiregister and to the connection network, wherein the transfer system transfers the line signalling of a speech channel in register phase from the signalling controller to the multiregister, and wherein the transfer system comprises in the line signalling controller, a marking memory with one cell per speech channel arranged for storing a bit supplied by the central unit, wherein said stored bits each have a specific value when the speech channel is in register phase, wherein means is provided for reading, in relation to a bit time slot of each speech channel, the signalling memory cell and the marking memory cell peculiar to a speech channel, wherein switching means is controlled by the bit from the marking memory cell, when it has the said specific value, to switch onto the multiplex highway instead of a bit from the speech channel, a line signalling bit coming from the signalling memory cell and wherein the multiregister includes means for selecting the said signalling bit in the information transmitted by the corresponding speech channel, so that the multiregister receives in this way at the same time for this speech channel the line signalling and the register signalling information.

2. A system according to claim 1, and which comprises similar means for transmission of line signalling from the multiregister, in the opposite transmission direction.

3. A system according to claim 1 or 2, and which includes frame counting means between the output of the signalling memory and the switching means and arranged to permit successive transfer of several signalling bits in several successive frames according to the position of the frame counting means.

4. A system according to claim 3, and wherein the frame counting means comprise a counter having as many positions as there are frames in the transmission period on the PCM multiplex highway signalling channel.

5. A system according to claim 4, and wherein the selection means are arranged to select and permit transferring, in addition to the signalling bits coming from the signalling memory, additional bits having predetermined values, which constitutes a signalling message.

6. A system according to claims 3, 4 or 5 and which comprises similar means to those of claims 3, 4 or 5 for the transmission of line signalling from the multiregister.

7. A system according to any one of the preceding claims and wherein the bit time slot during which the line signalling transfer is made is that of the least significant bit in the speech channel time slot.

8. A signal transfer system for a time

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (8)

**WARNING** start of CLMS field may overlap end of DESC **. frames, register RFS contains, for a given channel, a complete signalling transfer message. The control gate pcf, of the OR type receiving 8 bits 0 supplies a level 0 supplies a level 0 and NOT circuit idf which follows at level 1. Gatepct of AND type supplies a level 1 which unblocks a gate pcl controlling the transmission of signal bl (bit bl of the next TDM channel) serving for a writing order in memory MSL. The address is ITp', that of the channel whose IT has just ended. The information to be written in is supplied by the four righthand stages of register RFS and is formed of the four signalling bits A, B, C, D. Thus, the line signalling information transferred as has been described, is written in memory MSL, at the disposal of the central unit UC, or for the purpose of any processing in multiregister MR as was previously shown with respect to Figure 3. The transfer of line signalling in the other transmission direction calls for similar means, those of figure 4 coming to complete multiregister MR (Figure 3), with respect to an outgoing signalling memory similar to MSL, in which the signals to be transmitted are prepared and those of Figure 5 coming to complete control circuit CJ, with respect to a line signalling sending memory similar to MSR, in which the signalling bits to be transmitted on the external highway jme will be written. The preceding description is only by way of example and numerous alternatives can be foreseen. To mention only a few, the operational mode of the memories depends on the technology chosen, and this also applies for the switching operations concerned, i.e. types of gates and logic levels. The compromise between the memory and logic means can be modified for performing certain functions, thus the arrangement of Figure 5 which requires a 16 bit time division channel memory, but few logic circuits, could be replaced by a smaller memory recording a time division channel message receiving sequential, at the cost of more sophisticated logic circuits responsible for advancing this sequential according to the signals received. All the data, codes and formats given can finally vary according to the application. WHAT WE CLAIM IS:

1. A signal transfer system for a time division switching centre, including at least one PCM multiplex highway carrying a signalling channel and speech channels, a line signalling controller associated with that highway having a signalling memory arranged to store line signalling information received from the signalling channel in a cell peculiar to each speech channel, at least one multiregister for receiving the register signalling of a speech channel which is connected to it in the register phase of a connection, a connection network permitting selective connection of the speech channels to one another and to the multiregister, and a central control unit having access to the signalling controller, to the multiregister and to the connection network, wherein the transfer system transfers the line signalling of a speech channel in register phase from the signalling controller to the multiregister, and wherein the transfer system comprises in the line signalling controller, a marking memory with one cell per speech channel arranged for storing a bit supplied by the central unit, wherein said stored bits each have a specific value when the speech channel is in register phase, wherein means is provided for reading, in relation to a bit time slot of each speech channel, the signalling memory cell and the marking memory cell peculiar to a speech channel, wherein switching means is controlled by the bit from the marking memory cell, when it has the said specific value, to switch onto the multiplex highway instead of a bit from the speech channel, a line signalling bit coming from the signalling memory cell and wherein the multiregister includes means for selecting the said signalling bit in the information transmitted by the corresponding speech channel, so that the multiregister receives in this way at the same time for this speech channel the line signalling and the register signalling information.

2. A system according to claim 1, and which comprises similar means for transmission of line signalling from the multiregister, in the opposite transmission direction.

3. A system according to claim 1 or 2, and which includes frame counting means between the output of the signalling memory and the switching means and arranged to permit successive transfer of several signalling bits in several successive frames according to the position of the frame counting means.

4. A system according to claim 3, and wherein the frame counting means comprise a counter having as many positions as there are frames in the transmission period on the PCM multiplex highway signalling channel.

5. A system according to claim 4, and wherein the selection means are arranged to select and permit transferring, in addition to the signalling bits coming from the signalling memory, additional bits having predetermined values, which constitutes a signalling message.

6. A system according to claims 3, 4 or 5 and which comprises similar means to those of claims 3, 4 or 5 for the transmission of line signalling from the multiregister.

7. A system according to any one of the preceding claims and wherein the bit time slot during which the line signalling transfer is made is that of the least significant bit in the speech channel time slot.

8. A signal transfer system for a time

division switching system, substantially as described with reference to the accompanying drawings.