FI891784L - Laite ja menetelmä sivutettuun muistiin pääsemiseksi tietokonejärjestelmässä - Google Patents

Laite ja menetelmä sivutettuun muistiin pääsemiseksi tietokonejärjestelmässä Download PDF

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Publication number
FI891784L
FI891784L FI891784A FI891784A FI891784L FI 891784 L FI891784 L FI 891784L FI 891784 A FI891784 A FI 891784A FI 891784 A FI891784 A FI 891784A FI 891784 L FI891784 L FI 891784L
Authority
FI
Finland
Prior art keywords
accessing
computer system
paged memory
paged
memory
Prior art date
Application number
FI891784A
Other languages
English (en)
Swedish (sv)
Other versions
FI95971C (fi
FI891784A0 (fi
FI95971B (fi
Inventor
Patrick Maurice Bland
Mark Edward Dean
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of FI891784A0 publication Critical patent/FI891784A0/fi
Publication of FI891784L publication Critical patent/FI891784L/fi
Application granted granted Critical
Publication of FI95971B publication Critical patent/FI95971B/fi
Publication of FI95971C publication Critical patent/FI95971C/fi

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/20—Software design
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/70—Software maintenance or management
    • G06F8/71—Version control; Configuration management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • Dram (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Memory System (AREA)
  • Hardware Redundancy (AREA)
  • Bus Control (AREA)
FI891784A 1988-05-26 1989-04-14 Laite ja menetelmä sivutettuun muistiin pääsemiseksi tietokonejärjestelmässä FI95971C (fi)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US19672188 1988-05-26
US07/196,721 US5034917A (en) 1988-05-26 1988-05-26 Computer system including a page mode memory with decreased access time and method of operation thereof

Publications (4)

Publication Number Publication Date
FI891784A0 FI891784A0 (fi) 1989-04-14
FI891784L true FI891784L (fi) 1989-11-27
FI95971B FI95971B (fi) 1995-12-29
FI95971C FI95971C (fi) 1996-04-10

Family

ID=22726583

Family Applications (1)

Application Number Title Priority Date Filing Date
FI891784A FI95971C (fi) 1988-05-26 1989-04-14 Laite ja menetelmä sivutettuun muistiin pääsemiseksi tietokonejärjestelmässä

Country Status (24)

Country Link
US (1) US5034917A (fi)
EP (1) EP0343769B1 (fi)
JP (1) JPH06101225B2 (fi)
KR (1) KR920010950B1 (fi)
CN (1) CN1010809B (fi)
AT (1) ATE125058T1 (fi)
BE (1) BE1003816A4 (fi)
BR (1) BR8902399A (fi)
CA (1) CA1319201C (fi)
DE (2) DE68923403T2 (fi)
DK (1) DK189589A (fi)
ES (1) ES2075045T3 (fi)
FI (1) FI95971C (fi)
GB (1) GB2219418A (fi)
HK (1) HK23896A (fi)
IT (1) IT1230189B (fi)
MX (1) MX167244B (fi)
MY (1) MY104737A (fi)
NL (1) NL8901237A (fi)
NO (1) NO891581L (fi)
NZ (1) NZ228610A (fi)
PH (1) PH30402A (fi)
PT (1) PT90631B (fi)
SE (1) SE8901304L (fi)

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JPH07248963A (ja) * 1994-03-08 1995-09-26 Nec Corp Ｄｒａｍ制御装置
JPH08314795A (ja) * 1994-05-19 1996-11-29 Hitachi Ltd 記憶装置の読み出し回路及び記憶システム
AU703750B2 (en) * 1994-10-14 1999-04-01 Compaq Computer Corporation Easily programmable memory controller which can access different speed memory devices on different cycles
US5701143A (en) * 1995-01-31 1997-12-23 Cirrus Logic, Inc. Circuits, systems and methods for improving row select speed in a row select memory device
USRE36532E (en) * 1995-03-02 2000-01-25 Samsung Electronics Co., Ltd. Synchronous semiconductor memory device having an auto-precharge function
WO1996029652A1 (en) * 1995-03-22 1996-09-26 Ast Research, Inc. Rule-based dram controller
US5666494A (en) * 1995-03-31 1997-09-09 Samsung Electronics Co., Ltd. Queue management mechanism which allows entries to be processed in any order
US5638534A (en) * 1995-03-31 1997-06-10 Samsung Electronics Co., Ltd. Memory controller which executes read and write commands out of order
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US5765203A (en) * 1995-12-19 1998-06-09 Seagate Technology, Inc. Storage and addressing method for a buffer memory control system for accessing user and error imformation
US6209071B1 (en) 1996-05-07 2001-03-27 Rambus Inc. Asynchronous request/synchronous data dynamic random access memory
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US6052756A (en) * 1998-01-23 2000-04-18 Oki Electric Industry Co., Ltd. Memory page management
JPH11272606A (ja) * 1998-03-19 1999-10-08 Fujitsu Ltd バス制御装置
US6643752B1 (en) * 1999-12-09 2003-11-04 Rambus Inc. Transceiver with latency alignment circuitry
US7404032B2 (en) * 2000-01-05 2008-07-22 Rambus Inc. Configurable width buffered module having switch elements
US7356639B2 (en) * 2000-01-05 2008-04-08 Rambus Inc. Configurable width buffered module having a bypass circuit
US6502161B1 (en) 2000-01-05 2002-12-31 Rambus Inc. Memory system including a point-to-point linked memory subsystem
US7363422B2 (en) * 2000-01-05 2008-04-22 Rambus Inc. Configurable width buffered module
US20050010737A1 (en) * 2000-01-05 2005-01-13 Fred Ware Configurable width buffered module having splitter elements
US7266634B2 (en) * 2000-01-05 2007-09-04 Rambus Inc. Configurable width buffered module having flyby elements
US7017002B2 (en) * 2000-01-05 2006-03-21 Rambus, Inc. System featuring a master device, a buffer device and a plurality of integrated circuit memory devices
US6829184B2 (en) * 2002-01-28 2004-12-07 Intel Corporation Apparatus and method for encoding auto-precharge
US7315928B2 (en) * 2005-02-03 2008-01-01 Mediatek Incorporation Apparatus and related method for accessing page mode flash memory
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US8253751B2 (en) * 2005-06-30 2012-08-28 Intel Corporation Memory controller interface for micro-tiled memory access
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US8878860B2 (en) * 2006-12-28 2014-11-04 Intel Corporation Accessing memory using multi-tiling
US9773533B2 (en) 2013-06-06 2017-09-26 Etron Technology, Inc. Memory with low current consumption and method for reducing current consumption of a memory
CN113361683B (zh) * 2021-05-18 2023-01-10 山东师范大学 一种生物仿脑存储方法及系统

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Also Published As

Publication number Publication date
BE1003816A4 (fr) 1992-06-23
MY104737A (en) 1994-05-31
DE3909896A1 (de) 1989-11-30
GB2219418A (en) 1989-12-06
SE8901304L (sv) 1989-11-27
IT1230189B (it) 1991-10-18
FI95971C (fi) 1996-04-10
IT8920624A0 (it) 1989-05-24
BR8902399A (pt) 1990-01-16
CA1319201C (en) 1993-06-15
HK23896A (en) 1996-02-16
DK189589A (da) 1989-11-27
EP0343769B1 (en) 1995-07-12
DK189589D0 (da) 1989-04-19
US5034917A (en) 1991-07-23
DE68923403T2 (de) 1996-03-07
EP0343769A2 (en) 1989-11-29
CN1037983A (zh) 1989-12-13
DE68923403D1 (de) 1995-08-17
NL8901237A (nl) 1989-12-18
PT90631A (pt) 1989-11-30
PT90631B (pt) 1994-10-31
PH30402A (en) 1997-05-08
SE8901304D0 (sv) 1989-04-11
EP0343769A3 (en) 1992-04-29
MX167244B (es) 1993-03-11
FI891784A0 (fi) 1989-04-14
JPH0223591A (ja) 1990-01-25
GB8904917D0 (en) 1989-04-12
KR890017611A (ko) 1989-12-16
NZ228610A (en) 1991-03-26
NO891581D0 (no) 1989-04-18
JPH06101225B2 (ja) 1994-12-12
ATE125058T1 (de) 1995-07-15
KR920010950B1 (ko) 1992-12-24
CN1010809B (zh) 1990-12-12
NO891581L (no) 1989-11-27
FI95971B (fi) 1995-12-29
ES2075045T3 (es) 1995-10-01
DE3909896C2 (fi) 1990-09-20

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Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION