DE69325473D1 - Virtuelles Speichersystem verwendendes Datenverarbeitungssystem und -verfahren - Google Patents

Virtuelles Speichersystem verwendendes Datenverarbeitungssystem und -verfahren

Info

Publication number
DE69325473D1
DE69325473D1 DE69325473T DE69325473T DE69325473D1 DE 69325473 D1 DE69325473 D1 DE 69325473D1 DE 69325473 T DE69325473 T DE 69325473T DE 69325473 T DE69325473 T DE 69325473T DE 69325473 D1 DE69325473 D1 DE 69325473D1
Authority
DE
Germany
Prior art keywords
data processing
virtual storage
processing system
storage system
virtual
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69325473T
Other languages
English (en)
Other versions
DE69325473T2 (de
Inventor
Shinichiro Suzuki
Yoichiro Takeuchi
Tadashi Ishikawa
Ikuo Uchihori
Takayuki Yagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69325473D1 publication Critical patent/DE69325473D1/de
Publication of DE69325473T2 publication Critical patent/DE69325473T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69325473T 1992-01-20 1993-01-19 Virtuelles Speichersystem verwendendes Datenverarbeitungssystem und -verfahren Expired - Fee Related DE69325473T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP721892 1992-01-20
JP14752992A JP3590075B2 (ja) 1992-01-20 1992-06-08 仮想記憶方式のデータ処理装置及び方法

Publications (2)

Publication Number Publication Date
DE69325473D1 true DE69325473D1 (de) 1999-08-05
DE69325473T2 DE69325473T2 (de) 2000-01-20

Family

ID=26341486

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69325473T Expired - Fee Related DE69325473T2 (de) 1992-01-20 1993-01-19 Virtuelles Speichersystem verwendendes Datenverarbeitungssystem und -verfahren

Country Status (4)

Country Link
US (1) US6038631A (de)
EP (1) EP0552717B1 (de)
JP (1) JP3590075B2 (de)
DE (1) DE69325473T2 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3666258B2 (ja) * 1997-08-28 2005-06-29 セイコーエプソン株式会社 プリンタ
US6289445B2 (en) * 1998-07-21 2001-09-11 Lsi Logic Corporation Circuit and method for initiating exception routines using implicit exception checking
US6681322B1 (en) * 1999-11-26 2004-01-20 Hewlett-Packard Development Company L.P. Method and apparatus for emulating an instruction set extension in a digital computer system
US6594750B1 (en) * 1999-12-08 2003-07-15 Ati International Srl Method and apparatus for handling an accessed bit in a page table entry
US7191313B2 (en) * 2001-08-28 2007-03-13 Sony Corporation Microprocessor
GB0122120D0 (en) * 2001-09-13 2001-10-31 Koninkl Philips Electronics Nv Edge termination in MOS transistors
US6792516B2 (en) * 2001-12-28 2004-09-14 Intel Corporation Memory arbiter with intelligent page gathering logic
US6990604B2 (en) * 2001-12-28 2006-01-24 Storage Technology Corporation Virtual storage status coalescing with a plurality of physical storage devices
US7035984B2 (en) * 2001-12-31 2006-04-25 Intel Corporation Memory arbiter with grace and ceiling periods and intelligent page gathering logic
US6895460B2 (en) * 2002-07-19 2005-05-17 Hewlett-Packard Development Company, L.P. Synchronization of asynchronous emulated interrupts
US7971205B2 (en) * 2005-12-01 2011-06-28 International Business Machines Corporation Handling of user mode thread using no context switch attribute to designate near interrupt disabled priority status
US7734842B2 (en) * 2006-03-28 2010-06-08 International Business Machines Corporation Computer-implemented method, apparatus, and computer program product for managing DMA write page faults using a pool of substitute pages
US8904151B2 (en) * 2006-05-02 2014-12-02 International Business Machines Corporation Method and apparatus for the dynamic identification and merging of instructions for execution on a wide datapath
KR100843134B1 (ko) * 2006-09-15 2008-07-02 삼성전자주식회사 인터럽트 금지구간 처리 장치 및 방법과 페이지 고정 장치및 방법
US9134954B2 (en) * 2012-09-10 2015-09-15 Qualcomm Incorporated GPU memory buffer pre-fetch and pre-back signaling to avoid page-fault
JP5781716B2 (ja) * 2013-04-18 2015-09-24 株式会社日立製作所 計算機システム及び非同期レプリケーション管理方法
JP7249968B2 (ja) * 2020-03-09 2023-03-31 株式会社東芝 情報処理装置およびストレージ

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4589087A (en) * 1983-06-30 1986-05-13 International Business Machines Corporation Condition register architecture for a primitive instruction set machine
US4718008A (en) * 1986-01-16 1988-01-05 International Business Machines Corporation Method to control paging subsystem processing in a virtual memory data processing system during execution of critical code sections
US4868744A (en) * 1986-03-03 1989-09-19 International Business Machines Corporation Method for restarting a long-running, fault-tolerant operation in a transaction-oriented data base system without burdening the system log
US5218712A (en) * 1987-07-01 1993-06-08 Digital Equipment Corporation Providing a data processor with a user-mode accessible mode of operations in which the processor performs processing operations without interruption
US5148544A (en) * 1987-07-01 1992-09-15 Digital Equipment Corporation Apparatus and method for control of asynchronous program interrupt events in a data processing system
US5161227A (en) * 1989-11-13 1992-11-03 International Business Machines Corporation Multilevel locking system and method
US5237700A (en) * 1990-03-21 1993-08-17 Advanced Micro Devices, Inc. Exception handling processor for handling first and second level exceptions with reduced exception latency
US5778423A (en) * 1990-06-29 1998-07-07 Digital Equipment Corporation Prefetch instruction for improving performance in reduced instruction set processor
TW197505B (de) * 1991-03-07 1993-01-01 Digital Equipment Corp
US5307504A (en) * 1991-03-07 1994-04-26 Digital Equipment Corporation System and method for preserving instruction granularity when translating program code from a computer having a first architecture to a computer having a second reduced architecture during the occurrence of interrupts due to asynchronous events
JPH04306735A (ja) * 1991-04-04 1992-10-29 Toshiba Corp 非同期割込み禁止機構
US5483641A (en) * 1991-12-17 1996-01-09 Dell Usa, L.P. System for scheduling readahead operations if new request is within a proximity of N last read requests wherein N is dependent on independent activities

Also Published As

Publication number Publication date
US6038631A (en) 2000-03-14
JP3590075B2 (ja) 2004-11-17
DE69325473T2 (de) 2000-01-20
EP0552717A3 (en) 1994-09-14
EP0552717B1 (de) 1999-06-30
JPH05265861A (ja) 1993-10-15
EP0552717A2 (de) 1993-07-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee