KR930701794A - 데이타 프로세서 및 데이타 처리방법 - Google Patents

데이타 프로세서 및 데이타 처리방법

Info

Publication number
KR930701794A
KR930701794A KR1019920703157A KR920703157A KR930701794A KR 930701794 A KR930701794 A KR 930701794A KR 1019920703157 A KR1019920703157 A KR 1019920703157A KR 920703157 A KR920703157 A KR 920703157A KR 930701794 A KR930701794 A KR 930701794A
Authority
KR
South Korea
Prior art keywords
data
processing method
data processing
processor
data processor
Prior art date
Application number
KR1019920703157A
Other languages
English (en)
Other versions
KR0125623B1 (ko
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of KR930701794A publication Critical patent/KR930701794A/ko
Application granted granted Critical
Publication of KR0125623B1 publication Critical patent/KR0125623B1/ko

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • G06F15/17343—Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Multi Processors (AREA)
  • Advance Control (AREA)
KR1019920703157A 1991-04-09 1992-04-09 데이타 프로세서 및 데이타 처리방법 KR0125623B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP91-076574 1991-04-09
JP7657491 1991-04-09
PCT/JP1992/000447 WO1992018935A1 (en) 1991-04-09 1992-04-09 Data processor and data processing method

Publications (2)

Publication Number Publication Date
KR930701794A true KR930701794A (ko) 1993-06-12
KR0125623B1 KR0125623B1 (ko) 1998-07-01

Family

ID=13609021

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920703157A KR0125623B1 (ko) 1991-04-09 1992-04-09 데이타 프로세서 및 데이타 처리방법

Country Status (3)

Country Link
EP (1) EP0539595A4 (ko)
KR (1) KR0125623B1 (ko)
WO (1) WO1992018935A1 (ko)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4416881C2 (de) * 1993-05-13 1998-03-19 Pact Inf Tech Gmbh Verfahren zum Betrieb einer Datenverarbeitungseinrichtung
US6073185A (en) * 1993-08-27 2000-06-06 Teranex, Inc. Parallel data processor
WO1996008778A1 (en) * 1994-09-13 1996-03-21 Lockheed Martin Corporation Parallel data processor
US5943242A (en) * 1995-11-17 1999-08-24 Pact Gmbh Dynamically reconfigurable data processing system
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
DE19651075A1 (de) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Einheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen
US6338106B1 (en) 1996-12-20 2002-01-08 Pact Gmbh I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures
DE19654595A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
DE19654593A1 (de) * 1996-12-20 1998-07-02 Pact Inf Tech Gmbh Umkonfigurierungs-Verfahren für programmierbare Bausteine zur Laufzeit
DE59710317D1 (de) 1996-12-27 2003-07-24 Pact Inf Tech Gmbh VERFAHREN ZUM SELBSTÄNDIGEN DYNAMISCHEN UMLADEN VON DATENFLUSSPROZESSOREN (DFPs) SOWIE BAUSTEINEN MIT ZWEI- ODER MEHRDIMENSIONALEN PROGRAMMIERBAREN ZELLSTRUKTUREN (FPGAs, DPGAs, o.dgl.)
DE19654846A1 (de) 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Verfahren zum selbständigen dynamischen Umladen von Datenflußprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o. dgl.)
DE19704044A1 (de) * 1997-02-04 1998-08-13 Pact Inf Tech Gmbh Verfahren zur automatischen Adressgenerierung von Bausteinen innerhalb Clustern aus einer Vielzahl dieser Bausteine
DE19704728A1 (de) 1997-02-08 1998-08-13 Pact Inf Tech Gmbh Verfahren zur Selbstsynchronisation von konfigurierbaren Elementen eines programmierbaren Bausteines
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
DE19704742A1 (de) 1997-02-11 1998-09-24 Pact Inf Tech Gmbh Internes Bussystem für DFPs, sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen, zur Bewältigung großer Datenmengen mit hohem Vernetzungsaufwand
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (de) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
US6185667B1 (en) 1998-04-09 2001-02-06 Teranex, Inc. Input/output support for processing in a mesh connected computer
US6173388B1 (en) * 1998-04-09 2001-01-09 Teranex Inc. Directly accessing local memories of array processors for improved real-time corner turning processing
US6212628B1 (en) 1998-04-09 2001-04-03 Teranex, Inc. Mesh connected computer
DE19819569B4 (de) * 1998-04-30 2005-09-22 Siemens Ag Elektronischer Schaltkreis für die Umwandlung von Daten
DE10081643D2 (de) 1999-06-10 2002-05-29 Pact Inf Tech Gmbh Sequenz-Partitionierung auf Zellstrukturen
JP2004506261A (ja) 2000-06-13 2004-02-26 ペーアーツェーテー　イクスペーペー　テクノロジーズ　アクチエンゲゼルシャフト パイプラインｃｔプロトコルおよびｃｔ通信
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7657877B2 (en) 2001-06-20 2010-02-02 Pact Xpp Technologies Ag Method for processing data
US7996827B2 (en) * 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
WO2003060747A2 (de) 2002-01-19 2003-07-24 Pact Xpp Technologies Ag Reconfigurierbarer prozessor
EP2043000B1 (de) 2002-02-18 2011-12-21 Richter, Thomas Bussysteme und Rekonfigurationsverfahren
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
AU2003286131A1 (en) 2002-08-07 2004-03-19 Pact Xpp Technologies Ag Method and device for processing data
US7394284B2 (en) 2002-09-06 2008-07-01 Pact Xpp Technologies Ag Reconfigurable sequencer structure
EP1676208A2 (en) 2003-08-28 2006-07-05 PACT XPP Technologies AG Data processing device and method
US8250503B2 (en) 2006-01-18 2012-08-21 Martin Vorbach Hardware definition method including determining whether to implement a function as hardware or software
JP6308122B2 (ja) * 2014-12-16 2018-04-11 株式会社島津製作所 データ収集装置
US12013809B2 (en) * 2020-09-30 2024-06-18 Beijing Tsingmicro Intelligent Technology Co., Ltd. Computing array and processor having the same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6042516B2 (ja) * 1980-03-04 1985-09-24 日本電信電話株式会社 デ−タ処理装置
US4580215A (en) * 1983-03-08 1986-04-01 Itt Corporation Associative array with five arithmetic paths
US4942517A (en) * 1987-10-08 1990-07-17 Eastman Kodak Company Enhanced input/output architecture for toroidally-connected distributed-memory parallel computers
DE68926783T2 (de) * 1988-10-07 1996-11-28 Martin Marietta Corp Paralleler datenprozessor
GB8829624D0 (en) * 1988-12-20 1989-02-15 Amt Holdings Processor array

Also Published As

Publication number Publication date
WO1992018935A1 (en) 1992-10-29
KR0125623B1 (ko) 1998-07-01
EP0539595A1 (en) 1993-05-05
EP0539595A4 (en) 1994-07-20

Similar Documents

Publication Publication Date Title
KR930701794A (ko) 데이타 프로세서 및 데이타 처리방법
DE69424610D1 (de) Datenverarbeitungs-anlage und -verfahren
DE69211809D1 (de) Bilddatenverarbeitungsverfahren und -gerät
DE69230450D1 (de) Programmverarbeitungssystem und -verfahren
DE69230897D1 (de) Diskreter/invers-diskreter Cosinus-Transformationsprozessor und Datenverarbeitungsverfahren
DE69426138D1 (de) Bilddatenverarbeitungs-Einrichtung und -Verfahren
DE69332649D1 (de) Datenverarbeitungs- und Ausgabegerät
DE68918157D1 (de) Bildverarbeitungsverfahren und -vorrichtung.
DE69227726D1 (de) Bildverarbeitungsgerät und -Verfahren
DE69325415D1 (de) Datenverarbeitungsvorrichtung
DE69227533D1 (de) Bildverarbeitungsverfahren und -gerät
DE69230282D1 (de) Bildverarbeitungsverfahren und -vorrichtung
DE69229148D1 (de) Datenverarbeitungssystem und Verfahren
DE69321763D1 (de) Datenverarbeitungsverfahren und -vorrichtung
DE68928557D1 (de) Bildverarbeitungsgerät und -methode
DE69231053D1 (de) Datenverarbeitungssystem und -methode
DE4294540T1 (de) Datenverarbeitungssystem
DE69229771D1 (de) Datenverarbeitungsverfahren und -vorrichtung
DE69230901D1 (de) Graphisches Datenverarbeitungssystem und -verfahren
DE69219811D1 (de) Bildverarbeitungs-Einrichtung und -Verfahren
DE69222675D1 (de) Bildverarbeitungsverfahren und -vorrichtung
DE69232000D1 (de) Bildverarbeitungsverfahren und -gerät
DE69233681D1 (de) Datenverarbeitungsvorrichtung
DE69222584D1 (de) Bildverarbeitungsverfahren und -gerät
DE69220819D1 (de) Bildverarbeitungsverfahren und -gerät

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee