ES8800789A1 - Perfeccionamientos en un dispositivo transistor mos - Google Patents

Perfeccionamientos en un dispositivo transistor mos

Info

Publication number
ES8800789A1
ES8800789A1 ES557586A ES557586A ES8800789A1 ES 8800789 A1 ES8800789 A1 ES 8800789A1 ES 557586 A ES557586 A ES 557586A ES 557586 A ES557586 A ES 557586A ES 8800789 A1 ES8800789 A1 ES 8800789A1
Authority
ES
Spain
Prior art keywords
transistor
trench
surface area
trench transistor
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES557586A
Other languages
English (en)
Other versions
ES557586A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Publication of ES8800789A1 publication Critical patent/ES8800789A1/es
Publication of ES557586A0 publication Critical patent/ES557586A0/es
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66613Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Abstract

MODIFICACIONES EN UN DISPOSITIVO TRANSISTOR MOS. CONSISTENTES EN: INCLUIR, EN EL TRANSISTOR UNA CAPA DILECTRICA DE LA PUERTA QUE CUBRE EL SEGUNDO PARA DE PAREDES LATERALES, Y UN ELECTRODO (73) PUERTA DEL TRANSISTOR MOS QUE SE EXTIENDE A LO LARGO DEL SEGUNDO PAR DE PAREDES AL BORDE DE LA REGION DE LA FUENTE (77) Y SUPERPONIENDOSE EL OTRO BORDE DEL ELECTRODO PUERTA AL BORDE DE LA REGION DEL DRENADOR; QUE EL SEMICONDUCTOR ES SILICIO; QUE EL ELECTRODO PUERTA ES POLISILICIO.
ES557586A 1984-11-27 1987-06-11 Perfeccionamientos en un dispositivo transistor mos Expired ES8800789A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US67530584A 1984-11-27 1984-11-27

Publications (2)

Publication Number Publication Date
ES8800789A1 true ES8800789A1 (es) 1987-12-01
ES557586A0 ES557586A0 (es) 1987-12-01

Family

ID=24709896

Family Applications (2)

Application Number Title Priority Date Filing Date
ES549295A Expired ES8800512A1 (es) 1984-11-27 1985-11-26 Procedimiento para hacer un dispositivo transistor mos.
ES557586A Expired ES8800789A1 (es) 1984-11-27 1987-06-11 Perfeccionamientos en un dispositivo transistor mos

Family Applications Before (1)

Application Number Title Priority Date Filing Date
ES549295A Expired ES8800512A1 (es) 1984-11-27 1985-11-26 Procedimiento para hacer un dispositivo transistor mos.

Country Status (8)

Country Link
EP (1) EP0203146B1 (es)
JP (1) JPH0626251B2 (es)
KR (1) KR940005451B1 (es)
CA (1) CA1236932A (es)
DE (1) DE3570557D1 (es)
ES (2) ES8800512A1 (es)
IE (1) IE56967B1 (es)
WO (1) WO1986003341A1 (es)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01151268A (ja) * 1987-12-08 1989-06-14 Mitsubishi Electric Corp 半導体装置の製造方法
JP2661792B2 (ja) * 1989-05-12 1997-10-08 沖電気工業株式会社 電界効果トランジスタの製造方法
WO1990013918A1 (fr) * 1989-05-12 1990-11-15 Oki Electric Industry Co., Ltd. Transistor a effet de champ
JP2994670B2 (ja) * 1989-12-02 1999-12-27 忠弘 大見 半導体装置及びその製造方法
JP2790362B2 (ja) * 1990-06-04 1998-08-27 キヤノン株式会社 半導体装置
FR2720191B1 (fr) * 1994-05-18 1996-10-18 Michel Haond Transistor à effet de champ à grille isolée, et procédé de fabrication correspondant.
DE19743342C2 (de) * 1997-09-30 2002-02-28 Infineon Technologies Ag Feldeffekttransistor hoher Packungsdichte und Verfahren zu seiner Herstellung
FR2791810B1 (fr) * 1999-03-31 2001-06-22 France Telecom Procede de fabrication d'une heterostructure planaire
EP1091413A3 (en) * 1999-10-06 2005-01-12 Lsi Logic Corporation Fully-depleted, fully-inverted, short-length and vertical channel, dual-gate, cmos fet
US7282401B2 (en) 2005-07-08 2007-10-16 Micron Technology, Inc. Method and apparatus for a self-aligned recessed access device (RAD) transistor gate
US7867851B2 (en) 2005-08-30 2011-01-11 Micron Technology, Inc. Methods of forming field effect transistors on substrates
US7700441B2 (en) * 2006-02-02 2010-04-20 Micron Technology, Inc. Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates
US7602001B2 (en) 2006-07-17 2009-10-13 Micron Technology, Inc. Capacitorless one transistor DRAM cell, integrated circuitry comprising an array of capacitorless one transistor DRAM cells, and method of forming lines of capacitorless one transistor DRAM cells
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
JP5258230B2 (ja) * 2007-08-28 2013-08-07 セイコーインスツル株式会社 半導体装置の製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS506287A (es) * 1973-05-18 1975-01-22
JPS5499574A (en) * 1978-01-24 1979-08-06 Pioneer Electronic Corp Method of fabricating field effect transistor
US4296429A (en) * 1978-08-09 1981-10-20 Harris Corporation VMOS Transistor and method of fabrication
US4407058A (en) * 1981-05-22 1983-10-04 International Business Machines Corporation Method of making dense vertical FET's
US4419811A (en) * 1982-04-26 1983-12-13 Acrian, Inc. Method of fabricating mesa MOSFET using overhang mask
US4503598A (en) * 1982-05-20 1985-03-12 Fairchild Camera & Instrument Corporation Method of fabricating power MOSFET structure utilizing self-aligned diffusion and etching techniques

Also Published As

Publication number Publication date
DE3570557D1 (en) 1989-06-29
ES8800512A1 (es) 1987-11-16
ES549295A0 (es) 1987-11-16
EP0203146B1 (en) 1989-05-24
CA1236932A (en) 1988-05-17
KR940005451B1 (ko) 1994-06-18
IE852964L (en) 1986-05-27
KR880700473A (ko) 1988-03-15
ES557586A0 (es) 1987-12-01
JPS62500831A (ja) 1987-04-02
IE56967B1 (en) 1992-02-12
EP0203146A1 (en) 1986-12-03
JPH0626251B2 (ja) 1994-04-06
WO1986003341A1 (en) 1986-06-05

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