ES8405176A1 - Sistema de proceso de control de registro. - Google Patents
Sistema de proceso de control de registro.Info
- Publication number
- ES8405176A1 ES8405176A1 ES523751A ES523751A ES8405176A1 ES 8405176 A1 ES8405176 A1 ES 8405176A1 ES 523751 A ES523751 A ES 523751A ES 523751 A ES523751 A ES 523751A ES 8405176 A1 ES8405176 A1 ES 8405176A1
- Authority
- ES
- Spain
- Prior art keywords
- registers
- register
- memory
- processing system
- instruction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30101—Special purpose registers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/30138—Extension of register space, e.g. register cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Memory System (AREA)
Abstract
SISTEMA DE PROCESO DE CONTROL DE REGISTRO.INCLUYE: UNO O VARIOS REGISTROS REALES SITUADOS EN LA UNIDAD DE PROCESO; UN REGISTRO VIRTUAL QUE CORRESPONDE CON UNA RELACION DE 1:1 A DICHO REGISTRO REAL DISPUESTO EN LA MEMORIA; Y UN REGISTRO VIRTUAL QUE NO CORRESPONDE A DICHO REGISTRO REAL; UN DISPOSITIVO PARA DETECTAR LA INSTRUCCION DE CARGA O LA INTRUDCCINSTRUCCION DE ALMACENAMIENTO DE LOS REGISTROS; UN DISPOSITIVO PARA ESCRIBIR EL MISMO CONTENIDO EN AMBOS REGISTROS REAL Y VIRTUAL EN RESPUESTA A LA DETECCION DE LA INSTRUCCION DE CARGA; Y UN DISPOSITIVO PARA EFECTUAR LA LECTURASOLO A PARTIR DE DICHO REGISTRO VIRTUAL EN RESPUESTA A LA DETECCION DE UNA INSTRUCCION DE ALMACENAMIENTO.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57113470A JPS593642A (ja) | 1982-06-30 | 1982-06-30 | 制御レジスタ処理方式 |
Publications (2)
Publication Number | Publication Date |
---|---|
ES523751A0 ES523751A0 (es) | 1984-05-16 |
ES8405176A1 true ES8405176A1 (es) | 1984-05-16 |
Family
ID=14613061
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES523751A Expired ES8405176A1 (es) | 1982-06-30 | 1983-06-30 | Sistema de proceso de control de registro. |
Country Status (9)
Country | Link |
---|---|
US (1) | US4623962A (es) |
EP (1) | EP0098172B1 (es) |
JP (1) | JPS593642A (es) |
KR (1) | KR890000100B1 (es) |
AU (1) | AU546572B2 (es) |
BR (1) | BR8303527A (es) |
CA (1) | CA1200319A (es) |
DE (1) | DE3379848D1 (es) |
ES (1) | ES8405176A1 (es) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5960652A (ja) * | 1982-09-30 | 1984-04-06 | Fujitsu Ltd | デ−タ処理装置 |
US5249266A (en) * | 1985-10-22 | 1993-09-28 | Texas Instruments Incorporated | Data processing apparatus with self-emulation capability |
US5140687A (en) * | 1985-10-22 | 1992-08-18 | Texas Instruments Incorporated | Data processing apparatus with self-emulation capability |
US5293631A (en) * | 1991-08-06 | 1994-03-08 | Hewlett-Packard Company | Analysis and optimization of array variables in compiler for instruction level parallel processor |
US5666556A (en) * | 1993-12-30 | 1997-09-09 | Intel Corporation | Method and apparatus for redirecting register access requests wherein the register set is separate from a central processing unit |
US5758117A (en) * | 1995-12-14 | 1998-05-26 | International Business Machines Corporation | Method and system for efficiently utilizing rename buffers to reduce dispatch unit stalls in a superscalar processor |
US6298435B1 (en) * | 1996-04-16 | 2001-10-02 | International Business Machines Corporation | Methods and apparatus for exploiting virtual buffers to increase instruction parallelism in a pipelined processor |
US6003126A (en) * | 1997-07-01 | 1999-12-14 | International Business Machines | Special instruction register including allocation field utilized for temporary designation of physical registers as general registers |
GB2460280A (en) * | 2008-05-23 | 2009-11-25 | Advanced Risc Mach Ltd | Using a memory-abort register in the emulation of memory access operations |
US9229745B2 (en) | 2012-09-12 | 2016-01-05 | International Business Machines Corporation | Identifying load-hit-store conflicts |
US10901738B2 (en) * | 2017-11-14 | 2021-01-26 | International Business Machines Corporation | Bulk store and load operations of configuration state registers |
US10592164B2 (en) | 2017-11-14 | 2020-03-17 | International Business Machines Corporation | Portions of configuration state registers in-memory |
US10761983B2 (en) * | 2017-11-14 | 2020-09-01 | International Business Machines Corporation | Memory based configuration state registers |
CN116226021B (zh) * | 2023-05-06 | 2023-07-25 | 摩尔线程智能科技(北京)有限责任公司 | 数据收发方法、装置以及图形处理器 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4351024A (en) * | 1975-04-21 | 1982-09-21 | Honeywell Information Systems Inc. | Switch system base mechanism |
JPS5439539A (en) * | 1977-09-05 | 1979-03-27 | Hitachi Ltd | Data processor |
-
1982
- 1982-06-30 JP JP57113470A patent/JPS593642A/ja active Granted
-
1983
- 1983-06-28 KR KR1019830002921A patent/KR890000100B1/ko not_active IP Right Cessation
- 1983-06-29 CA CA000431511A patent/CA1200319A/en not_active Expired
- 1983-06-30 ES ES523751A patent/ES8405176A1/es not_active Expired
- 1983-06-30 EP EP83303789A patent/EP0098172B1/en not_active Expired
- 1983-06-30 BR BR8303527A patent/BR8303527A/pt not_active IP Right Cessation
- 1983-06-30 DE DE8383303789T patent/DE3379848D1/de not_active Expired
- 1983-06-30 AU AU16409/83A patent/AU546572B2/en not_active Ceased
- 1983-06-30 US US06/509,609 patent/US4623962A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
ES523751A0 (es) | 1984-05-16 |
CA1200319A (en) | 1986-02-04 |
US4623962A (en) | 1986-11-18 |
AU1640983A (en) | 1984-01-05 |
EP0098172B1 (en) | 1989-05-10 |
JPS593642A (ja) | 1984-01-10 |
KR890000100B1 (ko) | 1989-03-07 |
EP0098172A3 (en) | 1985-10-09 |
EP0098172A2 (en) | 1984-01-11 |
JPH0517577B2 (es) | 1993-03-09 |
DE3379848D1 (en) | 1989-06-15 |
AU546572B2 (en) | 1985-09-05 |
BR8303527A (pt) | 1984-02-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
ES8405176A1 (es) | Sistema de proceso de control de registro. | |
ES8202968A1 (es) | Dispositivo de control de direccion en un sistema de trata- miento de datos | |
AU540594B2 (en) | Memory protection system | |
ES8303743A1 (es) | Sistema de proceso de datos para el proceso en paralelo. | |
GB1055704A (en) | Improvements relating to electronic data processing systems | |
KR910006856A (ko) | 어드레스 레지스터를 이용하여 동적으로 버스제어를 실행하는 마이크로컴퓨터 | |
MY115173A (en) | Inverse transport processor with memory address circuitry | |
GB2016753A (en) | Data Processing System | |
GB1535185A (en) | Multiprocessor data processing system peripheral equipment access unit | |
JPS559228A (en) | Memory request control system | |
JPS56153452A (en) | Virtual computer system | |
JPS5785148A (en) | Instruction sequence control device | |
JPS5663652A (en) | Information processing unit | |
JPS646487B2 (es) | ||
JPS5723155A (en) | Program tracing system | |
JPS54129934A (en) | Data access control system | |
JPS5724081A (en) | Virtual storage controller of multiprocessor | |
JPS6450120A (en) | Register file | |
JPS55116145A (en) | Microprogram controller | |
JPS5696334A (en) | Prefetch system | |
GB1137670A (en) | Improvements in data processing systems | |
JPS57164363A (en) | Simulation system in multi-processor system | |
JPS5622152A (en) | Memory access system | |
JPS56168264A (en) | Data loading address storage system of digital computer | |
JPS5452935A (en) | Multiple access channel control unit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FD1A | Patent lapsed |
Effective date: 19991108 |