ES554098A0 - Regenerador de cadencia con un detector de fase - Google Patents
Regenerador de cadencia con un detector de faseInfo
- Publication number
- ES554098A0 ES554098A0 ES554098A ES554098A ES554098A0 ES 554098 A0 ES554098 A0 ES 554098A0 ES 554098 A ES554098 A ES 554098A ES 554098 A ES554098 A ES 554098A ES 554098 A0 ES554098 A0 ES 554098A0
- Authority
- ES
- Spain
- Prior art keywords
- phase detector
- phase
- det
- regenerator
- output signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003111 delayed effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Television Signal Processing For Recording (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
- Diaphragms For Electromechanical Transducers (AREA)
- Catalysts (AREA)
- Preparation Of Compounds By Using Micro-Organisms (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Sorption Type Refrigeration Machines (AREA)
- Polysaccharides And Polysaccharide Derivatives (AREA)
- Inorganic Insulating Materials (AREA)
- Control Of Motors That Do Not Use Commutators (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CH244085 | 1985-06-10 |
Publications (2)
Publication Number | Publication Date |
---|---|
ES8801737A1 ES8801737A1 (es) | 1987-11-01 |
ES554098A0 true ES554098A0 (es) | 1987-11-01 |
Family
ID=4233866
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES554098A Expired ES8801737A1 (es) | 1985-06-10 | 1986-04-17 | Regenerador de cadencia con un detector de fase |
Country Status (11)
Country | Link |
---|---|
US (1) | US4691327A (es) |
EP (1) | EP0204894B1 (es) |
JP (1) | JPS61288520A (es) |
AT (1) | ATE66768T1 (es) |
AU (1) | AU590277B2 (es) |
BR (1) | BR8602057A (es) |
CA (1) | CA1262174A (es) |
DE (1) | DE3681075D1 (es) |
ES (1) | ES8801737A1 (es) |
GR (1) | GR861495B (es) |
NO (1) | NO861216L (es) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4820994A (en) * | 1986-10-20 | 1989-04-11 | Siemens Aktiengesellschaft | Phase regulating circuit |
US4849998A (en) * | 1988-06-03 | 1989-07-18 | Communications Satellite Corporation | Rate synchronized symbol timing recovery for variable rate data transmission systems |
DK576888D0 (da) * | 1988-10-17 | 1988-10-17 | Schur Int As Brdr | Fremgangsmaade ved fremstilling af poseemballager med oprivelig svejselukning, saadanne emballager med genlukningsprofildele, samt hjaelpemateriale til brug ved denne fremstilling |
DE4138543A1 (de) * | 1991-11-23 | 1993-05-27 | Philips Patentverwaltung | Digitaler phasenregelkreis |
JPH06232738A (ja) * | 1993-02-03 | 1994-08-19 | Mitsubishi Electric Corp | 同期パルス発生回路 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3936762A (en) * | 1974-06-17 | 1976-02-03 | The Charles Stark Draper Laboratory, Inc. | Digital phase-lock loop systems for phase processing of signals |
JPS5941338B2 (ja) * | 1976-05-10 | 1984-10-06 | 日本電気株式会社 | クロツクパルス再生回路 |
US4151485A (en) * | 1977-11-21 | 1979-04-24 | Rockwell International Corporation | Digital clock recovery circuit |
JPS5853809B2 (ja) * | 1977-12-20 | 1983-12-01 | 日本電気株式会社 | クロツクパルス再生回路 |
US4327356A (en) * | 1979-06-19 | 1982-04-27 | Gilliland John D | Arrangement for monitoring the performance of a digital transmission system |
US4280099A (en) * | 1979-11-09 | 1981-07-21 | Sperry Corporation | Digital timing recovery system |
US4400817A (en) * | 1980-12-30 | 1983-08-23 | Motorola, Inc. | Method and means of clock recovery in a received stream of digital data |
FR2523383B1 (fr) * | 1982-03-15 | 1985-11-22 | Thomson Csf | Dispositif de recuperation de frequence d'horloge en transmission numerique |
US4590602A (en) * | 1983-08-18 | 1986-05-20 | General Signal | Wide range clock recovery circuit |
-
1986
- 1986-03-08 EP EP86103120A patent/EP0204894B1/de not_active Expired - Lifetime
- 1986-03-08 AT AT86103120T patent/ATE66768T1/de not_active IP Right Cessation
- 1986-03-08 DE DE8686103120T patent/DE3681075D1/de not_active Expired - Fee Related
- 1986-03-25 NO NO861216A patent/NO861216L/no unknown
- 1986-04-17 ES ES554098A patent/ES8801737A1/es not_active Expired
- 1986-05-06 US US06/860,273 patent/US4691327A/en not_active Expired - Fee Related
- 1986-05-07 BR BR8602057A patent/BR8602057A/pt unknown
- 1986-05-28 AU AU58006/86A patent/AU590277B2/en not_active Ceased
- 1986-06-04 JP JP61129983A patent/JPS61288520A/ja active Pending
- 1986-06-06 CA CA000510974A patent/CA1262174A/en not_active Expired
- 1986-06-09 GR GR861495A patent/GR861495B/el unknown
Also Published As
Publication number | Publication date |
---|---|
BR8602057A (pt) | 1987-01-06 |
DE3681075D1 (de) | 1991-10-02 |
ATE66768T1 (de) | 1991-09-15 |
ES8801737A1 (es) | 1987-11-01 |
AU5800686A (en) | 1986-12-18 |
NO861216L (no) | 1986-12-11 |
AU590277B2 (en) | 1989-11-02 |
EP0204894A3 (en) | 1988-11-17 |
JPS61288520A (ja) | 1986-12-18 |
EP0204894B1 (de) | 1991-08-28 |
US4691327A (en) | 1987-09-01 |
GR861495B (en) | 1986-10-10 |
CA1262174A (en) | 1989-10-03 |
EP0204894A2 (de) | 1986-12-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
ES2095932T3 (es) | Sintetizador de frecuencia de circuito de sincronizacion de fase con limitador duro activado por un sintetizador digital directo. | |
JPS6448267A (en) | Pll circuit for magnetic disk device | |
ES8302385A1 (es) | Un circuito cerrado enclavado en fase que produce una senal de salida que tiene una frecuencia enclavada a la frecuenciade una senal de entrada. | |
CA2081400A1 (en) | Frequency synthesis using frequency controlled carrier modulated with pll feedback signal | |
EP0170207A3 (en) | A write clock pulse generator used for a time base corrector | |
JPS5539490A (en) | Phase synchronizing signal generator circuit | |
ES554098A0 (es) | Regenerador de cadencia con un detector de fase | |
DE2962880D1 (en) | Circuit for timing signal recovery in digital signal transmission | |
CA2093040A1 (en) | Frequency synthesizer using phase-locked loop | |
JPS5685948A (en) | Stuffing synchronizing system | |
JPS57194637A (en) | Phase locked loop lock detecting circuit | |
ES2105919A1 (es) | Sinteti ador de frecuencia con bucle de enclavamiento de fase de division fraccionaria multiple. | |
JPS57162841A (en) | Digital pll circuit system | |
JPS55136745A (en) | Pll circuit extracting cmi signal timing | |
CA1328493C (en) | Phase detector with variable gain amplifier | |
JPS5380202A (en) | Phase-locked loop for demodulation of multichannel record | |
JPS5483752A (en) | Pll frequency synthesizer system | |
ATE2372T1 (de) | Schaltungsanordnung zur taktrueckgewinnung in regeneratoren fuer digitale signale. | |
JPS57101447A (en) | Clock phase lock circuit | |
JPS5787241A (en) | Phase synchronizing circuit for optional frequency conversion | |
JPS6413815A (en) | Pll circuit | |
JPS57173267A (en) | Afc circuit | |
JPS5696533A (en) | Digital pll circuit | |
JPS6424632A (en) | Phase locked loop circuit | |
DE3168960D1 (en) | Device for the recovery of a clock signal from a binary signal |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FD1A | Patent lapsed |
Effective date: 19970303 |