JPS55136745A - Pll circuit extracting cmi signal timing - Google Patents

Pll circuit extracting cmi signal timing

Info

Publication number
JPS55136745A
JPS55136745A JP4428879A JP4428879A JPS55136745A JP S55136745 A JPS55136745 A JP S55136745A JP 4428879 A JP4428879 A JP 4428879A JP 4428879 A JP4428879 A JP 4428879A JP S55136745 A JPS55136745 A JP S55136745A
Authority
JP
Japan
Prior art keywords
circuit
signal
cmi
output
timing clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4428879A
Other languages
Japanese (ja)
Other versions
JPS6016144B2 (en
Inventor
Chikao Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP54044288A priority Critical patent/JPS6016144B2/en
Publication of JPS55136745A publication Critical patent/JPS55136745A/en
Publication of JPS6016144B2 publication Critical patent/JPS6016144B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To make unnecessary the tank circuit, by reproducing the timing clock from CMI(Coded-Mark-Inversion) signal by using PLL circuit. CONSTITUTION:The CMI signal 1 is input to the combined logic circuit 4 at the delay circuit 2 together with the signal 3 delayed by a half period. The first half of the information bit is detected and intermittent detection signal 5 is fed to the exclusive logical sum circuit 8. The circuit 8 inputs the output 7 of the voltage controlled oscillator (VCO) 6 and the detection signal 5 to take exclusive logical sum for the both inputs. That is, position comparison is made. This output 9 is output as the control voltage 13 of VCO6 from the loop filter amplifying circuit 12. The control voltage 13 synchronizes the frequency and phase of the timing clock 7 of VCO6 to the frequency and phase of the timing clock of CMI signal 1, and the timing clock of CMI signal 1 is extracted from the output of VCO.
JP54044288A 1979-04-13 1979-04-13 CMI signal timing extraction PLL circuit Expired JPS6016144B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54044288A JPS6016144B2 (en) 1979-04-13 1979-04-13 CMI signal timing extraction PLL circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54044288A JPS6016144B2 (en) 1979-04-13 1979-04-13 CMI signal timing extraction PLL circuit

Publications (2)

Publication Number Publication Date
JPS55136745A true JPS55136745A (en) 1980-10-24
JPS6016144B2 JPS6016144B2 (en) 1985-04-24

Family

ID=12687309

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54044288A Expired JPS6016144B2 (en) 1979-04-13 1979-04-13 CMI signal timing extraction PLL circuit

Country Status (1)

Country Link
JP (1) JPS6016144B2 (en)

Also Published As

Publication number Publication date
JPS6016144B2 (en) 1985-04-24

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