JPS56104557A - Bit synchronous circuit - Google Patents

Bit synchronous circuit

Info

Publication number
JPS56104557A
JPS56104557A JP679180A JP679180A JPS56104557A JP S56104557 A JPS56104557 A JP S56104557A JP 679180 A JP679180 A JP 679180A JP 679180 A JP679180 A JP 679180A JP S56104557 A JPS56104557 A JP S56104557A
Authority
JP
Japan
Prior art keywords
input
output
change point
circuit
defo
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP679180A
Other languages
Japanese (ja)
Inventor
Takushi Hamada
Sadao Mizokawa
Masahiro Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP679180A priority Critical patent/JPS56104557A/en
Publication of JPS56104557A publication Critical patent/JPS56104557A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To extract receiving clocks stably, by causing the change point of delay clocks to function as the change point of receiving data, which disappeared, substitutionally when change point information of receiving data disappeared. CONSTITUTION:Receiving data RDATA is input to differentiating circuit 1 and has change point information extracted. The output signal of undesired pulse mask circuit 2 is input to one input of phase comparator 3, and the output of voltage control oscillator 5 is input to the other. Receiving clocks RCLK which are the output of oscillator 5 are so adjusted that they have a proper phase difference for output DEFO of the differentiating circuit by delay line 7. The output of delay line 7 is masked in AND gate 8 by output signal SYND of synchronization leading-in detecting circuit 6. Only DEFO is input by circuit 2 till completion of synchronization leading-in, and DEFO and delay clock DCLK are turned off and input by gate 9 after completion.
JP679180A 1980-01-25 1980-01-25 Bit synchronous circuit Pending JPS56104557A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP679180A JPS56104557A (en) 1980-01-25 1980-01-25 Bit synchronous circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP679180A JPS56104557A (en) 1980-01-25 1980-01-25 Bit synchronous circuit

Publications (1)

Publication Number Publication Date
JPS56104557A true JPS56104557A (en) 1981-08-20

Family

ID=11647992

Family Applications (1)

Application Number Title Priority Date Filing Date
JP679180A Pending JPS56104557A (en) 1980-01-25 1980-01-25 Bit synchronous circuit

Country Status (1)

Country Link
JP (1) JPS56104557A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6278755B1 (en) 1999-05-18 2001-08-21 Nec Corporation Bit synchronization circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6278755B1 (en) 1999-05-18 2001-08-21 Nec Corporation Bit synchronization circuit

Similar Documents

Publication Publication Date Title
IE41344B1 (en) Improvement to synchronizing circuits
GB1236494A (en) Improvements in or relating to phase difference detectors
GB1227711A (en)
JPS5720052A (en) Input data synchronizing circuit
ES482447A1 (en) Timing-phase recovery circuit
GB1423689A (en) Apparatus for sampling an asynchronous signal by a synchronous signal
GB1264023A (en) Frame synchronisation system
GB959311A (en) Skew correction system
GB2050007B (en) Electronic timepieces
JPS56104557A (en) Bit synchronous circuit
EP0108702A3 (en) Serial to parallel data conversion circuit
GB1152210A (en) Synchronizing System
GB1521029A (en) Synchronous digital systems
JPS5513585A (en) Frame synchronizing circuit
JPS558103A (en) Reproducing system of timing information
JPS54148413A (en) Reproduction system for timing information
GB1237422A (en) Bit sync recovery system
GB1148245A (en) Method and apparatus for timing pulse synchronisation
JPS524811A (en) Pulse demodulator
JPS5868345A (en) Bit synchronizing circuit
JPS55136745A (en) Pll circuit extracting cmi signal timing
JPS5758444A (en) Clock extracting system in dipulse code composite circuit
JPS57143963A (en) Data detector
JPS55146618A (en) Data synchronizing circuit
JPS6439145A (en) Circuit for switching data transfer timing