ES462082A1 - Procedimiento y elaborador para generar palabras de m + n bits para sistemas controlados de programas memorizados. - Google Patents

Procedimiento y elaborador para generar palabras de m + n bits para sistemas controlados de programas memorizados.

Info

Publication number
ES462082A1
ES462082A1 ES462082A ES462082A ES462082A1 ES 462082 A1 ES462082 A1 ES 462082A1 ES 462082 A ES462082 A ES 462082A ES 462082 A ES462082 A ES 462082A ES 462082 A1 ES462082 A1 ES 462082A1
Authority
ES
Spain
Prior art keywords
bit
amu
word
address
words
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES462082A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of ES462082A1 publication Critical patent/ES462082A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/342—Extension of operand address space
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0407—Selecting arrangements for multiplex systems for time-division multiplexing using a stored programme control

Abstract

Procedimiento y elaborador para generar palabras de m + n bits, para sistemas controlados de programas memorizados, cuyo elaborador tiene una primera unidad aritmética en una anchura de m bits (AMU) y una segunda AMU con una anchura de n bits, procedimiento caracterizado porque comprende los pasos de introducir una primera palabra de m bits en la primera AMU; transferir n bits desde n posiciones predeterminadas de bits de la primera palabra desde la primera AMU a la segunda AMU; introducir una segunda palabra de m bits en la primera AMU; y leer simultáneamente los n bits de la segunda AMU y los m bits de la segunda palabra de información de la primera AMU, para formar una palabra de m + n bits.
ES462082A 1976-09-03 1977-09-02 Procedimiento y elaborador para generar palabras de m + n bits para sistemas controlados de programas memorizados. Expired ES462082A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/720,417 US4090237A (en) 1976-09-03 1976-09-03 Processor circuit

Publications (1)

Publication Number Publication Date
ES462082A1 true ES462082A1 (es) 1978-12-16

Family

ID=24893963

Family Applications (1)

Application Number Title Priority Date Filing Date
ES462082A Expired ES462082A1 (es) 1976-09-03 1977-09-02 Procedimiento y elaborador para generar palabras de m + n bits para sistemas controlados de programas memorizados.

Country Status (11)

Country Link
US (1) US4090237A (es)
JP (1) JPS5848944B2 (es)
BE (1) BE858224A (es)
CA (1) CA1082369A (es)
DE (1) DE2739525C2 (es)
ES (1) ES462082A1 (es)
FR (1) FR2363834A1 (es)
GB (1) GB1567536A (es)
IT (1) IT1086453B (es)
NL (1) NL7709694A (es)
SE (1) SE432312B (es)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4291370A (en) * 1978-08-23 1981-09-22 Westinghouse Electric Corp. Core memory interface for coupling a processor to a memory having a differing word length
US4309754A (en) * 1979-07-30 1982-01-05 International Business Machines Corp. Data interface mechanism for interfacing bit-parallel data buses of different bit width
US4467443A (en) * 1979-07-30 1984-08-21 Burroughs Corporation Bit addressable variable length memory system
US4346437A (en) * 1979-08-31 1982-08-24 Bell Telephone Laboratories, Incorporated Microcomputer using a double opcode instruction
US4434459A (en) 1980-04-25 1984-02-28 Data General Corporation Data processing system having instruction responsive apparatus for both a basic and an extended instruction set
US4733351A (en) * 1984-12-31 1988-03-22 Wang Laboratories, Inc. Terminal protocols
US4814976C1 (en) * 1986-12-23 2002-06-04 Mips Tech Inc Risc computer with unaligned reference handling and method for the same
US4799187A (en) * 1987-07-30 1989-01-17 Wang Laboratories, Inc. Memory address generator with device address type specifier
JPH03186928A (ja) * 1989-12-16 1991-08-14 Mitsubishi Electric Corp データ処理装置
JP3181307B2 (ja) * 1991-04-25 2001-07-03 株式会社東芝 命令処理装置
US5566308A (en) * 1994-05-25 1996-10-15 National Semiconductor Corporation Processor core which provides a linear extension of an addressable memory space
KR960704269A (ko) * 1994-05-25 1996-08-31 존 엠. 클락 3세 어드레스가능한 메모리 스페이스의 선형 확장을 제공하는 프로세서 코어(processor core which provides a linear extenstion of an addressable memory space)
US5915266A (en) * 1994-05-25 1999-06-22 National Semiconductor Corporation Processor core which provides a linear extension of an addressable memory space

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1181461B (de) * 1963-10-08 1964-11-12 Telefunken Patent Adressenaddierwerk einer programm-gesteuerten Rechenmaschine
US3930232A (en) * 1973-11-23 1975-12-30 Raytheon Co Format insensitive digital computer

Also Published As

Publication number Publication date
NL7709694A (nl) 1978-03-07
FR2363834A1 (fr) 1978-03-31
JPS5331931A (en) 1978-03-25
SE432312B (sv) 1984-03-26
BE858224A (fr) 1977-12-16
CA1082369A (en) 1980-07-22
SE7709676L (sv) 1978-03-04
US4090237A (en) 1978-05-16
FR2363834B1 (es) 1981-05-29
JPS5848944B2 (ja) 1983-11-01
GB1567536A (en) 1980-05-14
IT1086453B (it) 1985-05-28
DE2739525C2 (de) 1982-04-01
DE2739525A1 (de) 1978-03-09

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