JPS5644937A - Adding circuit - Google Patents

Adding circuit

Info

Publication number
JPS5644937A
JPS5644937A JP12031179A JP12031179A JPS5644937A JP S5644937 A JPS5644937 A JP S5644937A JP 12031179 A JP12031179 A JP 12031179A JP 12031179 A JP12031179 A JP 12031179A JP S5644937 A JPS5644937 A JP S5644937A
Authority
JP
Japan
Prior art keywords
bits
memory
adder
output
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12031179A
Other languages
Japanese (ja)
Inventor
Toshiyuki Ikezaki
Kunikazu Shigeta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12031179A priority Critical patent/JPS5644937A/en
Publication of JPS5644937A publication Critical patent/JPS5644937A/en
Pending legal-status Critical Current

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  • Character Discrimination (AREA)

Abstract

PURPOSE: To simplify the constitution of an adding circuit, by using a memory where the number of "1" in address data is stored correspondingly to address data.
CONSTITUTION: Memory 9 uses two (256×4)-bit memories 10 and 11, and adder 12 is used as the adder for bits. Upper 8 bits 8a of input information 8 of 16 bits/1 word are input to the address of memory 10. Lower 8 bits 8b are input to the address of memory 11. The output of memory 10 is (0100)=4, and the output of memory 11 is (0011)=3. Consequently, the number of black bits ("1") is obtained for upper 8 bits 8a and lower 8 bits 8b respectively. By inputting outputs of memories 10 and 11 to next-stage adder 12, the number of black bits ("1") in all 16 bits of input information 8 can be obtained as the output of adder 12.
COPYRIGHT: (C)1981,JPO&Japio
JP12031179A 1979-09-18 1979-09-18 Adding circuit Pending JPS5644937A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12031179A JPS5644937A (en) 1979-09-18 1979-09-18 Adding circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12031179A JPS5644937A (en) 1979-09-18 1979-09-18 Adding circuit

Publications (1)

Publication Number Publication Date
JPS5644937A true JPS5644937A (en) 1981-04-24

Family

ID=14783093

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12031179A Pending JPS5644937A (en) 1979-09-18 1979-09-18 Adding circuit

Country Status (1)

Country Link
JP (1) JPS5644937A (en)

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