JPS54109324A - Generating circuit for key scanning signal - Google Patents

Generating circuit for key scanning signal

Info

Publication number
JPS54109324A
JPS54109324A JP1623978A JP1623978A JPS54109324A JP S54109324 A JPS54109324 A JP S54109324A JP 1623978 A JP1623978 A JP 1623978A JP 1623978 A JP1623978 A JP 1623978A JP S54109324 A JPS54109324 A JP S54109324A
Authority
JP
Japan
Prior art keywords
signal
key scanning
address
ram
word
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1623978A
Other languages
Japanese (ja)
Inventor
Yoshihiro Funakoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1623978A priority Critical patent/JPS54109324A/en
Publication of JPS54109324A publication Critical patent/JPS54109324A/en
Pending legal-status Critical Current

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  • Input From Keyboards Or The Like (AREA)
  • Calculators And Similar Devices (AREA)

Abstract

PURPOSE: To improve the manufacture yield of a LSI with the circuit constitution simplified by providing a method which generates a key scanning signal regarding the address selective signal of RAMs arrayed in several digits and several lines as a fundamental signal.
CONSTITUTION: Terminals A to D are output terminals of an address counter and when the address line of one of AND circuits A0 to A8 becomes "1" by a signal counted up at every one-word time, four cells of the RAM connected to the line is selected, so that memory contents of the RAM will be outputted via output lines Q1 to Q4. Output terminals of circuits A0 to A8 are connected to output buffers B0 to B8 respectively, which are connected to outputs K0 to K8 by way of two inverters. When a signal according to the word time is inputted to inputs A to D, key scanning signals which become "1" in the word-time order of (a) to (i) are outputted to outputs K0 to K8. RAM address assignment signals can therefore be assigned as key scanning signals not by providing a special digit-signal generating circuit and, consequently, the circuit constitution can be simplified.
COPYRIGHT: (C)1979,JPO&Japio
JP1623978A 1978-02-15 1978-02-15 Generating circuit for key scanning signal Pending JPS54109324A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1623978A JPS54109324A (en) 1978-02-15 1978-02-15 Generating circuit for key scanning signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1623978A JPS54109324A (en) 1978-02-15 1978-02-15 Generating circuit for key scanning signal

Publications (1)

Publication Number Publication Date
JPS54109324A true JPS54109324A (en) 1979-08-27

Family

ID=11910998

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1623978A Pending JPS54109324A (en) 1978-02-15 1978-02-15 Generating circuit for key scanning signal

Country Status (1)

Country Link
JP (1) JPS54109324A (en)

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