JPS57162193A - Large capacity memory device - Google Patents

Large capacity memory device

Info

Publication number
JPS57162193A
JPS57162193A JP4593281A JP4593281A JPS57162193A JP S57162193 A JPS57162193 A JP S57162193A JP 4593281 A JP4593281 A JP 4593281A JP 4593281 A JP4593281 A JP 4593281A JP S57162193 A JPS57162193 A JP S57162193A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
memory
error
division
divisions
preparative
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4593281A
Inventor
Hideo Kamata
Teru Koshidaka
Masami Yasuda
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/76Masking faults in memories by using spares or by reconfiguring using address translation or modifications

Abstract

PURPOSE:To utilize effectively an area in a memory which is not used by dividing the memory previously into a using area and preparative areas and, when an error is generated in the using memory division, changing addresses in the error memory division to the ones in the preparative memory division. CONSTITUTION:A memory MEM is divided into 4 divisions for example an and address setting device AC for using one of these divisions is connected to the memory. An error detecting device EDT checks the data read out from a memory MEM1 and, when an error is generated in the memory, an address converting part ADC applies the potential of ''0'' and ''1'' to output lines LT1 and LT2. Then an address data with the upper bit added by the device AD is to be processed and addresses in a divided memory part MEM2 is set up.
JP4593281A 1981-03-29 1981-03-29 Large capacity memory device Pending JPS57162193A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4593281A JPS57162193A (en) 1981-03-29 1981-03-29 Large capacity memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4593281A JPS57162193A (en) 1981-03-29 1981-03-29 Large capacity memory device

Publications (1)

Publication Number Publication Date
JPS57162193A true true JPS57162193A (en) 1982-10-05

Family

ID=12733032

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4593281A Pending JPS57162193A (en) 1981-03-29 1981-03-29 Large capacity memory device

Country Status (1)

Country Link
JP (1) JPS57162193A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62102386A (en) * 1985-10-29 1987-05-12 Toppan Printing Co Ltd Ic card
JPH02100158A (en) * 1988-10-06 1990-04-12 Koufu Nippon Denki Kk Information processor
JPH03102593A (en) * 1989-09-18 1991-04-26 Toppan Printing Co Ltd Ic memory card system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62102386A (en) * 1985-10-29 1987-05-12 Toppan Printing Co Ltd Ic card
JPH02100158A (en) * 1988-10-06 1990-04-12 Koufu Nippon Denki Kk Information processor
JPH03102593A (en) * 1989-09-18 1991-04-26 Toppan Printing Co Ltd Ic memory card system

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