ES2186970T3 - Decodificador de viterbi. - Google Patents

Decodificador de viterbi.

Info

Publication number
ES2186970T3
ES2186970T3 ES98306212T ES98306212T ES2186970T3 ES 2186970 T3 ES2186970 T3 ES 2186970T3 ES 98306212 T ES98306212 T ES 98306212T ES 98306212 T ES98306212 T ES 98306212T ES 2186970 T3 ES2186970 T3 ES 2186970T3
Authority
ES
Spain
Prior art keywords
memory
state
viterbi decoder
scs
state metrics
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES98306212T
Other languages
English (en)
Inventor
Sung-Han Choi
Jun-Jin Kong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Application granted granted Critical
Publication of ES2186970T3 publication Critical patent/ES2186970T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H03M13/6505—Memory efficient implementations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/3961—Arrangements of methods for branch or transition metric calculation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4107—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing add, compare, select [ACS] operations

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

SE EXPONE UN APARATO PARA PROPORCIONAR Y ALMACENAR UNA METRICA DE ESTADO QUE SE USA PARA UNA OPERACION DE SUMA - COMPARACION SELECCION (SCS) SE EXPONE EN UN DECODIFICADOR VITERBI, CON EL USO DE UNA SERIE DE UNIDADES SCS A FIN DE AUMENTAR LA VELOCIDAD DE DECODIFICACION. UNA MEMORIA DE METRICA DE ESTADO DE UN DECODIFICADOR DE VITERBI UTILIZA UNA MEMORIA DE DOS PUERTOS, EN LA QUE UN BANCO DE MEMORIAS PARA LEER Y ESCRIBIR UNA METRICA DE ESTADO DE UNA PRIMERA MITAD ENTRE LAS N METRICAS DE ESTADO GENERADAS EN UNA UNIDAD SCS Y DOS BANCOS DE MEMORIAS PARA LEER Y ESCRIBIR ALTERNATIVAMENTE LA METRICA DE ESTADO DE LA SEGUNDA MITAD, SIEMPRE QUE SE INTRODUCE UNA PALABRA DE CODIGO, SE INCORPORAN A UNA UNICA MEMORIA. COMO RESULTADO, SE PUEDE REDUCIR NOTABLEMENTE LA CAPACIDAD DE ALMACENAMIENTO PARA GUARDAR LAS METRICAS DE ESTADO, SI SE COMPARA CON UN APARATO CONVENCIONAL.
ES98306212T 1997-08-07 1998-08-04 Decodificador de viterbi. Expired - Lifetime ES2186970T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970037799A KR100484127B1 (ko) 1997-08-07 1997-08-07 비터비디코더

Publications (1)

Publication Number Publication Date
ES2186970T3 true ES2186970T3 (es) 2003-05-16

Family

ID=19517080

Family Applications (1)

Application Number Title Priority Date Filing Date
ES98306212T Expired - Lifetime ES2186970T3 (es) 1997-08-07 1998-08-04 Decodificador de viterbi.

Country Status (7)

Country Link
US (1) US6317472B1 (es)
EP (1) EP0896436B1 (es)
JP (1) JPH11154874A (es)
KR (1) KR100484127B1 (es)
CN (1) CN1097880C (es)
DE (1) DE69809155T2 (es)
ES (1) ES2186970T3 (es)

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EP0896436B1 (en) 2002-11-06
KR19990015603A (ko) 1999-03-05
CN1097880C (zh) 2003-01-01
KR100484127B1 (ko) 2005-06-16
DE69809155D1 (de) 2002-12-12
EP0896436A3 (en) 2001-03-07
CN1208287A (zh) 1999-02-17
US6317472B1 (en) 2001-11-13
EP0896436A2 (en) 1999-02-10
DE69809155T2 (de) 2003-03-27
JPH11154874A (ja) 1999-06-08

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