ATE475181T1 - Konfigurierbarer mvram und konfigurationsverfahren - Google Patents
Konfigurierbarer mvram und konfigurationsverfahrenInfo
- Publication number
- ATE475181T1 ATE475181T1 AT06392018T AT06392018T ATE475181T1 AT E475181 T1 ATE475181 T1 AT E475181T1 AT 06392018 T AT06392018 T AT 06392018T AT 06392018 T AT06392018 T AT 06392018T AT E475181 T1 ATE475181 T1 AT E475181T1
- Authority
- AT
- Austria
- Prior art keywords
- array
- memory cells
- configurable
- configuration data
- mvram
- Prior art date
Links
- 230000001934 delay Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
- G11C11/1657—Word-line or row circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1659—Cell access
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1693—Timing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Hall/Mr Elements (AREA)
- Oscillators With Electromechanical Resonators (AREA)
- Measurement And Recording Of Electrical Phenomena And Electrical Characteristics Of The Living Body (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/313,019 US7362644B2 (en) | 2005-12-20 | 2005-12-20 | Configurable MRAM and method of configuration |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE475181T1 true ATE475181T1 (de) | 2010-08-15 |
Family
ID=38007287
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT06392018T ATE475181T1 (de) | 2005-12-20 | 2006-12-20 | Konfigurierbarer mvram und konfigurationsverfahren |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7362644B2 (de) |
| EP (1) | EP1801810B1 (de) |
| JP (1) | JP5357387B2 (de) |
| AT (1) | ATE475181T1 (de) |
| DE (1) | DE602006015596D1 (de) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20070074232A (ko) * | 2006-01-09 | 2007-07-12 | 삼성전자주식회사 | 램 영역과 롬 영역을 동시에 가지는 반도체 메모리 장치 |
| KR20070076071A (ko) * | 2006-01-17 | 2007-07-24 | 삼성전자주식회사 | 비접촉식 카드 그리고 비접촉식 카드시스템 |
| US7746686B2 (en) * | 2006-04-21 | 2010-06-29 | Honeywell International Inc. | Partitioned random access and read only memory |
| US7457149B2 (en) * | 2006-05-05 | 2008-11-25 | Macronix International Co., Ltd. | Methods and apparatus for thermally assisted programming of a magnetic memory device |
| US7652905B2 (en) * | 2007-01-04 | 2010-01-26 | Macronix International Co., Ltd. | Flash memory array architecture |
| KR100898673B1 (ko) * | 2007-08-08 | 2009-05-22 | 주식회사 하이닉스반도체 | 플래시 메모리 소자 및 그 동작 방법 |
| US7936590B2 (en) * | 2008-12-08 | 2011-05-03 | Qualcomm Incorporated | Digitally-controllable delay for sense amplifier |
| US20100302838A1 (en) * | 2009-05-26 | 2010-12-02 | Magic Technologies, Inc. | Read disturb-free SMT reference cell scheme |
| US8144534B2 (en) * | 2009-08-25 | 2012-03-27 | Micron Technology, Inc. | Methods and memory devices for repairing memory cells |
| KR101604042B1 (ko) * | 2009-12-30 | 2016-03-16 | 삼성전자주식회사 | 자기 메모리 및 그 동작방법 |
| US8320167B2 (en) * | 2010-07-16 | 2012-11-27 | Qualcomm Incorporated | Programmable write driver for STT-MRAM |
| US8638596B2 (en) * | 2011-07-25 | 2014-01-28 | Qualcomm Incorporated | Non-volatile memory saving cell information in a non-volatile memory array |
| EP2766906B1 (de) * | 2011-10-10 | 2016-03-30 | Crocus Technology Inc. | Vorrichtung, system und verfahren zum schreiben auf mehrere magnetische direktzugriffsspeicherzellen mit einer einzigen feldlinie |
| US9047965B2 (en) * | 2011-12-20 | 2015-06-02 | Everspin Technologies, Inc. | Circuit and method for spin-torque MRAM bit line and source line voltage regulation |
| KR101997079B1 (ko) | 2012-07-26 | 2019-07-08 | 삼성전자주식회사 | 가변 저항 메모리를 포함하는 저장 장치 및 그것의 동작 방법 |
| KR102031661B1 (ko) | 2012-10-23 | 2019-10-14 | 삼성전자주식회사 | 데이터 저장 장치 및 컨트롤러, 그리고 데이터 저장 장치의 동작 방법 |
| WO2015174020A1 (ja) * | 2014-05-13 | 2015-11-19 | ソニー株式会社 | メモリシステム、メモリ周辺回路およびメモリ制御方法 |
| KR20170038816A (ko) | 2014-07-31 | 2017-04-07 | 휴렛 팩커드 엔터프라이즈 디벨롭먼트 엘피 | 크로스바 메모리 어레이 상의 데이터 인코딩에 리던던시 할당 |
| FR3130066B1 (fr) * | 2021-12-07 | 2024-07-19 | Hprobe | Dispositif et procédé de test de mémoire |
Family Cites Families (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63275097A (ja) | 1987-05-01 | 1988-11-11 | Nec Corp | 不揮発性メモリ |
| US6336161B1 (en) | 1995-12-15 | 2002-01-01 | Texas Instruments Incorporated | Computer configuration system and method with state and restoration from non-volatile semiconductor memory |
| US6462985B2 (en) | 1999-12-10 | 2002-10-08 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory for storing initially-setting data |
| DE10032271C2 (de) | 2000-07-03 | 2002-08-01 | Infineon Technologies Ag | MRAM-Anordnung |
| DE10032277A1 (de) | 2000-07-03 | 2002-01-24 | Infineon Technologies Ag | MRAM-Anordnung |
| DE10041378C1 (de) | 2000-08-23 | 2002-05-16 | Infineon Technologies Ag | MRAM-Anordnung |
| DE10053965A1 (de) | 2000-10-31 | 2002-06-20 | Infineon Technologies Ag | Verfahren zur Verhinderung unerwünschter Programmierungen in einer MRAM-Anordnung |
| DE10103313A1 (de) | 2001-01-25 | 2002-08-22 | Infineon Technologies Ag | MRAM-Anordnung |
| DE10107380C1 (de) * | 2001-02-16 | 2002-07-25 | Infineon Technologies Ag | Verfahren zum Beschreiben magnetoresistiver Speicherzellen und mit diesem Verfahren beschreibbarer magnetoresistiver Speicher |
| DE10121182C1 (de) | 2001-04-30 | 2002-10-17 | Infineon Technologies Ag | MRAM-Halbleiterspeicheranordnung mit redundanten Zellenfeldern |
| JP2003151260A (ja) * | 2001-11-13 | 2003-05-23 | Mitsubishi Electric Corp | 薄膜磁性体記憶装置 |
| JP4073690B2 (ja) | 2001-11-14 | 2008-04-09 | 株式会社ルネサステクノロジ | 薄膜磁性体記憶装置 |
| JP3799269B2 (ja) | 2001-12-10 | 2006-07-19 | 株式会社東芝 | 不揮発性半導体記憶装置 |
| JP2003178597A (ja) * | 2001-12-11 | 2003-06-27 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
| JP4278325B2 (ja) * | 2001-12-19 | 2009-06-10 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
| JP2003208796A (ja) * | 2002-01-15 | 2003-07-25 | Mitsubishi Electric Corp | 薄膜磁性体記憶装置 |
| US6801471B2 (en) * | 2002-02-19 | 2004-10-05 | Infineon Technologies Ag | Fuse concept and method of operation |
| JP2004110992A (ja) * | 2002-09-20 | 2004-04-08 | Renesas Technology Corp | 薄膜磁性体記憶装置 |
| JP2004118921A (ja) * | 2002-09-25 | 2004-04-15 | Toshiba Corp | 磁気ランダムアクセスメモリ |
| JP2004164745A (ja) * | 2002-11-13 | 2004-06-10 | Matsushita Electric Ind Co Ltd | 不揮発性半導体記憶装置 |
| JP3869430B2 (ja) * | 2004-05-11 | 2007-01-17 | 株式会社東芝 | 磁気ランダムアクセスメモリ |
-
2005
- 2005-12-20 US US11/313,019 patent/US7362644B2/en active Active
-
2006
- 2006-12-20 JP JP2006342730A patent/JP5357387B2/ja active Active
- 2006-12-20 AT AT06392018T patent/ATE475181T1/de not_active IP Right Cessation
- 2006-12-20 EP EP06392018A patent/EP1801810B1/de active Active
- 2006-12-20 DE DE602006015596T patent/DE602006015596D1/de active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US20070140033A1 (en) | 2007-06-21 |
| DE602006015596D1 (de) | 2010-09-02 |
| JP2007172819A (ja) | 2007-07-05 |
| EP1801810B1 (de) | 2010-07-21 |
| EP1801810A1 (de) | 2007-06-27 |
| JP5357387B2 (ja) | 2013-12-04 |
| US7362644B2 (en) | 2008-04-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |