ES2167797T3 - Uniones por soldadura optimizadas para chips de montaje en superficie. - Google Patents

Uniones por soldadura optimizadas para chips de montaje en superficie.

Info

Publication number
ES2167797T3
ES2167797T3 ES97947200T ES97947200T ES2167797T3 ES 2167797 T3 ES2167797 T3 ES 2167797T3 ES 97947200 T ES97947200 T ES 97947200T ES 97947200 T ES97947200 T ES 97947200T ES 2167797 T3 ES2167797 T3 ES 2167797T3
Authority
ES
Spain
Prior art keywords
pads
welding
roads
surface mount
maintained
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES97947200T
Other languages
English (en)
Inventor
Richard Keith Ii Mcmillan
Vivek Amir Jairazbhoy
Yi-Hsin Pao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ford Global Technologies LLC
Original Assignee
Ford Global Technologies LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ford Global Technologies LLC filed Critical Ford Global Technologies LLC
Application granted granted Critical
Publication of ES2167797T3 publication Critical patent/ES2167797T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09427—Special relation between the location or dimension of a pad or land and the location or dimension of a terminal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/0465—Shape of solder, e.g. differing from spherical shape, different shapes due to different solder pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/30—Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17
    • H05K2203/306—Lifting the component during or after mounting; Increasing the gap between component and PCB
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

SE DESVELA UN CIRCUITO IMPRESO MONTADO EN SUPERFICIE CON UN SUSTRATO (10), AL MENOS UN DISPOSITIVO PARA MONTAJE EN SUPERFICIE (14), AL MENOS DOS ALMOHADILLAS DE MONTAJE (12) POR DISPOSITIVO (14), JUNTAS DE SOLDADURA QUE CONECTAN LAS TERMINACIONES (22) DEL DISPOSITIVO (14) A SUS CORRESPONDIENTES ALMOHADILLAS (12), AL MENOS UNA ALMOHADILLA ELEVADORA RECTANGULAR (30) SOBRE EL SUSTRATO (10) ENTRE LAS ALMOHADILLAS (12), Y UNA MASA DE SOLDADURA (32) SOBRE CADA ALMOHADILLA ELEVADORA (30) EN CONTACTO CON LA SUPERFICIE INFERIOR (18) DEL DISPOSITIVO (14). LAS EXTENSIONES INTERNAS Y EXTERNAS (I I E I O ) DE LAS ALMOHADILLAS DE MONTAJE (12), EL TAMAÑO, NUMERO Y FORMA DE LAS ALMOHADILLAS ELEVADORAS Y LAS CANTIDADES DE SOLDADURA DEPOSITADAS SOBRE LAS ALMOHADILLAS ELEVADORAS (30) ESTAN DISEÑADOS PARA QUE LA JUNTA (24) TENGA PREFERENTEMENTE FILOS EXTERNOS CONVEXOS (28), EL DISPOSITIVO (14) SE MANTIENE A UNA ALTURA PREDETERMINADA (H O ) SOBRE LAS ALMOHADILLAS DE MONTAJE (12), EL A NGULO DEL INTERNO DE FILOAL SE MANTIENE SOBRE UN ANGULO MINIMO PREDETERMINADO PARA AUMENTAR EL TIEMPO DE INICIO DEL AGRIETAMIENTO DE LA JUNTA Y LA LONGITUD GLOBAL DE PROPAGACION DEL AGRIETAMIENTO DE LA JUNTA. EN UNA EJECUCION ALTERNATIVA DE LA INVENCION, TAMBIEN SE INCLUYEN VIAS TAPONADAS (34) BAJO LAS ALMOHADILLAS ELEVADORAS (30) Y/O DE MONTAJE (12) CON BOLSAS DE GAS (40) ATRAPADAS ENTRE LAS MASAS DE SOLDADURA (32)/JUNTAS DE SOLDADURA (24) Y LAS VIAS TAPONADAS (34). ESTAS BOLSAS DE GAS ATRAPADO (40) PROPORCIONAN UNA FUERZA DE EMPUJE ADICIONAL SOBRE EL SMD (14) DURANTE EL REFLUJO.
ES97947200T 1997-01-16 1997-12-29 Uniones por soldadura optimizadas para chips de montaje en superficie. Expired - Lifetime ES2167797T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/786,389 US5936846A (en) 1997-01-16 1997-01-16 Optimized solder joints and lifter pads for improving the solder joint life of surface mount chips

Publications (1)

Publication Number Publication Date
ES2167797T3 true ES2167797T3 (es) 2002-05-16

Family

ID=25138437

Family Applications (1)

Application Number Title Priority Date Filing Date
ES97947200T Expired - Lifetime ES2167797T3 (es) 1997-01-16 1997-12-29 Uniones por soldadura optimizadas para chips de montaje en superficie.

Country Status (10)

Country Link
US (1) US5936846A (es)
EP (1) EP0953277B1 (es)
JP (1) JP2001508949A (es)
CN (1) CN1245007A (es)
BR (1) BR9714289A (es)
CA (1) CA2278019A1 (es)
DE (1) DE69709172T2 (es)
ES (1) ES2167797T3 (es)
PT (1) PT953277E (es)
WO (1) WO1998032314A2 (es)

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EP1014767A1 (en) * 1998-12-23 2000-06-28 Lucent Technologies Inc. Thermal stress relief for surface mount components using via filling
KR100843737B1 (ko) * 2002-05-10 2008-07-04 페어차일드코리아반도체 주식회사 솔더 조인트의 신뢰성이 개선된 반도체 패키지
US7049051B2 (en) * 2003-01-23 2006-05-23 Akustica, Inc. Process for forming and acoustically connecting structures on a substrate
TWI243462B (en) * 2004-05-14 2005-11-11 Advanced Semiconductor Eng Semiconductor package including passive component
JP4557676B2 (ja) * 2004-10-27 2010-10-06 京セラ株式会社 半導体装置の実装構造
DE102005017527A1 (de) * 2005-04-15 2006-11-02 Osram Opto Semiconductors Gmbh Oberflächenmontierbares optoelektronisches Bauelement
DE102006054085A1 (de) * 2006-11-16 2008-05-29 Epcos Ag Bauelement-Anordnung
US7893545B2 (en) * 2007-07-18 2011-02-22 Infineon Technologies Ag Semiconductor device
US7830022B2 (en) * 2007-10-22 2010-11-09 Infineon Technologies Ag Semiconductor package
US8399995B2 (en) * 2009-01-16 2013-03-19 Infineon Technologies Ag Semiconductor device including single circuit element for soldering
DE102009060060A1 (de) * 2009-12-22 2011-06-30 Rohde & Schwarz GmbH & Co. KG, 81671 Halteelement zur unverlierbaren Montage einer Schraube
JP5552882B2 (ja) * 2010-04-26 2014-07-16 株式会社デンソー 表面実装型半導体パッケージの実装構造
JP5389748B2 (ja) * 2010-06-18 2014-01-15 日本メクトロン株式会社 電子部品の表面実装方法、及び該方法を用いて作製されたプリント回路板
US8604356B1 (en) * 2010-11-12 2013-12-10 Amkor Technology, Inc. Electronic assembly having increased standoff height
CN102522347B (zh) * 2011-12-23 2015-04-29 清华大学 一种制备焊料凸块的方法
JP2014110370A (ja) * 2012-12-04 2014-06-12 Seiko Epson Corp ベース基板、実装構造体、モジュール、電子機器、および移動体
JP5646021B2 (ja) * 2012-12-18 2014-12-24 積水化学工業株式会社 半導体パッケージ
US9622356B2 (en) * 2013-03-14 2017-04-11 Lockheed Martin Corporation Electronic package mounting
US9237655B1 (en) 2013-03-15 2016-01-12 Lockheed Martin Corporation Material deposition on circuit card assemblies
AT515071B1 (de) * 2013-09-03 2019-03-15 Zkw Group Gmbh Verfahren zum positionsstabilen Verlöten
JP6481446B2 (ja) * 2014-06-13 2019-03-13 株式会社村田製作所 積層コンデンサの実装構造体
US9634053B2 (en) 2014-12-09 2017-04-25 Taiwan Semiconductor Manufacturing Co., Ltd. Image sensor chip sidewall interconnection
CN113694796B (zh) * 2021-10-14 2022-02-08 深圳市澳华集团股份有限公司 一种肠道免疫增强剂生产用溶解装置及其使用方法
US11839031B2 (en) * 2022-04-06 2023-12-05 Western Digital Technologies, Inc. Micro solder joint and stencil aperture design

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DE3536431A1 (de) * 1985-10-12 1987-04-16 Standard Elektrik Lorenz Ag Loeten von oberflaechenmontierbaren bauelementen
EP0263222B1 (en) * 1986-10-08 1992-03-25 International Business Machines Corporation Method of forming solder terminals for a pinless ceramic module
US4749120A (en) * 1986-12-18 1988-06-07 Matsushita Electric Industrial Co., Ltd. Method of connecting a semiconductor device to a wiring board
US4760948A (en) * 1986-12-23 1988-08-02 Rca Corporation Leadless chip carrier assembly and method
DE3810653C1 (es) * 1988-03-29 1989-05-18 Dieter Dr.-Ing. Friedrich
JPH01251789A (ja) * 1988-03-31 1989-10-06 Toshiba Corp プリント基板
JP2761113B2 (ja) * 1991-02-25 1998-06-04 松下電工株式会社 プリント配線板
DE4137045A1 (de) * 1991-11-11 1993-05-13 Siemens Ag Verfahren zur herstellung von lotflaechen auf einer leiterplatte und lotpastenfolie zur durchfuehrung des verfahrens
US5315070A (en) * 1991-12-02 1994-05-24 Siemens Aktiengesellschaft Printed wiring board to which solder has been applied
US5311402A (en) * 1992-02-14 1994-05-10 Nec Corporation Semiconductor device package having locating mechanism for properly positioning semiconductor device within package
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KR100280762B1 (ko) * 1992-11-03 2001-03-02 비센트 비.인그라시아 노출 후부를 갖는 열적 강화된 반도체 장치 및 그 제조방법
GB9302228D0 (en) * 1993-02-05 1993-03-24 Ncr Int Inc Method of forming discrete solder portions on respective contact pads of a printed circuit board
JP3152834B2 (ja) * 1993-06-24 2001-04-03 株式会社東芝 電子回路装置
US5400950A (en) * 1994-02-22 1995-03-28 Delco Electronics Corporation Method for controlling solder bump height for flip chip integrated circuit devices
US5639013A (en) * 1994-12-23 1997-06-17 Ford Motor Company Optimally shaped solder joints for improved reliability and space savings
US5726861A (en) * 1995-01-03 1998-03-10 Ostrem; Fred E. Surface mount component height control

Also Published As

Publication number Publication date
DE69709172T2 (de) 2002-05-02
WO1998032314A3 (en) 1999-06-03
CA2278019A1 (en) 1998-07-23
EP0953277B1 (en) 2001-12-12
BR9714289A (pt) 2000-04-25
EP0953277A2 (en) 1999-11-03
CN1245007A (zh) 2000-02-16
PT953277E (pt) 2002-06-28
JP2001508949A (ja) 2001-07-03
US5936846A (en) 1999-08-10
DE69709172D1 (de) 2002-01-24
WO1998032314A2 (en) 1998-07-23

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