CN102522347B - 一种制备焊料凸块的方法 - Google Patents

一种制备焊料凸块的方法 Download PDF

Info

Publication number
CN102522347B
CN102522347B CN201110439629.2A CN201110439629A CN102522347B CN 102522347 B CN102522347 B CN 102522347B CN 201110439629 A CN201110439629 A CN 201110439629A CN 102522347 B CN102522347 B CN 102522347B
Authority
CN
China
Prior art keywords
solder
silicon wafer
pad
enclosure cavity
height
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201110439629.2A
Other languages
English (en)
Other versions
CN102522347A (zh
Inventor
蔡坚
王水弟
王谦
浦园园
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tsinghua University
Original Assignee
Tsinghua University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tsinghua University filed Critical Tsinghua University
Priority to CN201110439629.2A priority Critical patent/CN102522347B/zh
Priority to PCT/CN2011/084684 priority patent/WO2013091257A1/zh
Publication of CN102522347A publication Critical patent/CN102522347A/zh
Application granted granted Critical
Publication of CN102522347B publication Critical patent/CN102522347B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/0381—Cleaning, e.g. oxide removal step, desmearing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1181—Cleaning, e.g. oxide removal step, desmearing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H01L2224/1184—Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

本发明针对现有技术中因焊球上表面为球面而导致探针不能与焊球良好接触的缺陷，提供一种能够克服上述缺陷的制备焊料凸块的方法。本发明提供一种制备焊料凸块的方法，该方法包括：提供硅圆片，在该硅圆片上需要制备焊料凸块；在所述硅圆片的形成有焊盘的一侧上形成凸点下金属化层；在具有焊盘的位置处在所述凸点下金属化层上制作焊料；对所述焊料进行回流，并且在回流时采用与所述硅圆片平行的限高器来限制所形成的焊料凸块的高度低于未使用限高器时所形成的焊球的高度以使得回流后所形成的焊料凸块的上表面为平面。

Description

一种制备焊料凸块的方法
技术领域
本发明涉及半导体封装领域，尤其涉及一种制备焊料凸块的方法。
背景技术
在硅圆片上和基板上制作焊球是半导体封装中常用的技术，但是这种圆球形的引出端给探针测试芯片带来了很大的难度。如图1所示，由于在通过回流焊工艺形成焊球4时，整个硅圆片上的焊球4的大小肯定是大小不同的，这就有可能出现各个焊球4的上端面不在一个水平面上的情况，从而在对芯片进行测试时就很难确保每根探针1都接触到焊球4，另外，图1中的标号2表示焊盘，标号3表示金属化层。另外，由于焊球4的形状是圆球形的，这会导致另一问题，即在测试时探针1同焊球4的相对位置要绝对精确，稍有偏差，探针1就不能可靠地扎到焊球4的球面上，甚至根本扎不上，如图2所示。
针对上述问题，IBM公司提出一种受控塌陷芯片连接新技术(controlledcollapse chip connection new process)，该技术通过把焊料填充到玻璃模版中、回流后再转移到硅圆片上来制备焊球，由于在转移过程中焊球的形状受到模版形状的约束，所以转移后的焊球表面不是传统焊料回流后所形成的球面状，而是扁平的球形端面，虽然这种扁平的球形端面便于探针测试，但是该技术的流程复杂。
Jae-Woong Nah、Kyung W.Paik、Soon-Jin Cho和Won-Hoe Kim等人在文献“Flip Chip Assembly on PCB Substrate with Coined Solder Bumps”中提出一种用于解决图1和图2中指出的问题的方法，该方法在焊球回流成型后通过压扁的方式让圆球形焊球成为扁平形，但是该方法的缺陷是在压扁焊球时有可能损坏芯片。
发明内容
本发明针对现有技术中存在的上述缺陷，提供一种能够克服上述缺陷的制备焊料凸块的方法。
本发明提供一种制备焊料凸块的方法，该方法包括：
提供硅圆片，在该硅圆片上需要制备焊料凸块；
在所述硅圆片的形成有焊盘的一侧上形成凸点下金属化层；
在具有焊盘的位置处在所述凸点下金属化层上制作焊料；
对所述焊料进行回流，并且在回流时采用与所述硅圆片平行的限高器来限制所形成的焊料凸块的高度低于未使用限高器时所形成的焊球的高度以使得回流后所形成的焊料凸块的上表面为平面。
由于根据本发明的制备焊料凸块的方法是在回流时采用与所述硅圆片平行的限高器来限制所形成的焊料凸块的高度低于未使用限高器时所形成的焊球的高度，所以只要限高器所允许的焊料生长高度低于没有限高器时焊料的实际生长高度，就能够使得最终形成的焊料凸块的上表面为平面，从而在对芯片进行测试时避免了图1和图2所示情形的出现。
附图说明
图1示出了现有技术中因焊球大小不同而导致探针不能与焊球接触的情况；
图2示出了现有技术中因探针偏离正确位置而导致探针不能与焊球接触的情况；
图3示出了根据本发明的制备焊料凸块的方法的流程图；
图4示出了需要在其上制备焊料凸块的硅圆片的截面图；
图5示出了在图4的硅圆片上形成凸点下金属化层之后的截面图；
图6示出了在图5所示的硅圆片上通过电镀法制作焊料后的截面图；
图7示出了在图5所示的硅圆片上通过丝网印刷法制作焊料后的截面图；
图8示出了采用上内壁为平面的容器来限制回流时所形成的焊料凸块的高度的一种实施方式；
图9示出了采用平板来限制回流时所形成的焊料凸块的高度的一种实施方式；
图10是采用根据本发明的制备焊料凸块的方法所制备的焊料凸块的照片；
图11是图10所示的焊料凸块的剖面图。
具体实施方式
下面结合附图来详细描述根据本发明的制备焊料凸块的方法。
如图3所示，根据本发明的制备焊料凸块的方法包括：
S11、提供硅圆片，在该硅圆片上需要制备焊料凸块。
该硅圆片的结构可以如图4所示，其中标号2表示焊盘，标号10表示芯片。应当说明的是，在本说明书中，出于描述方便的原因而仅仅使用了术语“硅圆片”，实际上，根据本发明的制备焊料凸块的方法能够应用于任何需要制备焊料凸块的应用中，而并非仅仅局限于硅圆片，例如，根据本发明的制备焊料凸块的方法还适用于在基板上制备焊料凸块。
S12、在所述硅圆片的形成有焊盘1的一侧上形成凸点下金属化层3。如图5所示。
其中，可以通过电子束蒸发或溅射等工艺在所述硅圆片的形成有焊盘1的一侧上形成凸点下金属化层3。
S13、在具有焊盘1的位置处在所述凸点下金属化层3上制作焊料4。
其中，可以通过以下流程来制作焊料4：在所述凸点下金属化层3上形成掩膜；对位于所述焊盘1上方的掩膜进行刻蚀直到露出所述凸点下金属化层3；在所述凸点下金属化层3上通过电镀法制作焊料4；去除刻蚀后所剩余的掩膜。形成焊料4后的图形如图6所示。
当然，也可以通过以下流程来制作焊料：去除所述凸点下金属化层3使得仅留下位于所述焊盘1上方的凸点下金属化层3；通过丝网印刷法制作焊料4。形成焊料后的图形如图7所示。
以上仅结合图6和图7简要地描述了制作焊料的流程，由于该流程对于本领域技术人员而言是众所周知的，所以这里并未进行详细描述。而且，除了上述的制备焊料的流程之外，本领域技术人员公知的其他制备焊料的流程也是可行的。
S14、对所述焊料4进行回流，并且在回流时采用与所述硅圆片平行的限高器来限制所形成的焊料凸块的高度低于未使用限高器时所形成的焊球的高度以使得回流后所形成的焊料凸块的上表面为平面。
图8示出了采用上内壁为平面的容器5来限制回流时所形成的焊料凸块的高度的实施方式，其中图8示出的是上内壁为平面的容器5的剖面图。在对所述焊料4进行回流时，将制作了焊料后的硅圆片放置到所述上内壁为平面的容器5内，该容器5的上内壁与所述硅圆片平行并且所述上内壁与所述硅圆片之间的距离小于不使用所述容器5时所形成的焊球的高度，这样所形成的焊料凸块的上表面就无法形成球面，而是形成平面，从而能够使得回流后所形成的各个焊料凸块4的高度一致，消除了图1和图2中的缺陷。当然，由于球径存在着分散性，所以最终形成的平面的面积有微小的差异也是可以理解的，但是只要满足芯片测试的要求即可。而且，应当理解的是，虽然图8中示出的限高器是上内壁为平面的容器5，但是实际上，限高器的形状和结构并不局限于此，只要能够在回流时限制焊料凸块的生长高度使得所形成的焊料凸块的上表面为平面的装置，就都位于本发明的保护范围内。例如，限高器也可以是被固定在所述硅圆片上方并且与所述硅圆片平行的平板6，如图9所示。
另外，通过回流工艺形成焊料凸块之后的后续工艺，例如通过电镀法制作焊料4时，在回流之后还需去除多余的凸点下金属化层3，而通过丝网印刷法形成焊料4时，在回流之后还需清洗助焊剂，等等。由于这些后续工艺也是本领域技术人员公知的，所以此处不再赘述。
另外，图10还示出了采用根据本发明的制备焊料凸块的方法所实际制作完成的焊料凸块的照片(俯视图)，图11是图10的剖面图，可以看出通过根据本发明的制备焊料凸块的方法能够确保所形成的焊料凸块的上表面为平面，从而避免了在芯片测试时探针不能与部分焊料凸块良好接触的缺陷。
以上仅结合本发明的优选实施方式对本发明进行了详细描述，但是本领域技术人员应当理解，在不背离本发明精神和范围的情况下，可以对本发明做出各种变形和修改。

Claims (6)

1.一种制备焊料凸块的方法，该方法包括：
提供硅圆片，在该硅圆片上需要制备焊料凸块；
在所述硅圆片的形成有焊盘的一侧上形成凸点下金属化层；
在具有焊盘的位置处在所述凸点下金属化层上制作焊料；
对所述焊料进行回流，并且在回流时采用与所述硅圆片平行的限高器来限制所形成的焊料凸块的高度低于未使用限高器时所形成的焊球的高度以使得回流后所形成的焊料凸块的上表面为平面。
2.根据权利要求1所述的方法，其中，在所述硅圆片的形成有焊盘的一侧上形成凸点下金属化层包括：
通过电子束蒸发或溅射工艺在所述硅圆片的形成有焊盘的一侧上形成凸点下金属化层。
3.根据权利要求1所述的方法，其中，在具有焊盘的位置处在所述凸点下金属化层上制作焊料包括：
在所述凸点下金属化层上形成掩膜；
对位于所述焊盘上方的掩膜进行刻蚀直到露出所述凸点下金属化层；
在所述凸点下金属化层上制作焊料；
去除刻蚀后所剩余的掩膜。
4.根据权利要求1所述的方法，其中，在具有焊盘的位置处在所述凸点下金属化层上制作焊料包括：
去除所述凸点下金属化层使得仅留下位于所述焊盘上方的凸点下金属化层；
在仅位于焊盘上方的凸点下金属化层上通过丝网印刷法制作焊料。
5.根据权利要求1所述的方法，其中，所述限高器为被固定在所述硅圆片上方并且与所述硅圆片平行的平板。
6.根据权利要求1所述的方法，其中，所述限高器为上内壁为平面的容器，并且在对所述焊料进行回流时，将制作了焊料后的硅圆片放置到所述容器内，该容器的上内壁与所述硅圆片平行并且所述上内壁与所述硅圆片之间的距离小于不使用所述容器时所形成的焊球的高度。
CN201110439629.2A 2011-12-23 2011-12-23 一种制备焊料凸块的方法 Active CN102522347B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201110439629.2A CN102522347B (zh) 2011-12-23 2011-12-23 一种制备焊料凸块的方法
PCT/CN2011/084684 WO2013091257A1 (zh) 2011-12-23 2011-12-26 一种制备焊料凸块的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201110439629.2A CN102522347B (zh) 2011-12-23 2011-12-23 一种制备焊料凸块的方法

Publications (2)

Publication Number Publication Date
CN102522347A CN102522347A (zh) 2012-06-27
CN102522347B true CN102522347B (zh) 2015-04-29

Family

ID=46293224

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110439629.2A Active CN102522347B (zh) 2011-12-23 2011-12-23 一种制备焊料凸块的方法

Country Status (2)

Country Link
CN (1) CN102522347B (zh)
WO (1) WO2013091257A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103874342B (zh) * 2014-03-26 2017-07-04 新华三技术有限公司 电路板组装方法及电路板
CN104201156A (zh) * 2014-08-08 2014-12-10 天水华天科技股份有限公司 基于基板的凸点倒装芯片csp封装件、基板及制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1355555A (zh) * 2000-11-28 2002-06-26 中国科学院微电子中心 半导体芯片焊料凸点加工方法
CN101276760A (zh) * 2007-01-24 2008-10-01 日本特殊陶业株式会社 具有焊料突起的布线基板的制造方法、布线基板
CN101894766A (zh) * 2009-05-22 2010-11-24 中芯国际集成电路制造(上海)有限公司 焊料凸块制作方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5633535A (en) * 1995-01-27 1997-05-27 Chao; Clinton C. Spacing control in electronic device assemblies
US5936846A (en) * 1997-01-16 1999-08-10 Ford Global Technologies Optimized solder joints and lifter pads for improving the solder joint life of surface mount chips
US6395584B2 (en) * 1998-12-22 2002-05-28 Ficta Technology Inc. Method for improving the liquid dispensing of IC packages
US6617696B1 (en) * 2002-03-14 2003-09-09 Fairchild Semiconductor Corporation Supporting control gate connection on a package using additional bumps

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1355555A (zh) * 2000-11-28 2002-06-26 中国科学院微电子中心 半导体芯片焊料凸点加工方法
CN101276760A (zh) * 2007-01-24 2008-10-01 日本特殊陶业株式会社 具有焊料突起的布线基板的制造方法、布线基板
CN101894766A (zh) * 2009-05-22 2010-11-24 中芯国际集成电路制造(上海)有限公司 焊料凸块制作方法

Also Published As

Publication number Publication date
WO2013091257A1 (zh) 2013-06-27
CN102522347A (zh) 2012-06-27

Similar Documents

Publication Publication Date Title
JP6374062B2 (ja) マイクロｌｅｄモジュール及びその製造方法
JP2006202991A (ja) 回路基板及びその製造方法、並びに半導体パッケージ及びその製造方法
US20120267778A1 (en) Circuit board, semiconductor element, semiconductor device, method for manufacturing circuit board, method for manufacturing semiconductor element, and method for manufacturing semiconductor device
TW200812038A (en) Semiconductor package and the method for fabricating thereof
TW200931611A (en) Template for forming solder bumps, method of manufacturing the template and method of inspecting solder bumps using the template
CN102522347B (zh) 一种制备焊料凸块的方法
US9524944B2 (en) Method for fabricating package structure
US9059004B2 (en) Method for chip scale package and package structure thereof
US20130095611A1 (en) Packaging Methods for Semiconductor Devices
US9559076B2 (en) Package having substrate with embedded metal trace overlapped by landing pad
TWI453881B (zh) 封裝結構及其製法
CN103325758B (zh) 一种防锡球塌陷的fcqfn封装件及其制作工艺
JP2008060483A (ja) 半導体装置の実装構造体およびその製造方法
CN102983087B (zh) 倒装芯片bga组装工艺
KR101130498B1 (ko) 범프를 갖는 반도체 디바이스
JP6147061B2 (ja) フリップチップ型半導体発光素子、半導体装置及びその製造方法
US20050266611A1 (en) Flip chip packaging method and flip chip assembly thereof
CN113594119A (zh) 半导体封装及其制造方法
JP2001230537A (ja) ハンダバンプの形成方法
JP6762871B2 (ja) 平坦化によってはんだパッド形態差を低減する方法
CN203589010U (zh) 一种防锡球塌陷的fcqfn封装件
TWI360206B (en) Template for forming solder bumps, method of manuf
TWI222732B (en) Formation method for conductive bump
CN117995690A (zh) 芯片倒装方法以及倒装芯片
KR101033773B1 (ko) 솔더 범프 형성용 템플릿 및 이를 이용한 솔더 범프 형성 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant