ES2137909T3 - Sistema de bus de control y datos en paquetes de alta velocidad arbitrado por un modulo paralelo de interconexion. - Google Patents

Sistema de bus de control y datos en paquetes de alta velocidad arbitrado por un modulo paralelo de interconexion.

Info

Publication number
ES2137909T3
ES2137909T3 ES97933270T ES97933270T ES2137909T3 ES 2137909 T3 ES2137909 T3 ES 2137909T3 ES 97933270 T ES97933270 T ES 97933270T ES 97933270 T ES97933270 T ES 97933270T ES 2137909 T3 ES2137909 T3 ES 2137909T3
Authority
ES
Spain
Prior art keywords
data bus
arbitration
high speed
bus
module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES97933270T
Other languages
English (en)
Other versions
ES2137909T1 (es
Inventor
Robert T Regis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
InterDigital Technology Corp
Original Assignee
InterDigital Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by InterDigital Technology Corp filed Critical InterDigital Technology Corp
Publication of ES2137909T1 publication Critical patent/ES2137909T1/es
Application granted granted Critical
Publication of ES2137909T3 publication Critical patent/ES2137909T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7073—Synchronisation aspects
    • H04B1/7075—Synchronisation aspects with code phase acquisition
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/374—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a self-select method with individual priority code comparator
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/376—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a contention resolving method, e.g. collision detection, collision avoidance
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7073—Synchronisation aspects
    • H04B1/7075—Synchronisation aspects with code phase acquisition
    • H04B1/70751—Synchronisation aspects with code phase acquisition using partial detection
    • H04B1/70753—Partial phase search
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7073—Synchronisation aspects
    • H04B1/7075—Synchronisation aspects with code phase acquisition
    • H04B1/70755—Setting of lock conditions, e.g. threshold
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7073—Synchronisation aspects
    • H04B1/7075—Synchronisation aspects with code phase acquisition
    • H04B1/70758—Multimode search, i.e. using multiple search strategies
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7073—Synchronisation aspects
    • H04B1/7075—Synchronisation aspects with code phase acquisition
    • H04B1/708—Parallel implementation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
    • H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
    • H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
    • H04B2201/70702—Intercell-related aspects

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
  • Small-Scale Networks (AREA)
  • Communication Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Information Transfer Systems (AREA)
  • Traffic Control Systems (AREA)
  • Vehicle Body Suspensions (AREA)
  • Train Traffic Observation, Control, And Security (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

SE EXPONE UN SISTEMA DE BUS DE CONTROL Y DATOS A GRAN VELOCIDAD, HABILITADO POR UN MODULO PARALELO Y EN PAQUETES DE INTERCONEXION, QUE PERMITE COMUNICACIONES A GRAN VELOCIDAD ENTRE MODULOS DE MICROPROCESADOR EN UN ENTORNO DE PROCESO DIGITAL MAS COMPLEJO. EL SISTEMA INCORPORA UNA ARQUITECTURA DE HARDWARE SIMPLIFICADA, QUE INCORPORA UN SISTEMA RAPIDO DE PUESTA EN COLA DEL TIPO FIFO (PRIMERO QUE ENTRA, PRIMERO QUE SALE) A 12,5 MHZ, SEÑALES DE RELOJ DE NIVEL COMPATIBLE CON EL CMOS TTL, ARBITRAJE MAESTRO DE UN UNICO BUS, RELOJ SINCRONO, DMA, Y DIRECCIONAMIENTO DE UN MODULO UNICO PARA SISTEMAS DE MULTIPROCESADOR. EL SISTEMA INCLUYE UN BUS DE DATOS EN PARALELO CON MASTERS DE BUS COMPARTIDOS QUE RESIDEN EN CADA MODULO DE PROCESO Y QUE ESTABLECEN LOS PROTOCOLOS DE COMUNICACION Y TRANSFERENCIA DE DATOS. EL ARBITRAJE DEL BUS SE REALIZA POR UNA LINEA DEDICADA Y EN SERIE PARA ARBITRAJE, Y CADA MODULO SOLICITANTE COMPITE PARA ACCEDER AL BUS DE DATOS EN PARALELO COLOCANDO LA LINEA DE ARBITRAJE EN LA DIRECCION DEL MODULO Y SUPERVISANDO LAS POSIBLES COLISIONES EN LA LINEA DE ARBITRAJE.
ES97933270T 1996-06-27 1997-06-27 Sistema de bus de control y datos en paquetes de alta velocidad arbitrado por un modulo paralelo de interconexion. Expired - Lifetime ES2137909T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/671,221 US5754803A (en) 1996-06-27 1996-06-27 Parallel packetized intermodule arbitrated high speed control and data bus

Publications (2)

Publication Number Publication Date
ES2137909T1 ES2137909T1 (es) 2000-01-01
ES2137909T3 true ES2137909T3 (es) 2002-11-16

Family

ID=24693614

Family Applications (1)

Application Number Title Priority Date Filing Date
ES97933270T Expired - Lifetime ES2137909T3 (es) 1996-06-27 1997-06-27 Sistema de bus de control y datos en paquetes de alta velocidad arbitrado por un modulo paralelo de interconexion.

Country Status (14)

Country Link
US (4) US5754803A (es)
EP (2) EP0907921B1 (es)
JP (2) JP3604398B2 (es)
KR (1) KR100321490B1 (es)
CN (2) CN1107913C (es)
AT (1) ATE216100T1 (es)
AU (1) AU3649597A (es)
CA (1) CA2259257C (es)
DE (2) DE69711877T2 (es)
DK (1) DK0907921T3 (es)
ES (1) ES2137909T3 (es)
HK (2) HK1017108A1 (es)
PT (1) PT907921E (es)
WO (1) WO1997050039A1 (es)

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Also Published As

Publication number Publication date
KR20000022283A (ko) 2000-04-25
WO1997050039A1 (en) 1997-12-31
PT907921E (pt) 2002-09-30
EP0907921A1 (en) 1999-04-14
KR100321490B1 (ko) 2002-06-20
JP2004318901A (ja) 2004-11-11
DK0907921T3 (da) 2002-08-05
JPH11513158A (ja) 1999-11-09
CA2259257C (en) 2001-05-08
ES2137909T1 (es) 2000-01-01
JP3604398B2 (ja) 2004-12-22
CN1107913C (zh) 2003-05-07
EP1174798A3 (en) 2003-12-17
CA2259257A1 (en) 1997-12-31
HK1044388A1 (zh) 2002-10-18
US5754803A (en) 1998-05-19
US6823412B2 (en) 2004-11-23
DE69711877D1 (de) 2002-05-16
DE907921T1 (de) 1999-10-21
CN1228723C (zh) 2005-11-23
HK1017108A1 (en) 1999-11-12
EP0907921B1 (en) 2002-04-10
US6405272B1 (en) 2002-06-11
AU3649597A (en) 1998-01-14
CN1442795A (zh) 2003-09-17
EP1174798A2 (en) 2002-01-23
CN1223730A (zh) 1999-07-21
US20050097251A1 (en) 2005-05-05
DE69711877T2 (de) 2002-11-28
US20020184422A1 (en) 2002-12-05
ATE216100T1 (de) 2002-04-15

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