ES2072396T3 - Aparato decodificador. - Google Patents

Aparato decodificador.

Info

Publication number
ES2072396T3
ES2072396T3 ES90308249T ES90308249T ES2072396T3 ES 2072396 T3 ES2072396 T3 ES 2072396T3 ES 90308249 T ES90308249 T ES 90308249T ES 90308249 T ES90308249 T ES 90308249T ES 2072396 T3 ES2072396 T3 ES 2072396T3
Authority
ES
Spain
Prior art keywords
error
memory
error correction
decoding device
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES90308249T
Other languages
English (en)
Inventor
Tadashi C O Patents Div Fukami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Application granted granted Critical
Publication of ES2072396T3 publication Critical patent/ES2072396T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1806—Pulse code modulation systems for audio signals
    • G11B20/1809—Pulse code modulation systems for audio signals by interleaving
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1876—Interpolating methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

UN APARATO DESCODIFICADOR EN EL QUE PARA UNA PLURALIDAD DE SIMBOLOS DISPUESTOS EN UNA FORMA DE MATRIZ, SE CODIFICAN PRIMERO Y SEGUNDO CODIGOS DE CORRECCION DE ERRORES PARA CADA PLURALIDAD DE SIMBOLOS RESPECTIVAMENTE COLOCADOS EN UNA PRIMERA DIRECCION Y EN UNA SEGUNDA DIRECCION, Y DONDE LOS DATOS DE ENTRADA SE TRANSMITEN EN LA PRIMERA DIRECCION. EL APARATO DE DESCODIFICACION INCLUYE UNA PRIMERA MEMORIA (40) PARA ESCRIBIR DATOS DE ENTRADA, UN DETECTOR DE ERRORES (36) PARA DETECTAR UN ERROR DE LOS DATOS DE ENTRADA QUE SE ESCRIBEN DENTRO DE LA PRIMERA MEMORIA (40), BASADOS EN EL PRIMER CODIGO DE CORRECCION DE ERRORES Y PARA GENERAR DATOS DE ERROR DESDE UN PRIMER CODIGO DE CORRECCION DE ERRORES. UNA SEGUNDA MEMORIA (40) ESTA DISPUESTA PARA ESCRIBIR DATOS DE ERROR DEL PRIMER CODIGO DE CORRECCION DE ERRORES Y UN CORRECTOR DE ERRORES (41) ESTA PARA EJECUTAR SECUENCIALMENTE CORRECCIONES DE ERRORES DE LOS PRIMERO Y SEGUNDO CODIGOS DE CORRECCION DE ERRORES PARA LOS DATOS DE ENTRADA QUE SE ESCRIBEN ENLA PRIMERA MEMORIA (40) UTILIZANDO LOS DATOS DE ERROR DEL PRIMER CODIGO DE CORRECCION DE ERRORES QUE SE ESCRIBEN EN LA SEGUNDA MEMORIA (40).
ES90308249T 1989-07-29 1990-07-27 Aparato decodificador. Expired - Lifetime ES2072396T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19782789A JP3153995B2 (ja) 1989-07-29 1989-07-29 復号装置

Publications (1)

Publication Number Publication Date
ES2072396T3 true ES2072396T3 (es) 1995-07-16

Family

ID=16381000

Family Applications (1)

Application Number Title Priority Date Filing Date
ES90308249T Expired - Lifetime ES2072396T3 (es) 1989-07-29 1990-07-27 Aparato decodificador.

Country Status (8)

Country Link
US (1) US5430741A (es)
EP (1) EP0411835B1 (es)
JP (1) JP3153995B2 (es)
KR (1) KR0178514B1 (es)
CA (1) CA2022024C (es)
DE (1) DE69019432T2 (es)
ES (1) ES2072396T3 (es)
MY (1) MY106736A (es)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0571096B1 (en) * 1992-05-18 1999-06-23 Canon Kabushiki Kaisha Data processing apparatus
EP0748130B1 (en) * 1995-06-05 2002-09-25 Sony Electronics Inc. Recording and reproducing digital signals
EP0790615A3 (en) * 1996-02-19 1998-04-15 Sony Corporation Data decoding apparatus and method and data reproduction apparatus
JPH10172243A (ja) * 1996-12-11 1998-06-26 Sony Corp 円盤状記録媒体および円盤状記録媒体再生装置
EP1293978A1 (en) * 2001-09-10 2003-03-19 STMicroelectronics S.r.l. Coding/decoding process and device, for instance for disk drives
JP7166823B2 (ja) * 2018-07-18 2022-11-08 日本サーモスタット株式会社 湯水混合栓

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5961332A (ja) * 1982-09-30 1984-04-07 Nec Corp 誤り訂正回路
JPH0812612B2 (ja) * 1983-10-31 1996-02-07 株式会社日立製作所 誤り訂正方法及び装置
JPS62120670A (ja) * 1985-11-20 1987-06-01 Sony Corp デ−タの誤り訂正方法
JPS62177768A (ja) * 1986-01-31 1987-08-04 Sony Corp エラ−訂正装置
JP2751150B2 (ja) * 1986-03-11 1998-05-18 ソニー株式会社 磁気テープの記録装置および再生装置
US4845714A (en) * 1987-06-08 1989-07-04 Exabyte Corporation Multiple pass error correction process and apparatus for product codes

Also Published As

Publication number Publication date
DE69019432T2 (de) 1995-09-14
KR910003958A (ko) 1991-02-28
US5430741A (en) 1995-07-04
EP0411835A3 (en) 1992-01-15
JPH0362624A (ja) 1991-03-18
JP3153995B2 (ja) 2001-04-09
EP0411835A2 (en) 1991-02-06
MY106736A (en) 1995-07-31
CA2022024C (en) 2000-03-07
EP0411835B1 (en) 1995-05-17
CA2022024A1 (en) 1991-01-30
DE69019432D1 (de) 1995-06-22
KR0178514B1 (ko) 1999-04-01

Similar Documents

Publication Publication Date Title
GB1511806A (en) Error detection and correction in data processing systems
US3573728A (en) Memory with error correction for partial store operation
DE3587145D1 (de) Puffersystem mit erkennung von lese- oder schreibschaltungsfehlern.
DE3684788D1 (de) Fehlerkorrektur fuer paket-fehler-korrektur-code.
US4712216A (en) Method and device for correcting errors in memories
DE69220818T2 (de) Verfahren und Einrichtung zur Fehlererkennung in Recherspeichern versehen mit Mehrfach-bit-Ausgängen
DE69719086D1 (de) Zeitverteilte entfernung von fehlerkorrekturcodes (ecc) zur korrektur von speicherfehlern
FI844343A0 (fi) Enligt roerledningssystemet fungerande felkorrigeringssystem.
DE69031527D1 (de) Pipelinefehlerprüfung und Korrektur für Cache-Speicher
ATE477537T1 (de) Prädiktive generierung von fehlerkorrekturkodes für hochgeschwindigkeits-byte-schreiben in einem halbleiterspeicher
GB1481373A (en) Random access memory systems
KR890702121A (ko) 바이트 기입 에러 코드 방법 및 장치
NL7804674A (nl) Geheugen met detektie en korrektie van fouten.
DE3473365D1 (en) Single error correction circuit for system memory
JPS5486245A (en) Memory error logger for distinguishing solid error from transient error
AU7820987A (en) Parallel processor error checking
ATE14947T1 (de) Datenverarbeitungsvorrichtung zur verarbeitung von datenwoertern mit mehreren symbolen, auf einem symbolkorrigierenden kode basiert und mit mehreren betriebsweisen.
DE3484587D1 (de) Geraet zur verringerung des zur fehlererkennung- und korrektur erforderlichen speichers in datenverarbeitungsmaschinen.
DE69019822D1 (de) Verfahren und Vorrichtung zur Prüfung des Inhalts und der Adresse einer Speicheranordnung.
JPS57502025A (es)
IT953759B (it) Sistema e metodo epr la correzione di errori per memorie memorie monolitiche
KR840007190A (ko) 버퍼기억장치의 단일비트 에러처리 시스템
AU570415B2 (en) Multiprocessor system
ES2072396T3 (es) Aparato decodificador.
SE8700712D0 (sv) Tremodult minnessystem med symbolbreda minneschips och med felskyddsfacilitet, varvid varje symbol bestar av 2?72i+1 bitar

Legal Events

Date Code Title Description
FG2A Definitive protection

Ref document number: 411835

Country of ref document: ES