ES2030389T3 - Proceso de fabricacion de circuitos integrados para formar un transistor bipolar provisto de regiones de base extrinsecas. - Google Patents
Proceso de fabricacion de circuitos integrados para formar un transistor bipolar provisto de regiones de base extrinsecas.Info
- Publication number
- ES2030389T3 ES2030389T3 ES198686308296T ES86308296T ES2030389T3 ES 2030389 T3 ES2030389 T3 ES 2030389T3 ES 198686308296 T ES198686308296 T ES 198686308296T ES 86308296 T ES86308296 T ES 86308296T ES 2030389 T3 ES2030389 T3 ES 2030389T3
- Authority
- ES
- Spain
- Prior art keywords
- bipolar transistor
- base regions
- extrinsic base
- manufacturing process
- integrated circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 238000000034 method Methods 0.000 abstract 3
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000010276 construction Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
- H01L21/2652—Through-implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/01—Bipolar transistors-ion implantation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
INCLUYE LOS PASOS PARA LA FORMACION Y AUTO-ALINEAMIENTO DE LA ZONA QUE NO INVADE SUSTANCIALMENTE EL EMISOR. EN LOS PROCESOS CONOCIDOS PARA LA FABRICACION DE TRANSISTORES QUE REQUIEREN UN LECHO, PRECISAN UN COLECTOR BASE MAS ALTO POR DETENCIONES Y POR AVERIAS DE VOLTAGE.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/794,357 US4669179A (en) | 1985-11-01 | 1985-11-01 | Integrated circuit fabrication process for forming a bipolar transistor having extrinsic base regions |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2030389T3 true ES2030389T3 (es) | 1992-11-01 |
Family
ID=25162417
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES198686308296T Expired - Lifetime ES2030389T3 (es) | 1985-11-01 | 1986-10-24 | Proceso de fabricacion de circuitos integrados para formar un transistor bipolar provisto de regiones de base extrinsecas. |
Country Status (6)
Country | Link |
---|---|
US (1) | US4669179A (es) |
EP (1) | EP0221742B1 (es) |
JP (1) | JPS62113471A (es) |
AT (1) | ATE74228T1 (es) |
DE (1) | DE3684555D1 (es) |
ES (1) | ES2030389T3 (es) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4812417A (en) * | 1986-07-30 | 1989-03-14 | Mitsubishi Denki Kabushiki Kaisha | Method of making self aligned external and active base regions in I.C. processing |
US4740478A (en) * | 1987-01-30 | 1988-04-26 | Motorola Inc. | Integrated circuit method using double implant doping |
US5258317A (en) * | 1992-02-13 | 1993-11-02 | Integrated Device Technology, Inc. | Method for using a field implant mask to correct low doping levels at the outside edges of the base in a walled-emitter transistor structure |
US5338695A (en) * | 1992-11-24 | 1994-08-16 | National Semiconductor Corporation | Making walled emitter bipolar transistor with reduced base narrowing |
US5369052A (en) * | 1993-12-06 | 1994-11-29 | Motorola, Inc. | Method of forming dual field oxide isolation |
US5548158A (en) * | 1994-09-02 | 1996-08-20 | National Semiconductor Corporation | Structure of bipolar transistors with improved output current-voltage characteristics |
US5617357A (en) * | 1995-04-07 | 1997-04-01 | Advanced Micro Devices, Inc. | Flash EEPROM memory with improved discharge speed using substrate bias and method therefor |
US5849613A (en) * | 1997-10-23 | 1998-12-15 | Chartered Semiconductor Manufacturing Ltd. | Method and mask structure for self-aligning ion implanting to form various device structures |
SE518710C2 (sv) * | 2000-06-26 | 2002-11-12 | Ericsson Telefon Ab L M | Förfarande för att förbättra transistorprestanda samt transistoranordning och integrerad krets |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2358748A1 (fr) * | 1976-07-15 | 1978-02-10 | Radiotechnique Compelec | Procede d'autoalignement des elements d'un dispositif semi-conducteur et dispositif realise suivant ce procede |
US4111726A (en) * | 1977-04-01 | 1978-09-05 | Burroughs Corporation | Bipolar integrated circuit process by separately forming active and inactive base regions |
US4118250A (en) * | 1977-12-30 | 1978-10-03 | International Business Machines Corporation | Process for producing integrated circuit devices by ion implantation |
US4484211A (en) * | 1981-02-04 | 1984-11-20 | Matsushita Electric Industrial Co., Ltd. | Oxide walled emitter |
DE3115029A1 (de) * | 1981-04-14 | 1982-11-04 | Deutsche Itt Industries Gmbh, 7800 Freiburg | "verfahren zur herstellung eines integrierten bipolaren planartransistors" |
FR2508704B1 (fr) * | 1981-06-26 | 1985-06-07 | Thomson Csf | Procede de fabrication de transistors bipolaires integres de tres petites dimensions |
US4433471A (en) * | 1982-01-18 | 1984-02-28 | Fairchild Camera & Instrument Corporation | Method for the formation of high density memory cells using ion implantation techniques |
US4498227A (en) * | 1983-07-05 | 1985-02-12 | Fairchild Camera & Instrument Corporation | Wafer fabrication by implanting through protective layer |
US4573256A (en) * | 1983-08-26 | 1986-03-04 | International Business Machines Corporation | Method for making a high performance transistor integrated circuit |
US4574469A (en) * | 1984-09-14 | 1986-03-11 | Motorola, Inc. | Process for self-aligned buried layer, channel-stop, and isolation |
JPS61193440A (ja) * | 1985-02-22 | 1986-08-27 | Nec Corp | 半導体装置の製造方法 |
-
1985
- 1985-11-01 US US06/794,357 patent/US4669179A/en not_active Expired - Lifetime
-
1986
- 1986-10-24 ES ES198686308296T patent/ES2030389T3/es not_active Expired - Lifetime
- 1986-10-24 EP EP86308296A patent/EP0221742B1/en not_active Expired - Lifetime
- 1986-10-24 AT AT86308296T patent/ATE74228T1/de not_active IP Right Cessation
- 1986-10-24 DE DE8686308296T patent/DE3684555D1/de not_active Expired - Lifetime
- 1986-10-31 JP JP61261740A patent/JPS62113471A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
EP0221742A3 (en) | 1989-07-05 |
ATE74228T1 (de) | 1992-04-15 |
US4669179A (en) | 1987-06-02 |
DE3684555D1 (de) | 1992-04-30 |
EP0221742A2 (en) | 1987-05-13 |
EP0221742B1 (en) | 1992-03-25 |
JPS62113471A (ja) | 1987-05-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG2A | Definitive protection |
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