ES2003961A6 - Dispositivo de circuito para regeneracion y sincronizacion de una senal digital - Google Patents

Dispositivo de circuito para regeneracion y sincronizacion de una senal digital

Info

Publication number
ES2003961A6
ES2003961A6 ES8603299A ES8603299A ES2003961A6 ES 2003961 A6 ES2003961 A6 ES 2003961A6 ES 8603299 A ES8603299 A ES 8603299A ES 8603299 A ES8603299 A ES 8603299A ES 2003961 A6 ES2003961 A6 ES 2003961A6
Authority
ES
Spain
Prior art keywords
digital signal
vzl
decision logic
delay
delay line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES8603299A
Other languages
English (en)
Inventor
Michael Klein
Joachim Woelk
Shao Han Liu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Spain SA
Original Assignee
Alcatel Standard Electrics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Standard Electrics SA filed Critical Alcatel Standard Electrics SA
Publication of ES2003961A6 publication Critical patent/ES2003961A6/es
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

UNA LINEA DE RETARDO VARIABLE (VZL) ESTA CONECTADA EN SERIE CON UNA LOGICA DE DECISION (EL) Y ES ATRAVESADA POR UNA SEÑAL DIGITAL. LA LOGICA DE DECISION (EL) ESTA CONECTADA A UNA UNIDAD DE CONTROL DE RETARDO (VRE) POR LINEAS DE CONTROL (UPO, DOWNO) Y LA LINEA DE RETARDO (VZL) ESTA CONECTADA A LA UNIDAD DE CONTROL DE RETARDO (VRE) POR LINEAS DE DIRECCION (S0, S1, S2, S3). LA LOGICA DE DECISION (EL) CONTIENE UN CIRCUITO DE MUESTREO (AS), EL CUAL SE APLICA EL RELOJ DEL SISTEMA (CK) POR UNA LINEA DE RELOJ (TL), Y UN MEDIO DE EVALUACION (AWE). UNA SEÑAL DIGITAL ENTRANTE ES MUESTREADA EN CINCO INSTANTES DIFERENTES Y ENTONCES EVALUADA, TENIENDO EN CUENTA LA PRESENCIA DE UN RETARDO MINIMO O MAXIMO DE LA LINEA DE RETARDO (VZL). LA RELACION DE FASES ENTRE EL RELOJ DEL SISTEMA Y LA SEÑAL DE DATOS PUEDE SER TOMADA A TRAVES DE LA PRIMERA O DE LA SEGUNDA SALIDA DE INDICACION DE ESTADO (Z0, Z1) DEL MEDIO DE EVALUACION (AWE) EN CUALQUIER MOMENTO.
ES8603299A 1985-12-07 1986-12-05 Dispositivo de circuito para regeneracion y sincronizacion de una senal digital Expired ES2003961A6 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19853543392 DE3543392A1 (de) 1985-12-07 1985-12-07 Schaltungsanordnung zum regenerieren und synchronisieren eines digitalen signales

Publications (1)

Publication Number Publication Date
ES2003961A6 true ES2003961A6 (es) 1988-12-01

Family

ID=6287968

Family Applications (1)

Application Number Title Priority Date Filing Date
ES8603299A Expired ES2003961A6 (es) 1985-12-07 1986-12-05 Dispositivo de circuito para regeneracion y sincronizacion de una senal digital

Country Status (3)

Country Link
EP (1) EP0225587B1 (es)
DE (2) DE3543392A1 (es)
ES (1) ES2003961A6 (es)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3702614A1 (de) * 1987-01-29 1988-08-11 Standard Elektrik Lorenz Ag Digitales koppelnetz fuer leitungs- und paketvermittlung und koppeleinrichtung hierzu
BE1000512A7 (nl) * 1987-05-07 1989-01-10 Bell Telephone Mfg Schakelnetwerk.
EP0364451A1 (en) * 1988-03-26 1990-04-25 BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap Synchronizing circuit
DE59008700D1 (de) * 1989-09-19 1995-04-20 Siemens Ag Synchronisiereinrichtung für ein Digitalsignal.
DE3931259A1 (de) * 1989-09-19 1991-03-28 Siemens Ag Verfahren zur fortlaufenden anpassung der phase eines digitalsignals an einen takt
DE4025004A1 (de) * 1990-08-07 1992-02-13 Standard Elektrik Lorenz Ag Schaltungsanordnung zum regenerieren und synchronisieren eines digitalen signals
EP0562183A1 (en) * 1992-03-27 1993-09-29 ALCATEL BELL Naamloze Vennootschap Synchronization method and device realizing said method
DE4434803C1 (de) * 1994-09-29 1996-03-07 Ant Nachrichtentech Verfahren und Anordnung zur Abtastung eines seriellen Bitstromes
US6130566A (en) * 1996-10-30 2000-10-10 Yokomizo; Akira Digital wave shaping circuit, frequency multiplying circuit, and external synchronizing method, and external synchronizing circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3441501A1 (de) * 1984-11-14 1986-05-15 Standard Elektrik Lorenz Ag, 7000 Stuttgart Schaltungsanordnung zum regenerieren und synchronisieren eines digitalen signals

Also Published As

Publication number Publication date
EP0225587A3 (de) 1991-04-10
EP0225587A2 (de) 1987-06-16
DE3543392A1 (de) 1987-06-25
EP0225587B1 (de) 1993-02-24
DE3687825D1 (de) 1993-04-01

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Legal Events

Date Code Title Description
SA6 Expiration date (snapshot 920101)

Free format text: 2006-12-05

FD1A Patent lapsed

Effective date: 20021207