Classifications

• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02002—Preparing wafers
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/02—Pretreatment of the material to be coated
  • C23C16/0227—Pretreatment of the material to be coated by cleaning or etching
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
  • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
  • C23C16/32—Carbides
  • C23C16/325—Silicon carbide
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/56—After-treatment
• • H—ELECTRICITY
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02367—Substrates
  • H01L21/0237—Materials
  • H01L21/02373—Group 14 semiconducting materials
  • H01L21/02376—Carbon, e.g. diamond-like carbon
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02367—Substrates
  • H01L21/0237—Materials
  • H01L21/02373—Group 14 semiconducting materials
  • H01L21/02378—Silicon carbide
• • H—ELECTRICITY
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02436—Intermediate layers between substrates and deposited layers
  • H01L21/02439—Materials
  • H01L21/02441—Group 14 semiconducting materials
  • H01L21/02447—Silicon carbide
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02436—Intermediate layers between substrates and deposited layers
  • H01L21/02494—Structure
  • H01L21/02496—Layer structure
  • H01L21/02502—Layer structure consisting of two layers
• • H—ELECTRICITY
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  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02436—Intermediate layers between substrates and deposited layers
  • H01L21/02494—Structure
  • H01L21/02513—Microstructure
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02518—Deposited layers
  • H01L21/02521—Materials
  • H01L21/02524—Group 14 semiconducting materials
  • H01L21/02529—Silicon carbide
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  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02518—Deposited layers
  • H01L21/0257—Doping during depositing
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  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02612—Formation types
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
  • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• • H—ELECTRICITY
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  • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
  • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
  • H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices

Definitions

• TITLE METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE BASED ON SILICON CARBIDE AND STRUCTURE
• the present invention relates to the field of semiconductor materials for microelectronic components. It relates in particular to a process for manufacturing a semiconductor structure comprising an active layer of high-quality monocrystalline silicon carbide comprising or intended to accommodate electronic components, said active layer being placed on a support layer of polysilicon carbide. -crystalline.
• the invention also relates to an intermediate composite structure obtained during said process.
• SiC silicon carbide
• Power devices and integrated power systems based on monocrystalline silicon carbide can handle much higher power density compared to their traditional silicon counterparts, and this with smaller active area dimensions.
• To further limit the dimensions of power devices on SiC it is advantageous to manufacture vertical rather than lateral components. For this, vertical electrical conduction, between an electrode arranged on the front face of the assembly of components and an electrode arranged on the rear face, must be authorized by said assembly.
• a well-known thin film transfer solution is the Smart CutTM process, based on light ion implantation and direct bonding assembly.
• Such a method makes it possible, for example, to manufacture a composite structure comprising a thin layer of monocrystalline SiC (c-SiC), taken from a donor substrate of c-SiC, in direct contact with a support substrate of polycrystalline SiC (p- SiC), and allowing vertical electrical conduction.
• the support substrate which must have a sufficient thickness to be compatible with the formation of the components, is finally thinned to obtain the set of electronic components ready to be integrated.
• Document US8436363 is also known, which describes a process for manufacturing a composite structure comprising a thin layer of c-SiC placed on a metal support substrate whose coefficient of thermal expansion is matched with that of the thin layer. This manufacturing process includes the following steps:
• the composite structure comprising the metal support substrate and the thin layer in c-SiC, and on the other hand, the rest of the donor substrate in c-SiC.
• the present invention relates to an alternative solution to those of the state of the art, and aims to remedy all or part of the aforementioned drawbacks. It relates in particular to a method for manufacturing a semiconductor structure for electronic components, advantageously vertical, produced on and/or in an active layer of high quality monocrystalline silicon carbide, which is placed on a carbide support layer. of polycrystalline silicon. The invention also relates to a composite structure obtained at an intermediate step of said manufacturing process.
• the invention relates to a method for manufacturing a semiconductor structure, comprising: a) a step of providing a temporary graphite substrate having a grain size of between 4 microns and 35 microns, a porosity of between 6 and 17%, and a coefficient of thermal expansion between 4.10-6/°C and 5.10-6/°C; b) a step of depositing, directly on a front face of the temporary substrate, a polycrystalline silicon carbide support layer having a thickness of between 10 microns and 200 microns, c) a step of transferring a useful layer in monocrystalline silicon carbide on the support layer, directly or via an intermediate layer, to form a composite structure, said transfer implementing bonding by molecular adhesion, d) a step of forming an active layer on the useful layer, e) a step of removing the temporary substrate to form the semiconductor structure, said structure including the active layer, the useful layer and the support layer.
• step b) • the deposition of step b) is also carried out on a rear face of the temporary substrate to form a second support layer, and/or on a peripheral edge of said substrate;
• step c) transfer includes: o the introduction of light species into a monocrystalline silicon carbide donor substrate, to form a buried fragile plane defining with a front face of the donor substrate, the useful layer, o the assembly of the front face of the donor substrate on the support layer, directly or via an intermediate layer, by bonding by molecular adhesion, o separation along the buried fragile plane to transfer the useful layer onto the support layer;
• the intermediate layer is formed of tungsten, silicon, silicon carbide or other conductive or semi-conductive materials
• step d) comprises epitaxial growth of at least one additional layer of doped monocrystalline silicon carbide, on the useful layer, said additional layer forming all or part of the active layer;
• the manufacturing process comprises a step d') of producing all or part of electronic components on and/or in the active layer, step d') being inserted between step d) and step e) ;
• step e) comprises mechanical dismantling by propagation of a crack in the temporary substrate following the application of a mechanical stress, the crack extending substantially parallel to the plane of the interface between the temporary substrate and the backing layer;
• step e) comprises chemical dismantling between the support layer and the temporary substrate by lateral chemical etching
• step e) comprises chemical etching of all or part of the temporary substrate; • step e) comprises disassembly by thermal damage of the graphite of the temporary substrate;
• step c) comprises the transfer of a second useful layer of monocrystalline silicon carbide onto the second support layer, directly or via a second intermediate layer, said transfer implementing bonding by molecular adhesion;
• step d) comprises the formation of a second active layer on the second useful layer
• step e) makes it possible to form a second semiconductor structure, said structure including the second active layer, the second useful layer and the second support layer;
• the temporary substrate, provided in step a) has the shape of a circular wafer and a diameter 5% to 10% larger than a targeted diameter for the semiconductor structure;
• the temporary substrate, provided in step a) has the shape of a circular wafer and a diameter slightly smaller than a target diameter for the semiconductor structure, so that the deposition of step b), also operated on a peripheral edge of the temporary substrate, makes it possible to reach said target diameter.
• the invention also relates to a composite structure comprising:
• a polycrystalline silicon carbide support layer having a thickness of between 10 microns and 200 microns, at least arranged on and in contact with a front face of the temporary substrate, a useful layer of monocrystalline silicon carbide, placed on the support layer.
• the useful layer has a thickness of between 100 nm and 1500 nm;
• the temporary substrate has a thickness of between 100 microns and 2000 microns;
• the temporary substrate has a thermal conductivity of between 70 Wm _1 .K _1 and 130 Wm _1 .K _1 ;
• the temporary substrate and the support layer have a combined thickness of between 110 microns and 500 microns, typically 350 microns +/-25 microns.
• Figure 1 shows a semiconductor structure developed according to a manufacturing method according to the invention
• FIGS. 2a, 2b, 2c, 2d, 2d′ and 2e show steps of a manufacturing method according to the invention
• FIG. 3b Figures 3a and 3b show steps of a particular embodiment of the manufacturing method according to the invention.
• FIGS. 4a to 4c present a step c) of transfer of the manufacturing process according to the invention.
• the figures are schematic representations which, for the purpose of readability, are not to scale.
• the thicknesses of the layers along the z axis are not to scale with respect to the lateral dimensions along the x and y axes; and the relative thicknesses of the layers between them are not necessarily observed in the figures.
• the present invention relates to a method of manufacturing a semiconductor structure 100 (FIG. 1).
• semiconductor structure 100 is meant at least a stack of layers 4,3,2 intended to accommodate a plurality of microelectronic components; also means the stack of layers 4,3,2 with said electronic components 40, resulting from a collective manufacture on and/or in the active layer 4 maintained in the form of a wafer by a support layer 2, and ready to undergo the singulation stages prior to packaging.
• the manufacturing method advantageously applies to vertical microelectronic components, which require vertical electrical conduction through support layer 2, which forms the mechanical support for said components 40.
• the manufacturing process firstly comprises a step a) of supplying a temporary graphite substrate 1 having a front face 1a, a rear face 1b and a peripheral edge 1c (FIG. 2a).
• the graphite substrate 1 could be produced, for example, by deposition from a plasma, ion sputtering, cathodic arc deposition, evaporation of the graphite by laser, carbonization of a resin, etc.
• the graphite of the temporary substrate 1 has an average grain size of between 4 microns and 35 microns, a porosity of between 6 and 17%, and a thermal expansion coefficient of between 4.10 6 /°C and 5.10 6 /°C (between room temperature and 1000°C). These characteristics are chosen in particular to provide an excellent seed for the deposition of a layer of polycrystalline silicon carbide (p-SiC), called support layer 2 below, and which will be described with reference to step b) of the process.
• p-SiC polycrystalline silicon carbide
• the mean size of the grains corresponds to the arithmetic mean of the sizes of the grains with a dimension greater than or equal to 100nm. These grain sizes can be measured for example by scanning microscopy (SEM) or by electron backscattered diffraction (EBSD).
• the range of mean grain sizes is defined so that it is of the same order of magnitude as the mean grain size expected for the support layer 2, in the plane of the faces 1a, 1b.
• the thermal conductivity of the support layer 2 is thus ensured, because the grains of said layer will not be too small; moreover, even if the size of the grains is caused to increase during the deposition of the support layer 2, one remains within a range of controlled sizes, due to the defined range of average sizes of graphite grains, which limits the roughness at the level of the free surface of the support layer 2 deposited.
• the porosity range is also restricted so as to control the surface roughness of the support layer 2 after its deposition (step b) later).
• the coefficient of thermal expansion is defined so as to be matched with the coefficient of thermal expansion of silicon carbide, to limit the mechanical stresses in the structure during treatments (described later in the process) involving high temperatures.
• the temporary substrate 1 is compatible with temperatures which can go up to 1400° C. when the atmosphere is controlled, that is to say without oxygen; because if exposed to air, graphite begins to burn in a low temperature range, typically 400°C - 600°C. Protected by a protective layer completely encapsulating it, the temporary graphite substrate 1 is compatible with very high temperatures, even above 1400° C.
• the manufacturing method then comprises a step b) of depositing, directly on the front face 1a of the temporary substrate 1, a support layer 2 of polycrystalline silicon carbide (p-SiC) (FIG. 2b).
• the deposition can be carried out by any known technique, in particular by chemical vapor deposition (CVD), at a temperature of the order of 1100° C. to 1400° C. Mention may be made, for example, of a thermal CVD technique such as deposition at atmospheric pressure (APCVD for "atmospheric pressure CVD) or at low pressure (LPCVD for "low pressure CVD”), the precursors possibly being chosen from methylsilane, dimethyldichlorosilane or alternatively dichlorosilane+i-butane.
• CVD chemical vapor deposition
• a plasma-assisted CVD technique (PECVD for "plasma enhanced CVD") can also be used, with for example silicon tetrachloride and methane as precursors; preferentially, the frequency of the source used to generate the electric discharge creating the plasma is of the order of 3.3 MHz, and more generally comprised between 10 kHz and 100 GHz.
• PECVD plasma-assisted CVD
• conventional cleaning sequences may be applied to the temporary substrate 1 to remove all or part of the particulate, metallic or organic contaminants potentially present on its free faces 1a, 1b.
• the p-SiC support layer 2 has a thickness of between 10 microns and 200 microns. This thickness is chosen according to the thickness specifications expected for the semiconductor structure 100.
• the temporary substrate 1 and the support substrate 2 have a total cumulative thickness of between 110 microns and 500 microns, typically 350 microns +/- 25 microns. Mention may be made of the particular example of a temporary substrate 1 of 250 microns and a support layer 2 of 100 microns, or of a temporary substrate 1 of 300 microns and a support layer 2 of 50 microns.
• Support layer 2 will have, in semiconductor structure 100, the role of mechanical substrate and will potentially have to provide vertical electrical conduction. To guarantee this last property of electrical conduction (low resistivity), the support layer 2 is advantageously n- or p-type doped according to need.
• step b) is also carried out on the rear face lb of the temporary substrate 1 to form a second support layer 2', and/or on the peripheral edge le of said substrate 1.
• the role of the second support layer 2′ (and of the p-SiC deposited on the peripheral edge le) can essentially be to protect the temporary graphite substrate 1 during the heat treatments at very high temperatures which will follow in the process ; the thickness of the second support layer 2′ and of the p-SiC deposited on the peripheral edge 1e (also called protective layer hereinafter) will then be limited, of the order of a micron or a few microns.
• the second support layer 2' can alternatively be deposited on the rear face lb of the temporary substrate 1 in order to carry out the following steps of the method at the level of the two faces la, lb of the said substrate 1 (FIG. 3a).
• the second support layer 2' then has a thickness of the same order of magnitude as the first support layer 2 placed on the side of the front face la of the temporary substrate 1.
• a surface treatment is carried out, to improve the surface roughness of the support layer 2 and/or the quality of the edges of the structure, with a view to the next stage of transfer of the useful layer 3.
• the temporary substrate 1, provided in step a), which typically has the shape of a circular wafer, has a diameter 5% to 10% larger than the target diameter for the final semiconductor structure 100. This can make it possible to limit the problems of edges during the deposition of step b) and to maximize the surface occupied by the future components 40 on the semiconductor structure 100.
• the temporary substrate 1, provided in step a) has a diameter slightly less than the target diameter for the final semiconductor structure 100 (typically less than 5% less), so that the deposit of step b), operated in this case on the peripheral edge of the temporary substrate 1, makes it possible to reach said targeted diameter.
• the manufacturing method according to the invention then comprises a step c) of transferring a useful layer 3 of monocrystalline silicon carbide (c-SiC) directly onto the support layer 2 or via an intermediate layer, to form a composite structure 10 ( Figure 2c).
• the transfer implements bonding by molecular adhesion, and consequently a bonding interface 5.
• the intermediate layer can be formed on the side of the useful layer 3 and/or on the side of the support layer 2, to promote said bonding.
• transfer step c) successively comprises:
• the light species are preferably hydrogen, helium or a co-implantation of these two species, and are implanted at a determined depth in the donor substrate 30, consistent with the thickness of the targeted useful layer 3 (figure 4a). These light species will form, around the determined depth, microcavities distributed in a thin layer parallel to the free surface 30a of the donor substrate 30, ie parallel to the plane (x,y) in the figures. This thin layer is called the buried fragile plane 31, for simplicity.
• the implantation energy of the light species is chosen so as to reach the determined depth.
• hydrogen ions will be implanted at an energy of between 10 keV and 250 keV, and at a dose of between 5 E 16/cm2 and 1 E 17/cm2, to delimit a useful layer 3 having a thickness of the order from 100 to 1500 nm.
• an additional layer may be deposited on the front face 30a of the donor substrate 30, prior to the ion implantation step.
• This additional layer can be composed of a material such as silicon oxide or silicon nitride for example. It can be kept for the next step (and form all or part of the aforementioned intermediate layer), or it can be removed.
• bonding by molecular adhesion does not require an adhesive material, bonds being established on the atomic scale between the assembled surfaces.
• the assembly step may include, prior to bringing the faces to be assembled into contact, conventional sequences of cleaning, surface activation or other surface preparations, likely to promote the quality of the bonding interface 5 ( low defectivity, high adhesion energy).
• the front face 30a of the donor substrate 30 and/or the free face of the support layer 2 may (have) optionally comprise an intermediate layer, for example metallic (tungsten, etc.) or doped semiconductor (silicon, etc. ) to promote vertical electrical conduction, or insulating (silicon oxide, silicon nitride, etc.) for applications that do not require vertical electrical conduction.
• the intermediate layer is likely to promote bonding by molecular adhesion, in particular by erasing residual roughness or surface defects present on the faces to be assembled. It may undergo planarization or smoothing treatments to achieve a roughness of less than 1 nm RMS, or even less than 0.5 nm RMS, favorable to bonding.
• the separation along the buried fragile plane 31 usually takes place by applying a heat treatment at a temperature between 800° C. and 1200° C. (FIG. 4c).
• a heat treatment at a temperature between 800° C. and 1200° C. (FIG. 4c).
• Such a heat treatment induces the development of cavities and microcracks in the buried fragile plane 31, and their pressurization by the light species present in gaseous form, until the propagation of a fracture along said fragile plane 31.
• a mechanical stress can be applied to the bonded assembly and in particular at the level of the buried fragile plane 31, so as to mechanically propagate or help propagate the fracture leading to separation.
• the composite structure 10 comprising the temporary substrate 1 in graphite, the support layer 2 in p-SiC and the useful layer 3 transferred in c-SiC, and on the other hand , the remainder 30' of the donor substrate.
• the useful layer 3 typically has a thickness of between 100 nm and 1500 nm.
• the level and the type of doping of the useful layer 3 is defined by the choice of the properties of the donor substrate 30 or can be adjusted later via known techniques for doping semiconductor layers.
• the free surface of the useful layer 3 is usually rough after separation: for example, it has a roughness of between 5 nm and 100 nm RMS (AFM, scan 20 microns ⁇ 20 microns). Cleaning and/or smoothing steps can be applied to restore a good surface finish (typically, a roughness below a few Angstroms RMS on a 20 micron x 20 micron AFM scan).
• the free surface of the useful layer 3 can remain rough, as separated, when the next step of the process tolerates this roughness.
• the separation heat treatment is carried out in a controlled atmosphere devoid of oxygen.
• a protective layer is deposited before this heat treatment, to relax the atmospheric conditions of said treatment.
• the protective layer can be formed from p-SiC as indicated with reference to the particular embodiment involving the second support layer 2', or from amorphous SiC.
• step c) can also comprise the transfer of a second useful layer 3' in c-SiC onto the second support layer 2', directly or via a second intermediate layer, involving a second bonding interface 5' (FIG. 3b).
• the manufacturing method according to the invention then comprises a step d) of forming an active layer 4 on the useful layer 3 (FIG. 2d).
• the active layer 4 is produced by epitaxial growth of at least one additional layer of doped monocrystalline silicon carbide, on the useful layer 3.
• This epitaxial growth is carried out in the conventional temperature range, namely between 1500° C. and 1900°C and forms a layer with a thickness of the order of 1 micron to a few tens of microns, depending on the electronic components targeted.
• this protective layer may for example consist of a layer of polycrystalline (second support layer 2') or amorphous silicon carbide.
• the manufacturing method according to the invention can also comprise a step d') of producing all or part of the electronic components 40 on and/or in the active layer 4 (FIG. 2d').
• the electronic components 40 can for example consist of transistors or other high voltage and/or high frequency components.
• step d) can also comprise the formation of a second active layer on the second useful layer 3'; and step d') can comprise the production of all or part of second electronic components on and/or in said second active layer.
• the manufacturing method according to the invention comprises a step e) of removing the temporary substrate 1 to form the semiconductor structure 100, said structure including the active layer 4, the useful layer 3 and the support layer 2 (FIG. 2e (i)), and potentially the electronic components 40 (FIG. 2e (ii)), if a step of has been carried out.
• variants can be implemented for this step: some variants (first and second variants described below) are based on the dismantling of said substrate 1 and therefore can potentially include its recycling for a new use; other variants (third and fourth variants) involve the partial or total removal of the temporary substrate 1.
• step e) comprises mechanical dismantling by propagation of a crack in the temporary substrate 1 following the application of a mechanical stress, the crack extending substantially parallel to the plane of the interface between the temporary substrate 1 and the support layer 2.2'.
• inserting a bevel tool opposite screw or close to said interface makes it possible to initiate and propagate an opening at this interface or in the graphite of the temporary substrate 1, until the complete separation between the semiconductor structure 100 and the temporary substrate 1.
• the protective layer present on the edges of the temporary substrate 1 is removed, to promote the initiation of the crack in the graphite.
• step e) comprises a chemical dismantling between the support layer 2,2' and the temporary substrate 1 by lateral chemical etching.
• the protective layer located on the edges 1c of the temporary substrate 1 in the composite structure 10 must be removed chemically or mechanically, to allow access to the graphite.
• Lateral chemical etching can in particular implement a solution based on nitric acid and/or sulfuric acid, for example a solution of concentrated sulfuric acid and potassium dichromate or a solution of sulfuric acid, nitrate and potassium chlorate.
• Chemical etching using an alkaline solution (of the potassium hydroxide (KOH) or sodium hydroxide (NaOH) type) can also be applied.
• care will be taken to protect the free face and the edges of the active layer 4 and of the electronic components 40 if they are present, and/or to limit the time of contact with the etching solution, to avoid damage them during this chemical dismantling.
• step e) comprises a chemical etching of all or part of the temporary substrate 1.
• the protective layer on the edges le and on the rear face lb (second support layer 2') of the temporary 1 of the composite structure 10 will have to be removed to give access to the graphite.
• Mechanical removal can typically be carried out, for example by lapping the edges and the rear face ("edge grinding” or “grinding” according to the English terminology), or chemical, depending on the nature of the protective layer.
• the chemical etching of the temporary substrate 1 could for example implement one of the solutions stated above for the second variant, taking care to protect the active layer 4 and potentially the components 40.
• step e) comprises disassembly by thermal damage of the graphite making up the temporary substrate 1.
• it is required to remove the protective layer present at least on the edges of the temporary substrate 1.
• it is also possible to remove the protective layer from this face.
• Dismantling by thermal damage can take place at a temperature between 600° C. and 1000° C., in the presence of oxygen: the graphite of the temporary substrate 1 is then burned and crumbles to leave only the semi-integrated structure intact. driver 100.
• this dismantling variant can only be applied if said components 40 are compatible with the temperature applied.
• the removal of the temporary substrate 1 can leave residues on the rear face 2b of the support layer 2. These residues are then eliminated by lapping or mechanical grinding, by mechanical-chemical polishing, by chemical etching and/or thermal damage. Mechano-chemical polishing or chemical etching techniques can also be implemented to reduce the roughness of the rear face 2b of the support layer 2, if necessary.
• step e) of removing the substrate temporary 1 also makes it possible to form a second semiconductor structure, said structure including the second active layer (and potentially electronic components), the second useful layer 3' and the second support layer 2'.
• the semiconductor structure 100 must be manipulated during and after the removal of the temporary substrate 1, and its total thickness is insufficient for its mechanical maintenance during this manipulation, it is possible to use a removable handle: the latter is arranged on the active layer 4 and temporarily secured thereto, to perform the manipulation up to the singulation step, for example.
• the semiconductor structure 100 obtained at the end of the manufacturing method according to the invention comprises an active layer 4 finalized with potentially electronic components 40, and placed on a support layer 2 having the thickness targeted for the application. No mechanical thinning involving a significant loss of material is required.
• the support layer 2 is made of p-SiC of good quality (because deposited at relatively high temperatures) but at low cost compared to a solid monocrystalline or polycrystalline SiC substrate which should have been significantly thinned before singling out the components.
• the temporary graphite substrate 1 is advantageously recovered to be recycled. If not reused, such as graphite constitutes a low-cost material, the manufacturing method according to the invention remains economically advantageous compared to a solution with a solid SiC substrate.
• the choice of the physical characteristics of the temporary graphite substrate 1 ensures the formation of a support layer 2 making it possible to obtain a composite structure 10 that is robust and of high quality, and allowing the obtaining a reliable and high-performance semiconductor structure 100.
• the performance of the components 40 comes in particular from the fact that the composite structure 10 allows treatment at very high temperatures for the formation of the active layer 4.
• the invention also relates to a composite structure 10, described above with reference to the manufacturing process, and corresponding to an intermediate structure obtained during said process (FIGS. 2c, 2d, 3b).
• the composite structure 10 comprises:
• a temporary graphite substrate 1 having a grain size of between 4 microns and 35 microns, a porosity of between 6 and 17%, and a thermal expansion coefficient of between 4.10 6 /°C and 5.10 6 /°C,
• a useful layer 3 of monocrystalline silicon carbide placed directly on the support layer 2 or via an intermediate layer.
• the useful layer 3 has a thickness of between 100 nm and 1500 nm.
• the temporary substrate 1 has a thickness between 100 microns and 2000 microns.
• support layer 2 advantageously has good electrical conductivity, i.e. between 0.015 and 0.03 ohm.cm, high thermal conductivity, i.e. greater than or equal to 200 Wm _1 .K _1 and a coefficient of thermal expansion similar to that of the useful layer 3, ie typically between 3.8 ⁇ 10 6 /°C and 4.2 ⁇ 10 6 /°C at room temperature.
• the temporary substrate 1 can advantageously have a thermal conductivity of between 70W.m _1 .K _1 and 130W.m _1 .K 1 , so as to ensure a uniform temperature on the temporary substrate 1 during the very high heat treatment steps. manufacturing process temperatures. This notably improves the uniformity of the layers deposited and the reproducibility of the physical properties of the layers and components produced.
• the composite structure 10 can be “double-sided”, that is to say comprise:
• Such a composite structure 10 allows the formation of two active layers 4, respectively on the first 3 and the second 3 'useful layer, and, at the end of the manufacturing method according to the invention, the obtaining of two semi- conductors 100, from a single temporary substrate 1.
• the invention is not limited to the embodiments and the examples described, and variant embodiments can be added thereto without departing from the scope of the invention as defined by the claims.

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• 2021
  • 2021-03-09 FR FR2102306A patent/FR3120736A1/fr active Pending
• 2022
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