EP4049317A1 - Transistor à effet de champ vertical et son procédé de formation - Google Patents

Transistor à effet de champ vertical et son procédé de formation

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Publication number
EP4049317A1
EP4049317A1 EP20776124.8A EP20776124A EP4049317A1 EP 4049317 A1 EP4049317 A1 EP 4049317A1 EP 20776124 A EP20776124 A EP 20776124A EP 4049317 A1 EP4049317 A1 EP 4049317A1
Authority
EP
European Patent Office
Prior art keywords
semiconductor fin
shielding structure
drift region
effect transistor
field effect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP20776124.8A
Other languages
German (de)
English (en)
Inventor
Dick Scholten
Jens Baringhaus
Daniel Krebs
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP4049317A1 publication Critical patent/EP4049317A1/fr
Pending legal-status Critical Current

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    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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Definitions

  • the invention relates to a vertical field effect transistor and a method of forming the same.
  • the actively switchable component is provided by an inversion channel, for example by the p-region in an npn junction, in which an electron path is formed by applying a gate voltage.
  • an inversion channel for example by the p-region in an npn junction, in which an electron path is formed by applying a gate voltage.
  • semiconductors with a wide band gap for example silicon carbide (SiC) or gallium nitride (GaN)
  • the structure of a conventional power FinFET 100 is illustrated in FIG.
  • the doping profile 120 and the electric field 140 at 600 V drain voltage of this structure are illustrated in FIG. 1 with the lateral and vertical dimensions 150 and 160, respectively, in ⁇ m.
  • the conventional power FinFET 100 has a drift region 110 with an n-doping 114, a drain electrode 112, a source electrode 102, a gate electrode 108, a semiconductor fin 104 and an insulation 106.
  • the semiconductor fin 104 is connected to the source electrode 102 by means of an n + doping 116.
  • the switchable component consists of the narrow semiconductor fin 104, which is switchable due to its geometry and a suitable choice of the gate metallization 108.
  • the channel resistance of the power FinFET 100 is significantly lower than that of a conventional MOSFET or MISFET based on SiC or GaN. This results in a lower switch-on resistance of the entire component.
  • the conventional power FinFET 100 does not have any shielding of the channel region against electrical fields such as occur in particular in blocking operation. Accordingly, the achievable breakdown voltage is limited and in particular strongly dependent on process fluctuations (e.g. etching depth).
  • FIG. 1 shows the simulation of the electric field 140 in reverse operation with an applied drain voltage of 600 V for a conventional FinFET 100.
  • the highest field stress 142 can be found in the insulation 106 below the gate electrode 108.
  • the vertical field effect transistor has: a drift region having a first conductivity type; a semiconductor fin on or above the drift region, a source / drain electrode being formed laterally next to at least one side wall of the semiconductor fin on or above the drift region; and a shielding structure which is arranged laterally next to the at least one side wall of the semiconductor fin in the drift region, the shielding structure having a second conductivity type that is different from the first conductivity type.
  • the semiconductor fin is connected to the source / drain electrode in an electrically conductive manner.
  • the shielding structure within the drift area changes the field distribution.
  • the electric field is increased at the p-n junctions of the vertical field effect transistor and thus decreases in the insulation below the gate metal.
  • the shielding structure By means of the shielding structure, the electric field can be reduced in the insulation, in particular during blocking operation, and shifted into the drift area. This enables the maximum field peaks reached to be reduced. As a result, a field effect transistor with a higher dielectric strength and reliability can be provided.
  • the object is achieved by a vertical field effect transistor.
  • the vertical field effect transistor has: a drift region having a first conductivity type; a first semiconductor fin on or above the drift region and a second semiconductor fin which is arranged laterally next to the first semiconductor fin on or above the drift region, a source / drain electrode laterally next to at least one side wall of the first semiconductor fin is formed on or above the drift region; and a shield structure formed laterally adjacent to the at least one side wall of the first semiconductor fin, the shield structure being arranged in the second semiconductor fin, and wherein the shield structure has a second conductivity type that is different from the first conductivity type, and wherein the semiconductor fin is electrically conductively connected to the source / drain electrode.
  • the object is achieved by a method for forming a vertical field effect transistor.
  • the method includes: forming a drift region with a first conductivity type; Forming a semiconductor fin on or above the drift region, a source / drain electrode being formed laterally next to at least one side wall of the semiconductor fin on or above the drift region; and forming a shield structure laterally adjacent to the at least one Sidewall of the semiconductor fin is arranged in the drift region, wherein the shielding structure has a second conductivity type that differs from the first conductivity type, and wherein the semiconductor fin is electrically conductively connected to the source / drain electrode.
  • FIG. 1 shows sectional views of a transistor structure of the related art
  • FIGS. 2A and 2B are schematic sectional illustrations of a vertical field effect transistor in accordance with various embodiments
  • FIGS. 3A to 3K show schematic sectional illustrations of a vertical field effect transistor in accordance with various embodiments.
  • FIG. 4 shows a flow diagram of a method for forming a vertical field effect transistor in accordance with various embodiments.
  • a vertical field effect transistor 200 has a drift region 212 on a semiconductor substrate 216; a semiconductor fin 302 (the longitudinal direction of which extends perpendicular to the plane of the drawing) on or above the drift region 212, a shielding structure 214, a first source / drain electrode (eg a source electrode 202), a second source / drain electrode (eg a drain electrode 218).
  • a first source / drain electrode eg a source electrode 202
  • a second source / drain electrode eg a drain electrode 218
  • the vertical field effect transistor 200 furthermore has a gate electrode 210 next to at least one side wall of the semiconductor fin 302, the gate electrode 210 being electrically insulated from the source electrode 202 by means of an insulation 206.
  • a gate dielectric 208 is arranged between the gate electrode 210 and the semiconductor fin 302.
  • a highly doped connection region 204 can connect the semiconductor fin 302 to the source electrode 202 in an electrically conductive manner.
  • the source electrode 202 can additionally be formed laterally next to at least one side wall of the semiconductor fin 302 on or above the drift region 212.
  • the shielding structure 214 is arranged laterally next to the at least one side wall of the semiconductor fin 302 in the drift region 212.
  • the shielding structure 214 has a second conductivity type that is different from the first conductivity type.
  • the semiconductor substrate 216 can be, for example, a GaN substrate 216 or a SiC substrate 216.
  • the weakly n-conducting semiconductor drift region 212 (also referred to as drift zone 212) can be formed (eg applied) on the semiconductor substrate 216, for example a GaN or SiC drift region 212.
  • an n-conducting semiconductor can be formed Region in the form of the semiconductor fin 302, for example in the form of a GaN or SiC fin 302.
  • An n + -conductive connection region 204 can be formed on the semiconductor fin 302 or in an upper portion of the fin 302, by means of which the source electrode 202 is contacted.
  • the source electrode 202 can contact both the shielding structure 214 and the semiconductor fin 302.
  • the drain electrode 218 can be located on the rear side of the substrate 216.
  • the shielding structure 214 for example in the form of highly doped p-GaN or p-SiC regions in the drift region 212, the bottom of the Shield semiconductor fin 302 (the area between semiconductor fin 302 and drift area 212).
  • a space charge zone can be formed between the regions of the shielding structure 214 and the drift region 212 during operation. Thereby, the area in which a current can flow can be reduced, whereby the resistance can be increased.
  • the shielding structure 214 the total resistance of the field effect transistor 200 is increased compared to the variant without a shielding structure (FIG. 1), as is illustrated in FIG. 2B.
  • FIG. 1 the variant without a shielding structure
  • FIG. 2B illustrates the doping profile 242 and the electric field 244 at 600 V drain voltage of this structure 200 with the lateral and vertical dimensions 250 and 260 in ⁇ m, respectively.
  • Figure 244 on the right in FIG. 2B shows the simulation of the electric field 140 in reverse operation with an applied drain voltage of 600 V.
  • the field loading below the gate electrode 210 is reduced by means of the shielding structure 214.
  • the potential applied to the drain electrode 218 in the blocking case leads to an electric field which has its maximum directly below the shielding structure 214 and not, as in the case without the shielding structure 214 (see FIG. 1), near the bottom of the semiconductor -Fin 302.
  • the field effect transistor 200 can be normally off, since the electron gas below the semiconductor fin 302 can be depleted in the drift region.
  • a positive voltage to the gate electrode 210 electrons can be accumulated in the region of the semiconductor fin 302 which is adjacent to the gate electrode 210. The electrons can flow from the source electrode 202 through the semiconductor fin 302 into the bottom of the semiconductor fin 302 and from there into the drift region 212 and further through the drift region 212 and the substrate 216 into the drain electrode 218.
  • FIGS. 3A-3K show further embodiments of the vertical field effect transistor 200 illustrated in FIG. 2, the further layers or structures above the drift region 212 not being illustrated.
  • the lateral and vertical extent of the shielding structure 212 and its doping level depend on the application-specific degree of shielding of the space charge zone below the bottom of the semiconductor fin 302.
  • the gate electrode 210 is not required to be formed completely between two semiconductor fins 302, but for example only on each side wall of a semiconductor fin 302. This enables a reduced capacitance between the gate electrode 210 and the drain electrode 218.
  • the p-doped shielding structure can be formed after every second, third, etc. semiconductor fin 302.
  • FIG. 3A illustrates an embodiment in which a shielding structure 214 is formed after every second semiconductor fin 302 or every two semiconductor fins 302.
  • FIG. 3B shows an embodiment with a shielding structure 214 between four semiconductor fins 302 in each case.
  • a shielding structure 214 is formed on each side of the semiconductor fin 302.
  • the shielding structure 214 can in this case be formed between two semiconductor fins 302 (FIG. 3D) and / or a multiplicity of semiconductor fins between two adjacent shielding structures 214 (FIG. 3B).
  • the shielding structure 214 can be completely surrounded by the drift region 212 (see, for example, FIG. 3C). Alternatively (see, for example, FIG. 3B) or additionally (see, for example, FIG. 3E), the shielding structure 214 can have at least one region that is free from the drift region 212. In other words: In various embodiments, buried shielding structures 214 and / or shielding structures 214 arranged on the surface of the drift region 212 may be provided. The position of the buried shielding structures 214 is not limited to the trench between the semiconductor fins 302. Alternatively or additionally, the buried shielding structures 214 can be arranged vertically below the bottom of the semiconductor fin 302 (see, for example, FIG. 3F).
  • additional shielding structures can be formed in order to further increase the shielding effect.
  • the vertical distance of the shielding structure from the bottom of the semiconductor fin 302 and / or the lateral extent of the shielding structure can vary in different embodiments (see, for example, FIGS. 3A-3F).
  • the shielding structure 214 has at least a first shielding structure 214 and a second shielding structure 214.
  • the first shielding structure 214 can extend vertically further into the drift region 212 with respect to the semiconductor fin 302 or be spaced further apart vertically from the semiconductor fin 302 than the second shielding structure 214. This enables application-specific shielding of the bottom of the semiconductor fin 302 from electric fields.
  • shielding structures 214 can be formed in adjacent semiconductor fins 302, which do not serve as vertical field effect transistors (see, for example, FIGS. 3G-3I).
  • the vertical field effect transistor 200 has a drift region 212 with a first conductivity type; a first semiconductor fin 302 on or above the Drift region 212 and a second semiconductor fin 302, which is arranged laterally next to the first semiconductor fin 302 on or above the drift region 212.
  • a source / drain electrode 202 is formed on or above the drift region 212 laterally next to at least one side wall of the first semiconductor fin 302.
  • a shielding structure 214 is formed laterally next to the at least one side wall of the first semiconductor fin 302, the shielding structure 214 being arranged in the second semiconductor fin 302.
  • the shielding structure 214 has a second conductivity type that is different from the first conductivity type.
  • the semiconductor fin 302 is connected to the source / drain electrode 202 in an electrically conductive manner.
  • An additional semiconductor fin 302 can clearly be provided, which is offset in the plane with respect to the semiconductor fin 302, so that the shielding structure 214 is arranged in the additional semiconductor fin 302.
  • FIG. 3G illustrates an embodiment of a vertical field effect transistor in which a shielding structure 214, for example in the form of a p-doped region, is formed in every third semiconductor fin 302.
  • a shielding structure 214 can be formed in every second, fourth, etc., semiconductor fin 302.
  • the distance A between a semiconductor fin 302 with a shielding structure 214 and the distance B between two semiconductor fins 302 without a shielding structure 214 can be selected to be application-specific, for example identical or different.
  • distance A can be selected to be greater than distance B or distance B to be greater than distance A.
  • the shielding structure 214 can optionally also be formed in the entire semiconductor fin 302. Alternatively and / or additionally, the shielding structure 214 can extend beyond the bottom of the semiconductor fin 302 into the drift region 212 (see, for example, FIG. 3H - right shielding structure 214). In various embodiments, effective shielding of the bottom of the semiconductor fin 302 is implemented in that the shielding structure 214 extends in the direction of or below the bottom of the semiconductor fin 302.
  • the shielding structure can be formed over the entire width (in the plane of the drawing) of the semiconductor fin 302. In other words: the shielding structure 214 can occupy or fill the entire width of a semiconductor fin 302.
  • the shielding structure 214 can have a lateral extent that is smaller than the width of the semiconductor fin 302.
  • the shielding structure 214 can be set up in such a way that it laterally has the same extent as the source / drain electrode 202 or, alternatively, can be of this type be set up so that it has a laterally smaller extent than the extent of the source / drain electrode 202 (see, for example, FIG. 3H).
  • the variation of the lateral extent of the shielding structure 214 offers the possibility of optimizing the component with regard to the shielding (can become better with increasing lateral extent) or with regard to the transmission resistance (can decrease with decreasing lateral extent).
  • the trench structures (the area between two adjacent semiconductor fins 302), which in various embodiments contain the shielding structures 214, can have a greater lateral extent than the trenches between the individual semiconductor fins 302.
  • the shielding structures 214 can also be deep be embedded in the drift region 212, for example completely surrounded by the drift region 212 and at a distance from the bottom of the semiconductor fin 302.
  • the buried shielding structures 214 can be electrically connected to the source / drain electrode 202 at another point of the vertical field effect transistor.
  • the connections of the vertical field effect transistor are configured, for example, in a super cell structure (not illustrated).
  • the shielding structure 214 has a region which is arranged in the drift region 212 and extends laterally in the direction of the semiconductor fin 302. In various embodiments, the shielding structure 214 can adjoin the bottom of the semiconductor fin 302, for example touching it (not illustrated).
  • the shielding structure 214 can be connected to the semiconductor fin 302 and the drift region 212 in an electrically conductive manner.
  • the shielding structures 214 are electrically conductively connected to the source / drain electrode 202 (see, for example, FIG. 3B).
  • shielding structures can be provided which are not (directly) connected to the source / drain electrode 202 in an electrically conductive manner (see, for example, FIG. 3A).
  • the shielding structure 214 is at a floating electrical potential. In this case, the shielding effect of the shielding structure 214 is retained. However, the structure with the floating shield structure can no longer be used as a body diode for reverse operation.
  • all of the shielding structures 214 shown above can also be implemented in this floating form.
  • the semiconductor fins can have different widths.
  • a (second) semiconductor fin with an embedded shielding structure 214 can be made wider than a (first) semiconductor fin without a shielding structure.
  • the buried shielding structures 214 of the second conductivity type can be combined with additional regions 312 of the first conductivity type (see, for example, FIG. 3K). As a result, the depletion between the buried p-regions of the shielding structures and thus the spread of the current in the drift region 212 can be set. It is accordingly possible to control or adjust the current density in this area.
  • the second regions 312 can also be provided in all other embodiments.
  • the semiconductor fin can be designed in columnar form, for example spatially limited in all spatial directions.
  • the semiconductor fin can be a semiconductor pillar in various embodiments.
  • the semiconductor pillar can have a square, rectangular, round or hexagonal cross section of the pillar.
  • the semiconductor fin can be designed with non-rectangular side walls, for example conical or pyramid-shaped.
  • the shielding structures shown above can also be applied to these structural variants.
  • the buried shielding structures can be formed both parallel and perpendicularly as well as at any desired angle relatively laterally to the semiconductor fins.
  • FIG. 4 shows a flow chart of a method for forming a vertical field effect transistor in accordance with various embodiments.
  • the method 400 for forming a vertical field effect transistor 200 comprises: forming 410 a drift region with a first conductivity type; forming 420 a semiconductor fin 302 on or above the drift region, a source / drain electrode being formed laterally next to at least one side wall of the semiconductor fin 302 on or above the drift region 212; and forming 430 a shielding structure 214, which is arranged laterally next to the at least one side wall of the semiconductor fin 302 in the drift region 212, the shielding structure 214 having a second conductivity type that differs from the first conductivity type, and the shielding structure 214 having the semiconductor fin 302 and the drift region 212 are electrically conductively connected.
  • the shielding structures 214 can be formed, for example, by means of ion implantation, for example in the case of a SiC semiconductor fin or an SiC drift region with aluminum ion implantation or in the case of a GaN semiconductor fin or a GaN drift region with Mg ions.
  • an additional trench 310 can be provided, in the bottom of which the implantation takes place (see, for example, FIG. 3J).
  • the shielding structures can be formed by means of a so-called dead implantation.
  • the shielding structures are formed by implanting an ion species, for example argon ions, which do not cause any doping in the SiC or GaN drift region. These shielding structures are no longer electrically conductive. Correspondingly, their shielding effect is retained, but they can no longer act as a body diode for the
  • Reverse operation can be used.
  • a connection of such electrically non-conductive shielding structures to the source electrode is optional.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

L'invention concerne un transistor à effet de champ vertical (200) comprenant : une région de dérive (212) ayant un premier type de conductivité, une ailette semi-conductrice (302) qui est sur ou au-dessus de la région de dérive (212), une électrode de source/drain (202) qui se trouve sur ou au-dessus de l'ailette semi-conductrice (212) et une structure de blindage (214) qui est disposée latéralement adjacente à l'au moins une paroi latérale de l'ailette semi-conductrice (302) dans la région de dérive (212). La structure de blindage (214) a un second type de conductivité qui est différent du premier type de conductivité et l'ailette semi-conductrice (302) est connectée de manière électriquement conductrice à l'électrode de source/drain (202).
EP20776124.8A 2019-10-21 2020-09-21 Transistor à effet de champ vertical et son procédé de formation Pending EP4049317A1 (fr)

Applications Claiming Priority (2)

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DE102019216138.3A DE102019216138A1 (de) 2019-10-21 2019-10-21 Vertikaler feldeffekttransistor und verfahren zum ausbilden desselben
PCT/EP2020/076293 WO2021078451A1 (fr) 2019-10-21 2020-09-21 Transistor à effet de champ vertical et son procédé de formation

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EP4049317A1 true EP4049317A1 (fr) 2022-08-31

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US (1) US20220416028A1 (fr)
EP (1) EP4049317A1 (fr)
JP (1) JP7471403B2 (fr)
CN (1) CN114586173A (fr)
DE (1) DE102019216138A1 (fr)
WO (1) WO2021078451A1 (fr)

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DE102022203048A1 (de) 2022-03-29 2023-10-05 Robert Bosch Gesellschaft mit beschränkter Haftung Vertikales Leistungshalbleiterbauelement und Verfahren zum Herstellen eines vertikalen Leistungshalbleiterbauelements

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Publication number Priority date Publication date Assignee Title
US5856692A (en) * 1995-06-02 1999-01-05 Siliconix Incorporated Voltage-clamped power accumulation-mode MOSFET
JP3575331B2 (ja) * 1999-05-17 2004-10-13 日産自動車株式会社 電界効果トランジスタ
JP4564362B2 (ja) * 2004-01-23 2010-10-20 株式会社東芝 半導体装置
US8097919B2 (en) * 2008-08-11 2012-01-17 Cree, Inc. Mesa termination structures for power semiconductor devices including mesa step buffers
WO2013026035A1 (fr) * 2011-08-17 2013-02-21 Ramgoss, Inc. Transistor vertical à effet de champ sur substrat semi-conducteur à oxyde et son procédé de fabrication
JP5742657B2 (ja) * 2011-10-20 2015-07-01 住友電気工業株式会社 炭化珪素半導体装置およびその製造方法
JP6409681B2 (ja) * 2015-05-29 2018-10-24 株式会社デンソー 半導体装置およびその製造方法
JP6830627B2 (ja) * 2016-12-22 2021-02-17 国立研究開発法人産業技術総合研究所 半導体装置および半導体装置の製造方法
JP6855793B2 (ja) * 2016-12-28 2021-04-07 富士電機株式会社 半導体装置
JP6910944B2 (ja) * 2017-12-27 2021-07-28 ルネサスエレクトロニクス株式会社 半導体装置
US10861965B2 (en) * 2018-07-12 2020-12-08 Renesas Electronics America Inc. Power MOSFET with an integrated pseudo-Schottky diode in source contact trench

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JP2022553281A (ja) 2022-12-22
CN114586173A (zh) 2022-06-03
JP7471403B2 (ja) 2024-04-19
WO2021078451A1 (fr) 2021-04-29
DE102019216138A1 (de) 2021-04-22
US20220416028A1 (en) 2022-12-29

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