EP3994963A1 - Procédé de fabrication de cartes de circuits imprimés, et cartes de circuits imprimés fabriquées selon le procédé - Google Patents

Procédé de fabrication de cartes de circuits imprimés, et cartes de circuits imprimés fabriquées selon le procédé

Info

Publication number
EP3994963A1
EP3994963A1 EP20734156.1A EP20734156A EP3994963A1 EP 3994963 A1 EP3994963 A1 EP 3994963A1 EP 20734156 A EP20734156 A EP 20734156A EP 3994963 A1 EP3994963 A1 EP 3994963A1
Authority
EP
European Patent Office
Prior art keywords
metal layer
cover metal
substrate
substrate side
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP20734156.1A
Other languages
German (de)
English (en)
Inventor
Christian Schmid
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gebrueder Schmid GmbH and Co
Original Assignee
Gebrueder Schmid GmbH and Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gebrueder Schmid GmbH and Co filed Critical Gebrueder Schmid GmbH and Co
Publication of EP3994963A1 publication Critical patent/EP3994963A1/fr
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0041—Etching of the substrate by chemical or physical means by plasma etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/465—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer having channels for the next circuit layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4679—Aligning added circuit layers or via connections relative to previous circuit layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0376—Flush conductors, i.e. flush with the surface of the printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845—Stepped hole, via, edge, bump or conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0548—Masks
    • H05K2203/0554—Metal used as mask for etching vias, e.g. by laser ablation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0585—Second resist used as mask for selective stripping of first resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls

Definitions

  • the invention described below relates to a method for producing printed circuit boards and printed circuit boards produced according to the method.
  • PCB printed circuit board
  • Circuit boards always comprise a base substrate which is designed to be electrically non-conductive and which has a structure of conductor tracks (for short: conductor structure) for making electrical contact with the electronic components on at least one side of the substrate.
  • conductor tracks for short: conductor structure
  • the conductor tracks usually consist of a metal such as copper.
  • both sides of a carrier layer can be provided with a conductor structure, or a plurality of base substrates, each with one conductor track level, can be combined to form an MLB.
  • base substrates provided with a conductor structure on both sides can also form a basis for multilayer structures.
  • the conductor tracks of the various conductor track levels can be electrically connected to one another via through-contacts. For this purpose, for example, holes can be drilled into the base substrate and the borehole walls can be metallized.
  • the formation of the conductor structures on a base substrate usually takes place subtractively in a multi-stage photolithographic process using a photoresist, the solubility of which in a developer solution can be influenced by means of radiation, in particular by means of UV radiation.
  • a metal layer is formed on the base substrate and covered with a layer of the photoresist.
  • the layer made of the photoresist can for example be laminated onto the metal layer.
  • the layer of photoresist is then exposed to the radiation mentioned in an exposure step, partial areas of the layer being protected from exposure to radiation by means of an exposure mask will.
  • either the exposed or the unexposed partial areas of the layer made of the photoresist are soluble in the developer solution after the exposure step and can be removed in a subsequent step.
  • the development step partial areas of the metal layer on the base substrate are exposed, which can be removed wet-chemically in a further subsequent step, an etching step.
  • the residues of the metal layer that remain after the subsequent complete removal of the resist form the desired conductor structure. If necessary, this can - for example by galvanic deposition of a suitable metal - be reinforced in a deposition step.
  • the conductor tracks are located on the surface of a base substrate. This can be disadvantageous when manufacturing MLBs. If a surface of a base substrate provided with conductor tracks is pressed with another base substrate, there is often a need for control and correction as a result of deviations caused by the pressures and temperatures that occur during pressing. Conductor tracks on the surface of base substrates are particularly exposed to such loads. The smaller the distances and dimensions of the conductor tracks on the substrate, the greater the corresponding need for control and correction, for example with regard to existing impedance and signal speed requirements.
  • a general disadvantage of the classic subtractive processes is that the resolution of the conductor structures to be produced is limited. Conductor tracks with widths in the low double-digit or even single-digit pm range can hardly be produced in this way.
  • the present invention was based on the object of developing a procedure for the production of Lei terplatten with which the problems described can be avoided or at least verrin like. To solve this problem, the invention proposes the method described below, in particular in the particularly preferred embodiment with the features of claim 1.
  • the circuit board described below, in particular in the particularly preferred embodiment according to claim 14, is also covered by the invention. Further developments of the particularly preferred embodiments of the method are the subject of subclaims. The wording of all claims is hereby made part of the content of the description by reference.
  • the method according to the invention for producing a printed circuit board with a metallic Lei terstructure always comprises the immediately following steps a. to e .: a. Providing a base substrate in the form of a film or plate with a first and a second substrate side, which consists at least partially of an electrically non-conductive organic polymer material and in which the first substrate side is covered with a cover metal layer, b. Removal of the cover metal layer in regions, subdividing the first substrate side into at least one first sub-area in which the first substrate side is free of the cover metal layer, and into at least one second sub-area in which the first substrate side is covered with the cover metal layer, c.
  • the method according to the invention is suitable both for the production of single-layer printed circuit boards, which comprise only a base substrate with a conductor structure in one plane, and for the production of multi-layer printed circuit boards, which comprise conductor structures in at least two planes and usually also several base substrates.
  • the removal of the cover metal layer leads to step e. to form only part of the entire conductor structure of the circuit board.
  • the entire conductor structure of the circuit board is preferred in step e. educated.
  • the method additionally comprises the immediately following step f .: f. planarizing the first substrate side with the filled at least one recess.
  • the method comprises at least one of the immediately following features a. until about.
  • the base substrate has a thickness in the range from 10 ⁇ m to 3 mm, preferably in the range from 10 ⁇ m to 2 mm.
  • the organic polymer material is selected from the group comprising polyimide, polyamide, Teflon, polyester, polyphenylene sulfide, polyoxymethylene and polyether ketone.
  • the base substrate is particularly preferably a film made of a polymer material, in particular one of the polymer materials mentioned. This is particularly true if the printed circuit board to be manufactured is made of multiple layers. In the case of a single-layer printed circuit board, a comparatively thicker base substrate in the form of a plate is preferably chosen.
  • the base substrate can optionally comprise fillers, in particular dielectric fillers.
  • the base substrate can be a film made of one of the named polymer materials in which silicon dioxide particles are embedded.
  • dielectric fillers are metal or semi-metal oxides (in addition to silicon dioxide, in particular aluminum oxide, zirconium oxide or titanium oxide) and other ceramic fillers (in particular silicon carbide or boron nitride or boron carbide). If necessary, silicon can also be used.
  • the fillers are preferably in particulate form, in particular with an average particle size (d50) in the nano range ( ⁇ 1 ⁇ m).
  • the method according to the invention is particularly preferably characterized by at least one of the immediately following features a. to c. from: a.
  • the base substrate and / or the insulating layer comprise fillers, in particular dielectric fillers.
  • the base substrate and / or the insulating layer is a plastic film with the fillers.
  • the fillers have a mean particle size (d50) ⁇ 1 ⁇ m.
  • the base substrate for processing can be applied to a carrier or an auxiliary substrate, for example made of glass or aluminum.
  • the method comprises at least one of the immediately following features a. and b .: a. A layer made of copper or a copper alloy is selected as the cover metal layer. b. The cover metal layer has a thickness in the range from 10 nm to 10 ⁇ m, preferably in the range from 20 nm to 6 ⁇ m.
  • the cover layer should be closed and should not fall below the preferred minimum thickness mentioned so that the cover metal layer can fulfill its technical function as an etching barrier explained below.
  • the cover metal layer can fulfill its technical function as an etching barrier explained below.
  • titanium and nickel-chromium alloys can also be used as cover metals.
  • the cover metal layer it is basically possible to laminate or cover a thin metal foil, in particular a thin copper foil, as a cover metal layer on the first side of the substrate.
  • the method includes at least one of the steps a. to c. includes: a.
  • the cover metal layer is formed on the first side of the substrate by means of physical or chemical vapor deposition.
  • the cover metal layer is formed on the first side of the substrate by sputtering.
  • the cover metal layer is formed by a wet chemical coating process.
  • a copper layer is particularly preferably sputtered onto the base substrate as the cover metal layer.
  • an adhesion-promoting adhesion layer is applied to the first side of the substrate before the formation of the cover metal layer or when the cover metal layer is applied.
  • the method comprises one of the following steps a. or b .: a. The removal of the cover metal layer in regions on the first side of the substrate takes place using a masking step and a wet chemical etching step. b. The removal of the cover metal layer on the first side of the substrate in certain areas is carried out by means of a laser.
  • the removal of the first cover metal layer using the masking and wet-chemical etching step is a classic procedure that does not require detailed explanation.
  • the cover metal layer can be coated, for example, in a first step with a photoresist, which is exposed in areas and removed in the exposed areas with the aid of a developer solution, as described at the beginning.
  • the exposed cover metal layer is then etched away in the wet chemical etching step. This can be done, for example, with the aid of etching solutions based on copper chloride or ammonium persulfate.
  • the cover metal layer can be removed by means of the laser.
  • the method comprises one of the following steps a. and b .: a. A process gas from the group with 0 2 , H 2 , N 2 , argon, helium, CF, C 3 F 8 , CHF 3 and mixtures of the aforementioned gases such as 0 2 / CF 4 is used to provide the plasma. b. The action of the plasma takes place at a temperature in the range from minus 15 ° C to 200, preferably in the range from minus 15 ° C to 80 ° C.
  • the process gas used in the context of the present invention to provide plasma comprises at least one of the reactive gases from the group with CF, C 3 F 8 and CHF 3 .
  • Etching by means of a plasma is also state of the art.
  • process gases are used that can convert the material to be etched into the gas phase.
  • the gas enriched with the etched material is pumped out and fresh process gas is supplied. In this way, continuous removal is achieved.
  • an inductively coupled plasma ICP plasma is particularly preferred, for example generated by an ICP generator with DC bias.
  • the process gases mentioned immediately above are particularly suitable for etching the above-mentioned preferred polymer materials.
  • the base substrate made of the polymer material can come into direct contact with the plasma, while the at least one second sub-area of the first substrate side is covered with the cover metal layer.
  • metals are etched more slowly than polymer materials by a plasma, in particular when using the process gases mentioned.
  • the action of the plasma leads to the formation of depressions exclusively in the area of the at least one first sub-area of the first substrate side, while the cover metal layer forms a barrier that shields the at least one second sub-area from the plasma.
  • the surface of the base substrate can be structured specifically with depressions.
  • the plasma is used as part of an anisotropic etching process.
  • ions of the plasma are accelerated perpendicular to the surface of the substrate to be etched.
  • the accelerated ions ensure physical sputtering.
  • Embodiments of reactive ion etching (RIE) and reactive ion beam etching (RIBE) are particularly suitable as anisotropic etching process.
  • the method according to the invention is accordingly characterized by at least one of the immediately following steps and / or features a. to c. from: a.
  • the plasma in step c. and / or j. of claim 1 is used in the context of an anisotropic etching process.
  • ions of the plasma are accelerated perpendicular to the first substrate side (101a) and / or to the top side (110a).
  • the process gas used to provide plasma comprises at least one of the reactive gases from the group with CF, C 3 F 8 and CHF 3 .
  • the method can take the immediately following additional steps a. and b. include: a. Before step a. of claim 1, at least one recess is introduced into the first substrate side as part of a pretreatment. b. To provide the base substrate in step a. of claim 1, the first substrate side with the at least one recess is covered with the cover metal layer.
  • a base substrate pretreated in this way is subjected to the described plasma treatment, this leads to the described formation of the at least one depression in the at least one first partial area of the first substrate side. And where the depressions made in the base substrate during the pretreatment overlap with the first sub-area, they are deepened further by the plasma treatment.
  • the introduction of the at least one depression in the course of the pretreatment is preferably likewise carried out by the action of a plasma, analogously to step c. of claim 1.
  • the pretreatment can also include photolithographic steps.
  • the method comprises one of the following steps a. until about. To fill the at least one recess, the at least one recess is metallized in one step and the metallized at least one recess is filled with the filler metal in a subsequent step. b. The metallization of the at least one recess takes place by means of physical or chemical vapor deposition, in particular by means of sputtering the first substrate side, or by a wet chemical process. c. The first side of the substrate is completely metallized.
  • a thin layer of copper or a copper alloy is preferably formed as part of the metallization.
  • the metallization takes place, for example, by deposition of copper from a solution.
  • the filling with the filler metal is preferably carried out by means of electrochemical deposition.
  • Filling is particularly preferably carried out using a so-called via-fill method, which enables the deposition to take place primarily in the at least one recess and, if necessary, in bores or blind holes, while at the same time minimizing unwanted deposition on the first side of the substrate and reinforcing the cover metal layer rich in the at least one second Operabe.
  • a metallization layer applied over the entire surface enables electrical contact to be made with the first substrate side in order to be able to position a cathodic contact there for a subsequent electrochemical deposition and to ensure that the entire substrate side can be coated.
  • filler metal all metals and alloys from which conductor track structures can be made on circuit boards can be used as filler metal.
  • a. the filler metal with which the at least one recess is filled is copper or a copper alloy.
  • the method comprises one of the following steps a. or b .: a.
  • the cover metal layer is removed in the at least one second partial area by means of an etching step.
  • the cover metal layer is removed in the at least one second partial area by means of mechanical processing of the first substrate side.
  • the etching step is, for example, a classic etching step using a strong acid such as hydrochloric acid.
  • the cover metal layer can be removed, for example, by polishing and / or by grinding.
  • the aim is to completely remove the cover metal layer in the at least one second partial area. Only then is the formation of the conductor structure or part of the conductor structure completed.
  • the complete removal of the cover metal layer preferably also includes the removal of filler metal in the at least one partial area and optionally also in the area of the at least one recess, provided that the filler metal protrudes beyond the edge or the edges of the at least one recess.
  • the aim of planarization is to level the first substrate side in such a way that it does not have any conductor tracks protruding from the surface. Instead, the conductor structure is preferably completely sunk into the at least one depression.
  • the conductor structure formed lies within the base substrate in one plane.
  • the process also enables the production of MLBs, i.e. printed circuit boards that contain conductor structures on different levels.
  • the method according to the invention is characterized by the two additional steps a that follow immediately. and b. from: a.
  • the base substrate is provided with a first and a second substrate side, which is covered with a cover metal layer in both cases. b. Both sides of the substrate are treated with steps b. to e. of claim 1, optionally also with steps b. to f. of claim 1, subjected.
  • Step b In the case of variant 1, it is therefore mandatory in detail
  • a partial removal of the cover metal layer on the first and the second substrate side subdividing the substrate sides into at least one first sub-area in which the substrate sides are free of the cover metal layer, and in at least one second sub-area in which the substrate sides with the cover metal layer are covered,
  • the substrate sides are preferably treated one after the other.
  • the method according to the invention is characterized by the three additional steps a that follow immediately. to c. from: a. Provision of a base substrate on whose first substrate side according to steps b. to f of claim 1 a conductor structure has been formed and the second substrate side of which is free from a cover metal. b. Application of a cover metal layer to the second side of the substrate. c. Formation of a conductor structure on the second substrate side by treating the second substrate side with steps b. to e. of claim 1, optionally also with steps b. to f. of claim 1.
  • Step c In the case of variant 2, it is therefore mandatory in detail
  • the method according to the invention is characterized by the four additional steps a immediately following. to d. from: a. A base substrate, the first substrate side of which to form the conductor structure of a treatment according to steps b. to e. of claim 1, preferably according to steps b. to f. of claim 1, is provided to form a multilayer circuit board as a first circuit board layer with the conductor structure as the first conductor structure. b. Covering the first conductor structure with an insulation layer which, in combination with the base substrate, has an underside in direct contact with the conductor structure and an upper side facing away from the conductor structure and which consists at least partially of an electrically nonconductive organic polymer material. c.
  • Step d. includes in variant 3 in detail
  • variants 1 and 2 lead to a base substrate, the two substrate sides of which are each provided with a conductor structure sunk into at least one recess
  • variant 3 leads to a multilayer circuit board that comprises at least two circuit board layers, each with a conductor structure.
  • base substrates treated according to variants 1 and 2 in which there is already a conductor structure on the first and second substrate side, serve as the first circuit board layer and can be further processed according to variant 3.
  • Variant 3 enables the sequential construction of circuit boards with basically any number of circuit board layers. For example, a further insulation layer can be applied to the second conductor structure and subjected to the same treatment as the insulation layer applied to the first conductor structure. These steps can be repeated as often as you like.
  • steps b. to f. of claim 1 the selection and nature of the base substrates and the selection and application of the cover metal layers and the filler metal, the preferred developments already described above apply.
  • the insulation layer as in step a. of claim 1 provided Ba sissubstrat can be formed.
  • the insulating layer is particularly preferably a film made from one of the aforementioned electrically non-conductive organic polymer materials.
  • the application of the insulation layer in variant 3 is preferably carried out by lamination, coating or gluing.
  • Circuit boards produced according to variant 3 have conductor structures in different layers. In order to electrically connect the conductor structures with one another, vias are required. Two approaches A and B are particularly preferred for forming the vias:
  • the method according to the invention according to variant 3 is characterized by the two additional steps a immediately following. and b. from: a. When treating the upper side, between the plasma treatment and the filling with the filler metal, at least one depression formed on the upper side is connected to a depression in the first circuit board layer already filled with the filler metal by a bore. b. Filling the at least one recess with the filler metal also includes filling the bore.
  • the plated-through hole can therefore be elegantly integrated into a method according to the invention without causing significant additional expense.
  • the bore is particularly preferably a laser bore.
  • conductor structures formed according to variants 1 and 2 can also be electrically contacted. If, for example, according to variant 2, a conductor structure is formed on the second substrate side, one or more of the depressions formed can be connected to the conductor structure on the first substrate side by means of a hole after the plasma has acted on the second substrate side. The electrical contact is then made during the subsequent filling of the bore and the recesses with the filler metal.
  • the method according to the invention according to variant 3 comprises the immediately following six steps a. to f .: a. A base substrate, the first substrate side of which, forming a conductor structure, of a treatment according to the invention according to steps b. to e. of claim 1, preferably according to steps b. to f. of claim 1, is provided for the formation of a multilayer printed circuit board as the first printed circuit board layer with the conductor structure formed as the first conductor structure. b.
  • the first conductor structure is covered with an insulation layer which, in combination with the base substrate, has an underside in direct contact with the conductor structure and an upper side facing away from the conductor structure and which consists at least partially of an electrically nonconductive organic polymer material. c.
  • At least one first depression is made in the top side of the insulation layer, in particular by means of the action of a plasma.
  • formation of a cover metal layer on the upper side with at least one first recess. e. Area-wise removal of the cover metal layer, subdividing the top into at least one first sub-area in which the top is free of the cover metal layer, and in at least one second sub-area in which the top is covered with the cover metal layer. is covered, wherein the at least one first partial area comprises the at least one first, previously introduced depression in the top of the insulation layer.
  • step c. at least one depression made in the upper side of the insulation layer deepened further, at least as far as it lies in the at least one first partial area. Given a sufficiently long exposure time, this can result in a breakthrough which, with appropriate metallization and / or filling with a filler metal, can serve for through-hole plating, in particular for the first conductor structure.
  • step c Any treatment carried out on the top side of the insulation layer is preferably carried out like the pretreatment of the base substrate described above.
  • external conductor structures formed according to the method are coated with a solder resist to protect them.
  • Free contacts can be coated with a precious metal such as gold, silver or platinum.
  • a printed circuit board according to the invention is characterized by the following features: a. It comprises a base substrate with a first and a second substrate side. b. The base substrate has at least one depression on the first substrate side, in which a conductor structure is embedded. c. The base substrate has a planarized surface on the first substrate side.
  • the circuit board is characterized by the immediately following feature a. out: a. It has a multilayer structure and comprises the base substrate as a first circuit board layer with a first conductor structure and an insulation layer as a second circuit board layer with a second conductor structure.
  • the circuit board preferably has between 2 and 20 circuit board layers.
  • printed circuit boards can be produced with the highest resolution in the pm range, specifically with less effort and lower production costs with a higher yield than the state of the art allows.
  • the disadvantages of the subtractive as well as additive and semi-additive methods mentioned at the beginning are avoided.
  • channels could also be formed with the aid of a laser.
  • plasma etching offers the advantage that, with plasma etching, all channels and other indentations can be formed simultaneously and in one step, which is generally many times faster and more cost-effective. Furthermore, higher resolutions can be achieved by means of plasma etching.
  • Figure 1 shows the sequence of a method according to the invention according to the variant 3 and described above
  • FIGS. 2 and 3 are microscopic recordings of base substrates etched by means of a plasma within the scope of a method according to the invention.
  • a base substrate 101 is provided. This is covered with a cover metal layer 102 on its first substrate side 101a in step B.
  • a resist 103 is applied to the cover metal layer 102 in step C, which is exposed and removed in step D in the first partial areas 104.
  • the cover metal layer 102 is removed in the first partial regions 104, which are no longer covered by the resist 103, by means of an etching solution.
  • the substrate side 101a originally completely covered with the cover metal layer 102 is now divided into the first subregions 104, in which it is free of the cover metal layer 102, and into the second subregions 105, in which it is still covered with the cover metal layer 102.
  • step F a plasma is allowed to act on the substrate side 101a. While the subareas 105 are shielded from the plasma by the cover metal layer 102, this causes material to be removed in the subareas 104 and consequently the formation of the depressions 106. At the same time, the resist 103 is also completely removed.
  • step G the depressions 106 are metallized by means of sputtering, followed by filling of the depressions 106 by means of electrochemical deposition of a filler metal 108 in step H. Excess filler metal 108 is then mechanically removed in step I together with the cover metal layer 102 in the subareas 105 .
  • the conductor structure 109 is formed, which is sunk into the 106 gene.
  • step J an insulation layer 110 is laminated directly onto the substrate side 101a with the conductor structure 109.
  • step K its top 110a is covered with a cover metal layer 111, which in steps L, M and N - in analogy to steps C, D and E - with the application of a resist 112 and its partial removal with an etching solution becomes.
  • the top side 110a of the insulation layer 110 which was originally completely covered with the cover metal layer 111, is now divided into the first subregions 113, in which it is free of the cover metal layer 111, and the second subregions 114, in which it is still with the Cover metal layer 111 is covered.
  • a plasma is allowed to act on the top side 110a of the insulation layer 110.
  • step P one of the recesses 115 formed is connected through a bore 116 to a recess 106 in the first conductor structure 109 that is already filled with the filler metal 108.
  • step Q metallization of the recesses 115 including the bore 116 by means of sputtering, followed by filling of the recesses 115 by means of electrochemical deposition of a filler metal 118 in step R.
  • step S Excess filler metal 118 is then in step S together with the cover metal layer 111 in mechanically removed from the subregions 114.
  • the conductor structure 119 is formed, which is sunk into the depressions 115.
  • step T a solder resist 120 is applied, followed by partial gold plating 121 of individual contacts of the conductor structure 119.
  • a reduction in the number of individual steps of the method described can be achieved by structuring the cover metal layers by means of a laser instead of the photolithographic structuring of the cover metal layers 102 and 111 in steps C to E and L to N.
  • the base substrates shown in FIGS. 2 and 3 were treated by means of RIE in step F of the process sequence shown in FIG. 1 and illustrate the result of the plasma treatment.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

L'invention concerne un procédé de fabrication d'une carte de circuits imprimés, dans lequel un substrat de base (101) réalisé en tant que film ou plaque est fourni avec un premier côté de substrat (101a) et un deuxième côté de substrat. Le substrat de base est constitué au moins en partie d'un matériau polymère organique électriquement non conducteur. Le premier côté de substrat (101a) est recouvert d'une couche métallique de recouvrement (102). La couche métallique de recouvrement (102) est retirée par endroits en divisant le premier côté de substrat (101a) en au moins une première zone partielle (104), dans laquelle le premier côté de substrat (101a) est sans couche métallique de recouvrement (102), et en au moins une deuxième zone partielle (105), dans laquelle le premier côté de substrat (101a) est recouvert de la couche métallique de recouvrement (102). Par l'action d'un plasma sur le premier côté de substrat (101a), le matériau polymère est retiré dans la ou les premières zones partielles (104) en formant au moins un renfoncement (106). Puis, le ou les renfoncements (106) sont remplis d'un métal de remplissage (108), et la couche métallique de recouvrement (102) est enlevée en formant la structure conductrice (109) ou une partie d'une structure conductrice dans la ou les deuxièmes zones partielles (105). Si nécessaire, le premier côté de substrat (101a) est ensuite planarisé avec le ou les renfoncements (106) remplis. Le procédé est adapté pour fabriquer des cartes de circuits imprimés mono- et multicouches.
EP20734156.1A 2019-07-04 2020-06-18 Procédé de fabrication de cartes de circuits imprimés, et cartes de circuits imprimés fabriquées selon le procédé Pending EP3994963A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102019209889.4A DE102019209889A1 (de) 2019-07-04 2019-07-04 Verfahren zur Leiterplattenherstellung sowie gemäß dem Verfahren hergestellte Leiterplatten
PCT/EP2020/067042 WO2021001167A1 (fr) 2019-07-04 2020-06-18 Procédé de fabrication de cartes de circuits imprimés, et cartes de circuits imprimés fabriquées selon le procédé

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EP3994963A1 true EP3994963A1 (fr) 2022-05-11

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US (1) US20220361341A1 (fr)
EP (1) EP3994963A1 (fr)
JP (1) JP2022537656A (fr)
KR (1) KR20220030279A (fr)
CN (1) CN114009154A (fr)
DE (1) DE102019209889A1 (fr)
TW (1) TW202109622A (fr)
WO (1) WO2021001167A1 (fr)

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DE102021209939A1 (de) 2021-09-08 2023-03-09 Gebr. Schmid Gmbh Verfahren zur Leiterplattenherstellung und Leiterplatte
CN115884494A (zh) * 2021-09-28 2023-03-31 深南电路股份有限公司 一种线路内埋方法及线路内埋pcb板
CN114745845B (zh) * 2022-04-30 2023-08-08 苏州浪潮智能科技有限公司 一种印刷电路板及制造方法

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EP0127689B1 (fr) * 1983-05-19 1987-08-26 Ibm Deutschland Gmbh Procédé pour la fabrication de circuits imprimés ayant des conducteurs métalliques incrustés dans le support isolant
US5173442A (en) * 1990-07-23 1992-12-22 Microelectronics And Computer Technology Corporation Methods of forming channels and vias in insulating layers
US5244538A (en) * 1991-07-26 1993-09-14 Microelectronics And Computer Technology Corporation Method of patterning metal on a substrate using direct-write deposition of a mask
JP3361556B2 (ja) * 1992-09-25 2003-01-07 日本メクトロン株式会社 回路配線パタ−ンの形成法
JPH07240568A (ja) * 1994-02-28 1995-09-12 Mitsubishi Electric Corp 回路基板およびその製造方法
US6518160B1 (en) * 1998-02-05 2003-02-11 Tessera, Inc. Method of manufacturing connection components using a plasma patterned mask
US20060127686A1 (en) * 2004-12-15 2006-06-15 Meloni Paul A Thermally conductive polyimide film composites having high thermal conductivity useful in an electronic device
TWI253714B (en) * 2004-12-21 2006-04-21 Phoenix Prec Technology Corp Method for fabricating a multi-layer circuit board with fine pitch
KR101267277B1 (ko) * 2011-05-19 2013-05-24 한국기계연구원 유연기판의 금속배선 형성방법
US20140027163A1 (en) * 2012-07-30 2014-01-30 Samsung Electro-Mechanics Co., Ltd. Printed circuit board and method for manufacturing the same
JP6044592B2 (ja) * 2014-05-29 2016-12-14 トヨタ自動車株式会社 多層配線基板及びその製造方法

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KR20220030279A (ko) 2022-03-10
US20220361341A1 (en) 2022-11-10
DE102019209889A1 (de) 2021-01-07
TW202109622A (zh) 2021-03-01
CN114009154A (zh) 2022-02-01
JP2022537656A (ja) 2022-08-29
WO2021001167A1 (fr) 2021-01-07

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