EP3937159A2 - Dispositif d'affichage et son procédé de fabrication - Google Patents

Dispositif d'affichage et son procédé de fabrication Download PDF

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Publication number
EP3937159A2
EP3937159A2 EP21167969.1A EP21167969A EP3937159A2 EP 3937159 A2 EP3937159 A2 EP 3937159A2 EP 21167969 A EP21167969 A EP 21167969A EP 3937159 A2 EP3937159 A2 EP 3937159A2
Authority
EP
European Patent Office
Prior art keywords
detection line
ddv
cds
crack detection
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP21167969.1A
Other languages
German (de)
English (en)
Other versions
EP3937159A3 (fr
Inventor
Hongam Kim
Youngmin Cho
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Display Co Ltd
Original Assignee
Samsung Display Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Display Co Ltd filed Critical Samsung Display Co Ltd
Publication of EP3937159A2 publication Critical patent/EP3937159A2/fr
Publication of EP3937159A3 publication Critical patent/EP3937159A3/fr
Pending legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/70—Testing, e.g. accelerated lifetime tests
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2380/00—Specific applications
    • G09G2380/02—Flexible displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/40—Thermal treatment, e.g. annealing in the presence of a solvent vapour
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • the disclosure herein relates to a display device and a method of manufacturing the same, and more specifically, to a display device and a method of manufacturing the same with improved reliability by readily inspecting damage to a display panel, which may occur during a bonding process between a display panel and a driving circuit.
  • Display devices such as a television, a monitor, a smart phone, and a tablet that provide an image to a user include a display panel that displays an image.
  • a display panel various display panels such as a liquid crystal display panel, an organic light emitting display panel, an electro wetting display panel, and an electrophoretic display panel are being developed.
  • the display panel includes pixels that display an image and a driving chip for driving the pixels.
  • the pixels are disposed in the display area of the display panel, and the driving chip is disposed in the non-display area of the display panel surrounding the display area.
  • a bent portion is defined between the driving chip and the display area, and the bent portion is bent so that the driving chip is disposed under the display panel.
  • the disclosure provides a display device with improved reliability and a method of manufacturing the same.
  • the disclosure also provides a display device with improved reliability and a method of manufacturing the display device that can readily detect damage to a display panel that may have occurred in the bonding process of a driving circuit and a display panel including a flexible base layer.
  • An embodiment provides a display device including a display panel including a display area displaying an image, a non-display area adjacent to the display area, and a plurality of signal lines; and a driving circuit disposed in the non-display area.
  • the driving circuit may include a plurality of bumps arranged in a plurality of rows, the plurality of bumps may include a crack detection bump arranged in at least one row among the plurality of rows, the plurality of signal lines may include a crack detection line electrically connected to the crack detection bump, and at least a portion of the crack detection line may be disposed adjacent to an edge of the driving circuit.
  • the driving circuit may include at least one long side extending in a first direction parallel to the plurality of rows, and at least one short side extending in a second direction intersecting the first direction, and the at least a portion of the crack detection line may be disposed adjacent to the at least one short side.
  • the crack detection line may be disposed adjacent to at least a portion of the at least one long side of the driving circuit.
  • the plurality of circuit board pads may include resistance test pads, and the crack detection line may be electrically connected to the resistance test pads.
  • each of the first detection line and the second detection line may include a structure forming a loop structure through a plurality of detection lines extending along the edge of the driving circuit.
  • the crack detection bump may include first to fourth crack detection bumps.
  • the first detection line may include a first input detection line electrically connected to the first crack detection bump and a first output detection line electrically connected to the second crack detection bump.
  • the second detection line may include a second input detection line electrically connected to the third crack detection bump and a second output detection line electrically connected to the fourth crack detection bump.
  • the first detection line may have a structure in which the first input detection line and the first output detection line are connected to form a loop structure
  • the second detection line may include a structure in which the second input detection line and the second output detection line are connected to form a loop structure
  • the crack detection bump may include a dummy bump disposed at an end of at least one row among the plurality of rows.
  • the method may further include electrically connecting a circuit board including a plurality of circuit board pads to the display panel, wherein the crack detection line may be electrically connected to resistance test pads among the plurality of circuit board pads, and the resistance test pads may measure a resistance of the crack detection line to determine whether a crack has occurred.
  • the driving circuit may include a crack detection bump electrically connected to the crack detection line; and a comparison unit electrically connected to the crack detection bump, and the comparison unit may measure a resistance of the crack detection line to determine whether a crack has occurred.
  • the direction substantially perpendicular to the plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3.
  • "when viewed from the plane” or “in a plan view” may be defined as a viewing an object from above in the third direction DR3.
  • the display device DD may detect an external input TC applied from the outside.
  • the external input TC may include various types of inputs provided from the outside of the display device DD.
  • the external input may be provided in various forms.
  • FIG. 3 is a schematic perspective view of a display device according to an embodiment.
  • FIG. 4 is a schematic diagram illustrating a folded state of the display device illustrated in FIG. 3 folded.
  • the folding area FA' is bent or folded along the folding axis FX' parallel to the first direction DR1, so that the display device DD-1 may be folded.
  • the folding axis FX' may be defined as a long axis parallel to the long side of the display device DD-1.
  • the display device DD illustrated in FIG. 1 may be folded along a short axis, and unlike this, the display device DD-1 illustrated in FIG. 3 may be folded on a long axis.
  • the display device DD-1 may be in-folded so that the display surface DS is not exposed to the outside.
  • the display device DD that is in-folded along the folding axis FX parallel to the short axis will be described.
  • the embodiments are not limited thereto, and the display device may be in-folded along a folding axis parallel to a long axis or may be out-folded along a folding axis defined below or under the display device.
  • FIG. 5A is a schematic plan view illustrating a display device according to an embodiment.
  • FIG. 5B is a schematic plan view of a display device according to another embodiment.
  • FIG. 5A is a schematic plan view of the display device DD illustrated in FIG. 1 .
  • FIG. 5B is a schematic plan view illustrating a display device DD-a according to another embodiment among the display device(s) illustrated in FIG. 1 .
  • the scan lines SL1 to SLm may extend in the second direction DR2 and may be electrically connected to the scan driver SDV.
  • the data lines DL1 to DLn extend in the first direction DR1 and may be electrically connected to the data driver DDV through the bending area BA.
  • the emission lines EL1 to ELm may extend in the second direction DR2 to be connected to the emission driver EDV.
  • the first power line PL1 may extend to the second area AA2 through the bending area BA.
  • the first power line PL1 may extend toward a lower end of the second area AA2 in a plan view.
  • the first power line PL1 may receive a first voltage.
  • the second power line PL2 may be disposed in the non-display area NDA adjacent to the long sides of the first area AA1 and the non-display area NDA facing the second area AA2 with the display area DA interposed therebetween.
  • the second power line PL2 may be disposed outside the scan driver SDV and the emission driver EDV.
  • the second power line PL2 may extend to the second area AA2 through the bending area BA.
  • the second power line PL2 may extend in the first direction DR1 in the second area AA2 with the data driver DDV therebetween.
  • the second area AA2 may extend toward a lower end of the second area AA2 in a plan view.
  • the second power line PL2 may receive a second voltage having a lower level than the first voltage.
  • the connection relationship is not shown, and the second power line PL2 may extend to the display area DA and may be electrically connected to the pixels PX, and a second voltage may be provided to the pixels PX through the second power line PL2.
  • connection circuit lines CTL may extend in the second direction DR2 and may be arranged in the first direction DR1.
  • the connection circuit lines CTL may be electrically connected to the first power line PL1 and the pixels PX.
  • the first voltage may be applied to the pixels PX through the first power line PL1 and the connection circuit lines CTL electrically connected to each other.
  • the first control line CSL1 may be electrically connected to the scan driver SDV and may extend toward the lower end of the second area AA2 through the bending area BA.
  • the second control line CSL2 may be electrically connected to the emission driver EDV and may extend toward the lower end of the second area AA2 through the bending area BA.
  • the data driver DDV may be disposed between the first control line CSL1 and the second control line CSL2.
  • the signal pads DP-PD may be disposed adjacent to the lower end of the second area AA2.
  • the data driver DDV, the first power line PL1, the second power line PL2, the first control line CSL1, and the second control line CSL2 may be electrically connected to the signal pads DP-PD.
  • the data lines DL1 to DLn may be electrically connected to the corresponding signal pads DP-PD through a data driver DDV.
  • the data lines DL1 to DLn may be electrically connected to the data driver DDV, and the data driver DDV may be electrically connected to the signal pads DP-PD respectively corresponding to the data lines DL1 to DLn.
  • the timing controller may control operations of the scan driver SDV, the data driver DDV, and the emission driver EDV.
  • the timing controller may generate a scan control signal, a data control signal, and an emission control signal in response to control signals received from the outside.
  • the scan control signal may be provided to the scan driver SDV through the first control line CSL1.
  • the emission control signal may be provided to the emission driver EDV through the second control line CSL2.
  • the data control signal may be provided to a data driver DDV.
  • the timing controller receives the image signals from the outside, converts the data format of the image signals to match the interface specification with the data driver DDV, and provides the converted image data to the data driver DDV.
  • the scan driver SDV may generate scan signals in response to the scan control signal.
  • the scan signals may be applied to the pixels PX through the scan lines SL1 to SLm.
  • the scan signals may be sequentially applied to the pixels PX.
  • the data driver DDV may generate data voltages corresponding to the image signals in response to the data control signal.
  • the data voltages may be applied to the pixels PX through the data lines DL1 to DLn.
  • the emission driver EDV may generate emission signals in response to the emission control signal.
  • the emission signals may be applied to the pixels PX through the emission lines EL1 to ELm.
  • the data driver DDV, the scan driver SDV, and the emission driver EDV may be referred to as a driving circuit according to an embodiment, and hereinafter, in describing the driving circuit according to an embodiment, the data driver DDV is described as an example, and the data driver DDV is referred to as a driving circuit.
  • a crack detection line CDS is disposed on the second area AA2 of the display panel DP to be adjacent to one side of the data driver DDV.
  • the crack detection line CDS is disposed adjacent to a side of the data driver DDV to detect defects such as cracks occurring in the peripheral area of the data driver DDV.
  • description of the data driver DDV and the crack detection line CDS will be described below.
  • a data line, a scan line, an emission line, a control line, a connection line, and a crack detection line are referred to as signal lines disposed on the display panel.
  • the pixels PX may be provided with the data voltages in response to the scan signals.
  • the pixels PX may display an image by emitting light having luminance corresponding to data voltages in response to emission signals.
  • the emission time of the pixels PX may be controlled by emission signals.
  • the display device DD may further include a circuit board PCB electrically connected to the display panel DP.
  • the circuit board PCB may be a rigid circuit board or a flexible circuit board.
  • a timing control circuit for controlling the operation of the display panel DP may be disposed on the circuit board PCB.
  • An input detection circuit for controlling the input detection unit ISP may also be disposed on the circuit board PCB.
  • Each of the timing control circuit and the input detection circuit may be mounted on a circuit board PCB in the form of an integrated chip.
  • the timing control circuit and the input detection circuit may be mounted on a circuit board PCB in the form of an integrated chip.
  • the circuit board PCB may include circuit board pads PCB-PD electrically connected to the signal pads DP-PD of the display panel.
  • the circuit board PCB may further include signal lines electrically connecting the circuit board pads PCB-PD to the timing control circuit and/or the input detection circuit.
  • the circuit board pads PCB-PD may be output pads, and the circuit board PCB may further include an input pad.
  • the display panel DP-1 included in the display device DD-a may further include a module crack detection line MCD.
  • the module crack detection line MCD may be disposed in the non-display area NDA of the first area AA1 of the display panel DP-1 and may be disposed at the outermost side of the display panel DP.
  • the module crack detection line MCD may be disposed outside the configuration of the scan driver SDV, the emission driver EDV, and the second power line PL2, and may be disposed adjacent to the outer line of the display device DD-a.
  • the module crack detection line MCD may detect defects such as cracks occurring in the outermost area of the display device DD-a.
  • the module crack detection line MCD may be electrically connected to at least one of the signal pads DP-PD of the display panel DP-1, and the signal pads DP-PD of the display panel DP-1 may be electrically connected to the circuit board pads PCB-PD of the circuit board PCB.
  • the circuit board PCB may further include a crack detection circuit that receives an electrical signal from the module crack detection line MCD and determines whether a crack has occurred in the outermost area of the display device DD-a.
  • the embodiments are not limited thereto, and the module crack detection line MCD may be electrically connected to the driving circuit DDV, and in this case, the driving circuit DDV may further include a crack detection circuit for determining whether a crack has occurred in the outermost area of the display device DD-a.
  • FIG. 6 is a schematic diagram illustrating a cross-section of a display panel according to an embodiment. For example, in FIG. 6 , a cross section of the display panel DP viewed from the first directional axis DR1 is illustrated.
  • the display panel DP may include a base layer BL, a circuit element layer DP-CL disposed on the base layer BL, a display element layer DP-OLED disposed on the circuit element layer DP-CL, a thin film sealing layer TFE disposed on the display element layer DP-OLED, and an input detection unit ISP disposed on the thin film sealing layer TFE.
  • the display element layer DP-OLED may be disposed on the display area DA.
  • the base layer BL may include the display area DA and the non-display area NDA around the display area DA.
  • the base layer BL may include a flexible material.
  • the base layer BL may include a flexible plastic material.
  • the base layer BL may include polyimide (PI).
  • the base layer BL may include polyimide having a low modulus.
  • the circuit element layer DP-CL may include an insulating layer, a semiconductor pattern, a conductive pattern, and a signal line.
  • An insulating layer, a semiconductor layer, and a conductive layer may be formed on the base layer BL by coating and evaporation. Thereafter, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by photolithography processes to form a semiconductor pattern, a conductive pattern, and a signal line.
  • the circuit element layer DP-CL may include transistors formed of a semiconductor pattern, a conductive pattern, and a signal line.
  • the display element layer DP-OLED may include light emitting elements electrically connected to transistors.
  • the pixels PX may include transistors and light emitting elements.
  • the thin film sealing layer TFE may be disposed on the circuit element layer DP-CL to cover or overlap the display element layer DP-OLED.
  • the thin film sealing layer TFE may include an inorganic material layer, an organic material layer, and an inorganic material layer sequentially stacked.
  • the inorganic material layers may include an inorganic material and may protect the pixels from moisture or oxygen.
  • the organic material layer may include an organic material and may protect the pixels PX from foreign substances such as dust particles.
  • the input detection unit ISP may include sensors (not shown) for detecting an external input TC (see FIG. 1 ).
  • the sensors may detect the external input TC (see FIG. 1 ) by a capacitive method.
  • the external input TC (see FIG. 1 ) may include various types of inputs such as part of the user's body, light, heat, pen, or pressure.
  • the input detection unit ISP may be manufactured directly on the thin film sealing layer TFE.
  • the embodiments are not limited thereto, and the input detection unit ISP may be manufactured as a panel separated from the display panel DP and then, attached to the display panel DP by an adhesive.
  • FIG. 7 is a schematic partial cross-sectional view of a display device according to an embodiment.
  • FIG. 7 is a schematic cross-sectional view taken along line I-I' shown in FIGS. 5A and 5B .
  • the driving circuit DDV includes a driving chip DV-BS and bumps DDV-BP.
  • the driving chip DV-BS provides a base surface on which components such as the bumps DDV-BP are disposed.
  • the bumps DDV-BP may be disposed in rows on the driving chip DV-BS.
  • the bumps DDV-BP may include an input bump DV-IP that receives control signals and power provided from the circuit board PCB and may output bumps DV-OP1, DV-OP2, DV-OP3, DV-OP4, and DV-OP5 for driving the display panel DP.
  • the output bumps are provided in multiple rows, and as shown in FIG.
  • the embodiments are not limited thereto.
  • the output bumps DV-OP1, DV-OP2, DV-OP3, DV-OP4, and DV-OP5 may be arranged in 2 to 4 rows or 6 or more rows.
  • a detailed description of the plurality of bumps DDV-BP included in the driving circuit DDV will be described below.
  • the pads PD may be included on the base layer BL of the display panel DP.
  • the pads PD respectively correspond to the bumps DDV-BP, and may include a first pad PD1, a second pad PD2, a third pad PD3, a fourth pad PD4, a fifth pad PD5, and a sixth pad PD6.
  • the first pad PD1, the second pad PD2, the third pad PD3, the fourth pad PD4, and the fifth pad PD5 may be arranged to correspond to the plurality of output bumps DV-OP1, DV-OP2, DV-OP3, DV-OP4, and DV-OP5, and the sixth pad PD6 may be disposed to correspond to the input bump DV-IP.
  • An anisotropic conductive film ACF is disposed between the display panel DP and the driving circuit DDV, and the display panel DP and the driving circuit DDV may be attached to each other by the anisotropic conductive film ACF.
  • the anisotropic conductive film ACF may include an adhesive resin RS and conductive particles CB.
  • the conductive particles CB are disposed between the bumps DDV-BP and the pads PD to electrically connect the bumps DDV-BP to the pads PD.
  • the display panel DP and the driving circuit DDV may be attached and electrically connected to each other with the anisotropic conductive film ACF therebetween by a pressing and heating process.
  • the embodiments are not limited thereto, and the anisotropic conductive film ACF is omitted in the display device DD of an embodiment, and the display panel DP and the driving circuit DDV may be electrically connected by an ultrasonic bonding process or the like.
  • the circuit board PCB may be electrically connected to the display panel DP through the anisotropic conductive film ACF.
  • the circuit board PCB may include a circuit base layer PCB-BS and circuit board pads PCB-PD disposed on the circuit base layer PCB-BS and electrically connected to the signal pads DP-PD of the display panel DP.
  • FIG. 8 is a schematic plan view showing an arrangement of bumps of a driving circuit according to an embodiment.
  • the bumps DDV-BP may include an output bump including first bumps DV-OP1, second bumps DV-OP2, third bumps DV-OP3, fourth bumps DV-OP4, and fifth bumps DV-OP5, which are arranged in output rows R-1, R-2, R-3, R-4, and R-5, and an input bump DV-IP disposed on the input row R-I.
  • FIGS. 7 and 8 illustrate that the output bump includes five output rows R-1, R-2, R-3, R-4, and R-5, but the embodiments are not limited thereto.
  • the output bumps may be arranged in 2 to 4 rows, or 6 or more rows.
  • the first row R-1 may be the row closest to the display area DA (see FIGS. 5A and 5B ) when applied to the display device according to an embodiment.
  • the first row R-1 may be defined adjacent to the first long side DDV-S1 adjacent to the display area DA among the long sides DDV-S1 and DDV-S2 of the driving circuit DDV.
  • the input row R-I may be defined adjacent to the second long side DDV-S2 spaced apart from the display area DA.
  • the driving circuit DDV may further include output bumps and signal lines respectively connected to the input bumps.
  • Each of the output bumps and the input bumps may be disposed in the second direction DR2 and may be spaced apart in the first direction DR1.
  • Long sides DDV-S1 and DDV-S2 of the driving circuit DDV may extend in the second direction DR2, and short sides DDV-S3 and DDV-S4 of the driving circuit DDV may extend in the first direction DR1.
  • the first direction DR1 may be referred to as a column direction
  • the second direction DR2 may be referred to as a row direction.
  • First bumps DV-OP1, second bumps DV-OP2, third bumps DV-OP3, fourth bumps DV-OP4, and fifth bumps DV-OP5 may each include n bumps, where n is a natural number.
  • n is a natural number.
  • the number of each bump forming the first bumps DV-OP1, the second bumps DV-OP2, the third bumps DV-OP3, the fourth bumps DV-OP4, and the fifth bumps DV-OP5 may be the same.
  • the embodiments are not limited thereto, and the number of bumps arranged in each column may be different depending on the structure of the display device.
  • the first reference bump disposed in the center of the first bumps DV-OP1 and the second reference bump disposed in the center of the second bumps DV-OP2 may be disposed on the reference line VL defined in the second direction DR2.
  • a third reference bump disposed at the center of the third bumps DV-OP3 may also be disposed on the reference line VL.
  • the fourth reference bump disposed at the center of the fourth bumps DV-OP4 may also be disposed on the reference line VL
  • the fifth reference bump disposed at the center of the fifth bumps DV-OP5 may also be disposed on the reference line VL.
  • the first bumps DV-OP1 may include 1-1-th bumps DV-OP11 disposed relatively to the left and 1-2-th bumps DV-OP12 disposed relatively to the right with respect to the first reference bump.
  • the second bumps DV-OP2 may include 2-1-th bumps DV-OP21 disposed relatively to the left and 2-2-th bumps DV-OP22 disposed relatively to the right with respect to the second reference bump.
  • the third bumps DV-OP3 may include 3-1-th bumps DV-OP31 disposed relatively to the left and 3-2-th bumps DV-OP32 disposed relatively to the right with respect to the third reference bump.
  • the fourth bumps DV-OP4 may include 4-1-th bumps DV-OP41 disposed relatively to the left and 4-2-th bumps DV-OP42 disposed relatively to the right with respect to the fourth reference bump
  • the fifth bumps DV-OP5 may include 5-1-th bumps DV-OP51 disposed relatively to the left and 5-2-th bumps DV-OP52 disposed relatively to the right with respect to the 5th reference bump.
  • the 1-1-th bumps DV-OP11, the 2-1-th bumps DV-OP21, the 3-1-th bumps DV-OP31, the 4-1-th bumps DV-OP41, and the 5-1-th bumps DV-OP51 may be arranged to form an acute angle clockwise with respect to the reference line VL.
  • the 1-2-th bumps DV-OP12, the 2-2-th bumps DV-OP22, the 3-2-th bumps DV-OP32, the 4-2-th bumps DV-OP42, and the 5-2-th bumps DV-OP52 which are disposed to the right side with respect to the reference line VL, may be arranged to form an acute angle counterclockwise with respect to the reference line VL.
  • the slope of the n-th disposed bump of the first bumps DV-OP1 and the slope of the n-th disposed bump of the second bumps DV-OP2 may be the same.
  • each of the slope of the n-th disposed bump of the first bumps DV-OP1, the slope of the n-th disposed bump of the third bumps DV-OP3, the slope of the n-th disposed bump of the fourth bumps DV-OP4, and the slope of the n-th disposed bump of the fifth bumps DV-OP5 may be the same.
  • the pitch between the first bumps DV-OP1 may be smaller than the pitch between the second bumps DV-OP2.
  • the pitch between the second bumps DV-OP2 may be smaller than the pitch between the third bumps DV-OP3.
  • the pitch between the third bumps DV-OP3 may be smaller than the pitch between the fourth bumps DV-OP4.
  • a pitch between the fourth bumps DV-OP4 may be smaller than a pitch between the fifth bumps DV-OP5.
  • the arrangement interval between bumps in the first bumps DV-OP1 is the smallest, and the arrangement interval between bumps may increase toward a lower row.
  • the distance from the reference line VL to the first outermost bump of the first row R-1 may be shorter than the distance from the reference line VL to the second outermost bump of the second row R-2.
  • the distance from the reference line VL to the second outermost bump of the second row R-2 may be shorter than the distance from the reference line VL to the third outermost bump of the third row R-3.
  • the distance from the reference line VL to the third outermost bump of the third row R-3 is shorter than the distance from the reference line VL to the fourth outermost bump of the fourth row R-4, and the distance from the reference line VL to the fourth outermost bump of the fourth row R-4 may be shorter than the distance from the reference line VL to the fifth outermost bump of the fifth row R-5.
  • the distance between the first to fifth outermost bump and the reference line VL increases as the row number increases.
  • the separation distance from the short sides DDV-S3 and DDV-S4 of the driving circuit DDV to the first outermost bump may be longer than the separation distance from the short sides DDV-S3 and DDV-S4 to each of the second to fifth outermost bumps.
  • the input bump DV-IP disposed on the input row R-I may also include a reference input bump placed on the reference line VL, and a first input bumps DV-IP1 disposed relatively to the left and a second input bumps DV-IP2 disposed relatively to the right side with respect to the first reference bump.
  • Any corresponding one of the data lines DL1 to DLn may be electrically connected to each of the plurality of bumps DDV-BP.
  • Each of the output bump including first bumps DV-OP1, second bumps DV-OP2, third bumps DV-OP3, fourth bumps DV-OP4, and fifth bumps DV-OP5, which are disposed in the rows R-1, R-2, R-3, R-4, and R-5, and the input bump DV-IP disposed on the input row R-I may be electrically connected to any corresponding one among the data lines DL1 to DLn.
  • the driving circuit DDV may include a dummy bump DMB disposed in at least one of the rows R-1, R-2, R-3, R-4, R-5, and R-I.
  • the dummy bump DMB may be disposed between the outermost bump and both short sides DDV-S3 and DDV-S4 of the driving circuit DDV in at least one row of the plurality of rows R-1, R-2, R-3, R-4, R-5, and R-I.
  • the dummy bump DMB is disposed in each of the first row R-1, the second row R-2, the third row R-3, and the fourth row R-4. As shown in FIG.
  • four dummy bumps DMB may be disposed in the first row R-1, three dummy bumps DMB may be disposed in the second row R-2, two dummy bumps DMB may be disposed in the third row R-3, and one dummy bump DMB may be disposed in the fourth row R-4.
  • the number of dummy bumps DMB arranged in each row is not limited thereto.
  • the dummy bump DMB may be disposed to compensate for this.
  • the distance from the short sides DDV-S3 and DDV-S4 of the driving circuit DDV to the outermost bump or the dummy bump DMB disposed at the outermost side may be substantially the same in the first row R-1 to the fifth row R-5.
  • the dummy bump DMB may protrude by a thickness substantially equal to those of the bumps DDV-BP.
  • the dummy bump DMB and the bumps DDV-BP may include the same material and may be formed by the same process.
  • the thickness of the bumps DDV-BP may be about 7 ⁇ m or greater and about 10 ⁇ m or less, and the thickness of the dummy bump DMB may be about 7 ⁇ m or greater and about 10 ⁇ m or less.
  • the driving circuit DDV may further include alignment marks ALM1 and ALM2 disposed at an end of at least one of the rows R-1, R-2, R-3, R-4, R-5, and R-I.
  • the alignment marks ALM1 and ALM2 may include a first alignment mark ALM1 disposed at the end of the first row R-1, and a second alignment mark ALM2 disposed at the end of the input row R-I.
  • the alignment marks ALM1 and ALM2 may be disposed adjacent to a side of the driving circuit DDV.
  • the alignment marks ALM1 and ALM2 may be disposed adjacent to short sides DDV-S3 and DDV-S4 of the driving circuit DDV.
  • the dummy bump DMB may be disposed between the alignment marks ALM1 and ALM2 and the bumps DDV-BP.
  • the second alignment mark ALM2 may be omitted.
  • the alignment marks ALM1 and ALM2 may be applied as an identification mark for identifying the position of the driving circuit DDV or aligning the driving circuit DDV and the display panel DP in the process of bonding the driving circuit DDV and the display panel DP.
  • the alignment marks ALM1 and ALM2 have a cross shape, but the embodiments are not limited thereto.
  • the alignment marks ALM1 and ALM2 may have different shapes as long as they can be used to align the driving circuit DDV.
  • the driving circuit DDV may further include side bumps SDB disposed adjacent to the short sides DDV-S3 and DDV-S4.
  • the side bumps SDB are disposed adjacent to the short sides DDV-S3 and DDV-S4 of the driving circuit DDV and compensate for a step difference or height different in an area adjacent to the short sides DDV-S3 and DDV-S4 of the driving circuit DDV.
  • Side bumps SDB may be provided and may protrude by a thickness substantially equal to those of the bumps DDV-BP.
  • the side bump SDB and the bumps DDV-BP may include the same material and may be formed by the same process.
  • FIG. 9 is a schematic plan view of a partial area of a display device according to an embodiment.
  • FIG. 10 is an enlarged schematic plan view of a partial area of a display device according to an embodiment.
  • area A of FIGS. 5A and 5B and an area in which signal pads are disposed are enlarged and shown.
  • area B shown in FIG. 9 is enlarged.
  • the crack detection line CDS is disposed adjacent to the edge of the driving circuit DDV.
  • the crack detection line CDS may be disposed adjacent to short sides DDV-S3 and DDV-S4 of the driving circuit DDV.
  • the crack detection line CDS may include a left crack detection line CDS-L disposed adjacent to the first short side DDV-S3, and a right crack detection line CDS-R disposed adjacent to the second short side DDV-S4.
  • the left crack detection line CDS-L and the right crack detection line CDS-R may have symmetrical shapes with respect to the reference line VL of the driving circuit DDV.
  • Each of the left crack detection line CDS-L and the right crack detection line CDS-R may be disposed adjacent to not only the short sides DDV-S3 and DDV-S4 of the driving circuit DDV, but also at least a part of the second long sides DDV-S2.
  • Each of the detection lines included in the crack detection line CDS may have substantially the same wiring length.
  • each of the first detection line CDS1, the second detection line CDS2, the third detection line CDS3, and the fourth detection line CDS4 included in the crack detection line CDS may have substantially the same wiring length.
  • the difference in resistance due to the wiring length between each detection line can be minimized or reduced. If the lengths of at least any two detection lines of detection lines included in the crack detection line CDS are different, the display device may be provided with a compensation unit capable of applying a weight to compensate for a difference in wiring resistance between detection lines having different lengths.
  • the circuit board PCB may include circuit board pads PCB-PD, and the circuit board pads PCB-PD may include resistance test pads RTP1, RTP2, RTP3, and RTP4.
  • the resistance test pads RTP1, RTP2, RTP3, and RTP4 are electrically connected to the test signal pads DPP1, DPP2, DPP3, and DPP4 among the signal pads DP-PD of the display panel, and the crack detection line CDS may be electrically connected to the test signal pads DPP1, DPP2, DPP3, and DPP4.
  • the crack detection line CDS may be electrically connected to the resistance test pads RTP1, RTP2, RTP3, and RTP4.
  • the display device includes a crack detection line CDS disposed adjacent to at least a portion of an edge of the driving circuit DDV.
  • the crack detection line CDS is electrically connected to the crack detection bumps CDB1, CDB2, and CDB3 included in the driving circuit DDV and the resistance test pads RTP1, RTP2, RTP3, and RTP4 included in the circuit board PCB, so that it is determined whether defects such as cracks have occurred in the area adjacent to the edge of the driving circuit DDV through the resistance test.
  • a defect such as a crack has occurred in the display panel due to the pressure generated in the process of compressing the display panel and the driving circuit DDV, a defect is detected by the crack detection line CDS, so that a display device with improved reliability can be provided.
  • the crack detection line CDS may include detection lines.
  • the crack detection line CDS may include a first detection line CDS-1, a second detection line CDS-2, a third detection line CDS-3, and a fourth detection line CDS- 4.
  • the crack detection line CDS includes a left crack detection line CDS-L and a right crack detection line CDS-R, and each of the left crack detection line CDS-L and the right crack detection line CDS-R may include a first detection line CDS-1, a second detection line CDS-2, a third detection line CDS-3, and a fourth detection line CDS-4.
  • the display panel DP (see FIGS. 5A and 5B ) further includes a crack detection pad CDP electrically connected to an end of the crack detection line CDS disposed on the base layer BL.
  • the display panel DP may be electrically connected to a crack detection bump DMB of the driving circuit DDV through the crack detection pad CDP.
  • the crack detection bump DMB may be arranged to correspond one-to-one with the crack detection pad CDP electrically connected to the crack detection line CDS.
  • the display panel DP may include a pad disposed to correspond to each corresponding bump among the bumps of the driving circuit DDV, and a data line electrically connected to the pad. In an embodiment, as shown in FIG.
  • the crack detection line CDS of an embodiment includes a connection crack detection line CDS-C electrically connecting the left crack detection line CDS-L and the right crack detection line CDS-R.
  • the crack detection line CDS may be disposed adjacent to the entire edge of the driving circuit DDV. Accordingly, in an area adjacent to the entire edge of the driving circuit DDV, it is possible to easily detect whether a crack has occurred in the display panel.
  • first input detection line CDS-11R, the first output detection line CDS-12R, and the second input detection line CDS-21R may be disposed on the second insulating layer IL2.
  • the data lines DL and the crack detection lines CDS electrically connected to the output bumps of the output row are arranged on different layers, and the data lines DL and the crack detection lines CDS electrically connected to the input bumps of the input row may also be disposed on different layers.
  • the crack detection line CDS of an embodiment is disposed on a different layer from the data line DL, the crack detection line CDS may be disposed along the entire edge of the driving circuit DDV without interference between signal lines.
  • the comparison unit CPP may determine that there is a normal wiring state in which no crack (or fine crack) has occurred and the device is in good condition, and in case that the difference between the resistance values measured in the detection lines is outside the second set range, it may be determined as defective in which a crack or the like has occurred.

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EP21167969.1A 2020-07-10 2021-04-13 Dispositif d'affichage et son procédé de fabrication Pending EP3937159A3 (fr)

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US10643511B2 (en) * 2016-08-19 2020-05-05 Apple Inc. Electronic device display with monitoring circuitry
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KR102439673B1 (ko) 2017-06-19 2022-09-05 삼성디스플레이 주식회사 표시 장치
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US11468808B2 (en) 2022-10-11

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