EP3853855B1 - Procédé permettant de programmer un système de mémoire - Google Patents

Procédé permettant de programmer un système de mémoire Download PDF

Info

Publication number
EP3853855B1
EP3853855B1 EP19915722.3A EP19915722A EP3853855B1 EP 3853855 B1 EP3853855 B1 EP 3853855B1 EP 19915722 A EP19915722 A EP 19915722A EP 3853855 B1 EP3853855 B1 EP 3853855B1
Authority
EP
European Patent Office
Prior art keywords
program
mca
memory cell
operations
memory cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
EP19915722.3A
Other languages
German (de)
English (en)
Other versions
EP3853855A4 (fr
EP3853855A1 (fr
Inventor
Haibo Li
Man Lung Mui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yangtze Memory Technologies Co Ltd
Original Assignee
Yangtze Memory Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yangtze Memory Technologies Co Ltd filed Critical Yangtze Memory Technologies Co Ltd
Publication of EP3853855A1 publication Critical patent/EP3853855A1/fr
Publication of EP3853855A4 publication Critical patent/EP3853855A4/fr
Application granted granted Critical
Publication of EP3853855B1 publication Critical patent/EP3853855B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G11C16/3486—Circuits or methods to prevent overprogramming of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5622—Concurrent multilevel programming of more than one cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5624—Concurrent multilevel programming and programming verification

Definitions

  • the present invention is related to a method for programming a memory system, and more particularly, to a method for programming a memory system to reduce the retention error.
  • NAND flash memory is a type of non-volatile storage medium that has been widely used in many fields including notebook, mobile phones, and hard drive.
  • the data stored in NAND flash memory may not always be stable and fixed.
  • the flash memory cells may change and become invalid.
  • the retention error would be even more detrimental when the flash memory cells are multiple-level cells (MLC).
  • MLC multiple-level cells
  • IVS instant (or initial) threshold voltage(Vt) shift
  • a method for programming memory system of a plurality of multiple-level memory cells comprising: performing a plurality of program operations to program the memory cells; wherein a first memory cell is to be programmed by the plurality of program operations to a first programming state lower than a predetermined programming state and a second memory cell is to be programmed by said plurality of program operations to a second programming state higher than or equal to the predetermined programming state; after each of the plurality of program operations, performing at least one threshold voltage test to determine if threshold voltages of the memory cells are greater than at least one verification voltage of a set of verification voltages, said set of verification voltages comprising a first verification voltage corresponding to the first programming state and a second verification voltage corresponding to the second programming state; when a threshold voltage of the first memory cell is determined to be greater than the first verification voltage, inhibiting the first memory cell from being programmed during a next program operation and when a threshold voltage of the second memory cell is determined to newly become greater than the second verification, keeping programming the
  • a method for programming a semiconductor memory device includes: performing a program loop using a blind program operation until the selected cell threshold voltages reach a first verification level; upon detecting a cell having the threshold voltage reaching the first verification level, verifying whether a cell having the threshold voltage reached a second verification level higher than the first verification level; upon verifying a cell having the threshold voltage reaching the second verification level, continuously performing program loops on cells having the first verification level as a target level and on cells having the second verification level as a target level; and upon verifying no cell having the threshold voltage reaching the second verification level, performing a program loop on memory cells having a target level higher than the first verification level, after programming the memory cells having the first verification level as the target level.
  • a method for programming a selected memory cell on a selected word line through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the selected memory cell is inhibited while other memory cells of the selected word line are being programmed. Another program verify operation is performed on the selected memory cell. If the program verify operation fails, a bit line coupled to the selected cell is biased at the step voltage and a final programming pulse is issued to the selected word line. The selected memory cell is then locked from further programming without evaluating the final program verify operation.
  • DE102005009700A1 a method is enclosed involving applying programming pulse and verification voltage to memory cells to verify that each cell has reached a desired state. Read voltage that equals the verification voltage is applied to read data from the cells. The cells that are programmed for highest state are selected. Additional programming pulse is applied to the selected cells without verifying the state of selected cells for enlarging a read margin.
  • a method for programming a memory system of the invention is defined by claim 1 and a memory system of the invention is defined by claim 4.
  • FIG. 1 shows a memory system 100 according to one embodiment of the present invention.
  • the memory system 100 includes a plurality of memory cells MCA(1,1) to MCA(M,N) and a control circuit 110, where M and N are positive integers.
  • the memory system 100 can be a flash memory, such as a NAND type flash memory.
  • N memory cells are coupled to the same corresponding word line.
  • the memory cells MCA(1,1) to MCA(1,N) are coupled to the word line WL1, and the memory cells MCA(M,1) to MCA(M,N) are coupled to the word line WLM. Also, the control circuit 110 is coupled to the word lines WL1 to WLM for controlling the memory cells MCA(M,1) to MCA(M,N) for programming operations.
  • Memory cells coupled to the same word line are programmed at the same time by applying the program voltage through the word line.
  • the memory cells MCA(1,1) to MCA(M,N) are multiple-level cells (MLC), including quad-level cells (QLC) and triple-level cells (TLC). That is, each of the memory cells MCA(1,1) to MCA(M,N) can store data of multiple bit states.
  • MLC multiple-level cells
  • QLC quad-level cells
  • TLC triple-level cells
  • each of the memory cells MCA(1,1) to MCA(M,N) can include a floating gate transistor FT.
  • the gate terminals of the floating gate transistors FT of the memory cells MCA(1,1) to MCA(M,N) can receive a program voltage from the word lines WL1 to WLM, and the first terminals of the floating gate transistors FT of the memory cell MCA(1,1) to MCA(M,N) can receive a reference voltage.
  • the program voltage can be greater than the reference voltage, and thus the high cross voltage between the gate terminals and the first terminals of the floating gate transistors FT will inject electrons to the gate structures of the floating gate transistors FT, increasing the threshold voltage of the floating gate transistors FT.
  • the threshold voltages of the floating gate transistors FT will be raised to the desired levels. Consequently, the state of data stored in the memory cells MCA(1,1) to MCA(M,N) can be identified according to the levels of the threshold voltages of the floating gate transistors FT of the memory cells MCA(1,1) to MCA(M,N).
  • the memory cells MCA(1,1) to MCA(M,N) may be able to store eight different states of data.
  • the threshold voltage of the memory cell MCA(1,1) is smaller than a first verification voltage, then the memory cell MCA(1,1) may be deemed as not being programmed, and the memory cell MCA(1,1) may be deemed as having a first programming state.
  • the threshold voltage of the memory cell MCA(1,1) is greater than the first verification voltage, then the memory cell MCA(1,1) may be deemed as being programmed to have a second programming state.
  • the memory cell MCA(1,1) is kept being programmed to have its threshold voltage being greater than a second verification voltage which is greater than the first verification voltage, then the memory cell MCA(1,1) will be deemed as being programmed to have a third programming state, and so on.
  • the memory cells MCA(1,1) to MCA(M,N) may be able to store more or less states of data, and the states of data may be represented by threshold voltages with different orders according to the application need.
  • the threshold voltages of the memory cells MCA(1,1) to MCA(M,N) may be dropped within a short period of time, which is the so called instant threshold voltage shift (or initial threshold voltage shift).
  • the instant threshold voltage shift may result in the threshold voltages of some of the memory cells MCA(1,1) to MCA(M,N) dropping below the verification voltage, thereby causing the data stored in some of the memory cells MCA(1,1) to MCA(M,N) to fault.
  • FIG. 2 shows a method 200 for operating the memory system 100 according to one embodiment of the present invention.
  • steps S210 to S280 are performed by the control circuit 110. That is the control circuit 110 provides the desired program voltages according to the programming progress.
  • step S210 the program operation is performed to raise the threshold voltages of the memory cells MCA(1,1) to MCA(M,N), and every time after the program operation is performed, at least one threshold voltage test is performed to determine if the threshold voltages of the memory cells MCA(1,1) to MCA(M,N) are greater than at least one verification voltage.
  • a program operation is performed to program the memory cell MCA(1,1) to have the second programming state. In this case, a threshold voltage test corresponding to the second programming state will be performed in step S220.
  • the same program operation may also program the memory cell MCA(1,2) to have the third programming state. In this case, a threshold voltage test corresponding to the third programming state will also be performed in step S220.
  • the memory cell MCA(1,1) is meant to be programmed to have the second programming state and the memory cell MCA(1,1) has passed the threshold voltage test corresponding to the second programming state, then the memory cell MCA(1,1) would be inhibited during the next program operation as shown in step S250. However, if the memory cell MCA(1,1) has not passed the threshold voltage test corresponding to the second programming state, meaning the threshold voltage of the memory cell MCA(1,1) is still smaller than the corresponding verification voltage, then the memory cell MCA(1,1) will be programmed during the next program operation to keep raising its threshold voltage.
  • a reprogramming scheme is applied when a predetermined number of program operations have been performed and a threshold voltage of the memory cell is determined to newly become greater than a verification voltage that is not smaller than the predetermined verification voltage. Namely, for memory cells to be programmed to higher programming states, the additional program operation is applied to further secure the threshold voltage.
  • the predetermined verification voltage can be corresponding to the sixth programming state.
  • the memory cell MCA(1,2) is meant to be programmed to the sixth programming state and has been determined to newly become greater than the verification voltage corresponding to the sixth programming state in step S220, then, instead of being inhibited, the memory cell MCA(1,2) will be programmed again during the next program operation. Therefore, the affection of the instant threshold voltage shift on the memory cell MCA(1,2) is reduced.
  • the additional program operations are performed to memory cells meant to be programmed to higher programming states because the issue of instant threshold voltage shift can become more significant when the threshold voltages of the memory cells become higher. Also, if the additional program operation is added when the memory cells have lower programming states, then the memory cells may be over programmed when they are programmed to have the higher programming states, which may deteriorate the memory cells and cause instability.
  • step 230 the number of program operations performed will be checked before applying the additional program operation for preventing over programming. For example, in some embodiments, before the 18 th program operation, the memory cells passing the threshold voltage tests will always be inhibited during the next program operation as shown in step S250. However, after the 17 th program operation, the additional program operation will be performed to those memory cells that are determined to newly become greater than the verification voltage corresponding to the higher programming states as shown in steps S240 and S242.
  • the memory cell MCA(1,1) If the threshold voltage of the memory cell MCA(1,1) is determined to be greater than the verification voltage corresponding to the first programming state, the memory cell MCA(1,1) will be inhibited during the next program operation as shown in step S250. After the program operations have been performed more than a predetermined number of times, for example but not limited to 17 times, if the threshold voltage of the memory cell MCA(1,2) is determined to newly become greater than the verification voltage corresponding to the sixth programming state, the memory cell MCA(1,2) will be programmed again during the next program operation.
  • step S230 may be omitted, and the additional program operation will be performed to all memory cells that have been determined to newly become greater than the verification voltages corresponding to higher programming states without considering the number of program operations that have been performed.
  • the incremental step pulse programming can be applied to the method 200.
  • a first program pulse may be generated to program the memory cells MCA(1,1) to MCA(M,N) while during a second program operation after the first program operation, a second program pulse may be generated to program the memory cells MCA(1,1) to MCA(M,N).
  • the second program pulse can have a voltage greater than the first program pulse to help to increase the threshold voltages of the memory cells MCA(1,1) to MCA(M,N) in the second program operation.
  • step S260 can be performed to determine if there are more than a target number of memory cells that have not passed the corresponding threshold voltage tests. If there are more than the target number of memory cells that have not passed the corresponding threshold voltage tests, it may imply that the memory system 100 has not been programmed successfully and may need more times of program operation. However, if there are less than the target number of memory cells that have not passed the corresponding threshold voltage tests, it may imply that the memory system 100 has been programmed successfully as concluded in step S280.
  • the total number of the program operations can be limited to be under a maximum number for preventing over programming and endless operations. Therefore, in step S270, if the program operations have been performed for more than the maximum number of times, then the program process will be determined to have failed in step S272. Otherwise, the next program operation will be performed in step S210.
  • the threshold voltages of the memory cells can be steadily secured, and the retention error caused by instant threshold voltage shift can be reduced.
  • FIG. 3 shows a possible method 300 for operating the memory system 100 according to an example which is not part of the present invention and which is present for illustration purpose only, same applies for the description of the examples corresponding to figure 3 .
  • the method 300 can include steps S310 to S380 as shown in FIG. 3 , but is not limited to the order shown in FIG. 3 .
  • steps S310 to S380 can be performed by the control circuit 110. That is the control circuit 110 can provide the desired program voltages according to the programming progress.
  • the verification voltage can be increased to reduce the retention error caused by the instant threshold voltage shift.
  • step S330 will determine if the predetermined number of program operations have been performed. If the program operations have been performed more than the predetermined number of times, for example but not limited to 17 times, then the verification voltages to be tested in following threshold voltage tests will be increased in step S340. That is, to pass the threshold voltage corresponding to a specific programming state, the threshold voltage of the memory cell must be higher than a previous standard level. Consequently, even if the instant threshold voltage shift occurs, the threshold voltage of the memory cell will still be high enough to acquire the desired programming state during the read operation.
  • the programming state of the threshold voltage test will be checked in step S332.
  • the threshold voltage test corresponding to a target programming state for example but not limited to the sixth programming state
  • the verification voltages to be tested in following threshold voltage tests will be increased in step 5340. Therefore, memory cells that are meant to be programmed to higher programming states and are more difficult to be programmed will be tested more strictly during the program process to prevent the instant threshold voltage shift from causing retention errors.
  • One of the reasons for not increasing the verification voltages in the very beginning of the program process is to protect the memory cells MCA(1,1) to MCA(M,N) from being over programmed.
  • one of the steps S330 and S332 may be omitted if the condition of the memory system 100 allows.
  • the memory system and the methods for programming the memory systems perform additional program operations to memory cells that have newly passed the threshold voltage tests Therefore, the memory cells are programmed to have threshold voltages greater than the verification voltages used in the read operation with sufficient headroom, preventing the retention errors caused by the instant threshold voltage shift and securing the reading

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Claims (6)

  1. Procédé permettant de programmer un système de mémoire (100), le système de mémoire (100) comprenant une pluralité de cellules de mémoire (MCA(1,1)...MCA(M,N)), dans lequel la pluralité de cellules de mémoire comprend une première cellule de mémoire et une deuxième cellule de mémoire, dans lequel la pluralité de cellules de mémoire sont des cellules à niveaux multiples (MLC), le procédé comprenant:
    l'exécution d'une pluralité d'opérations de programme pour programmer la pluralité de cellules de mémoire (MCA(1,1)...MCA(M,N)); la première cellule de mémoire doit être programmée par la pluralité d'opérations de programme à un premier état de programmation inférieur à un état de programmation prédéterminé et la deuxième cellule de mémoire doit être programmée par la pluralité d'opérations de programme à un deuxième état de programmation supérieur ou égal à l'état de programmation prédéterminé,
    après chaque opération de programme de la pluralité d'opérations de programme:
    - effectuer au moins un test de tension de seuil (S220) pour déterminer si les tensions de seuil de la pluralité de cellules de mémoire (MCA(1,1)...(MCA(M,N)) sont supérieures à au moins une tension de vérification d'un ensemble de tensions de vérification, l'ensemble de tensions de vérification comprenant une première tension de vérification correspondant au premier état de programmation et une deuxième tension de vérification correspondant au deuxième état de programmation;
    - déterminer si le nombre d'opérations de programmation effectuées de la pluralité d'opérations de programme a atteint un nombre prédéterminé;
    - si une tension de seuil de la première cellule de mémoire (MCA(1,1)) est déterminée comme étant supérieure à la première tension de vérification, inhiber la programmation de la première cellule de mémoire (MCA(1,1)) pendant l'opération de programmation suivante correspondante de la pluralité d'opérations de programme (S250);
    - si le nombre d'opérations de programmation effectuées n'a pas atteint le nombre prédéterminé et si une tension de seuil de la deuxième cellule de mémoire (MCA(1,2)) est déterminée comme étant supérieure à la deuxième tension de vérification, inhiber la programmation de la deuxième cellule de mémoire pendant l'opération de programme suivante correspondante de la pluralité d'opérations de programme (S250);
    - en réponse à une tension de seuil de la deuxième cellule de mémoire (MCA(1,2)) déterminée comme étant nouvellement supérieure à la deuxième tension de vérification et à la détermination que le nombre d'opérations de programmation effectuées de la pluralité d'opérations de programme est égal ou supérieur au nombre prédéterminé, maintenir la programmation de la deuxième cellule de mémoire (MCA(1,2)) pendant l'opération de programme suivante de la pluralité d'opérations de programme (S242).
  2. Procédé selon la revendication 1, comprenant en outre:
    lorsqu'il y a plus d'un nombre cible de cellules de mémoire qui n'ont pas passé les tests de tension de seuil correspondants, exécuter l'opération de programme suivante correspondante de la pluralité d'opérations de programme.
  3. Procédé selon la revendication 1 ou 2, comprenant en outre:
    au cours d'une première opération de programme de la pluralité d'opérations de programme, générer une première impulsion de programme pour programmer la pluralité de cellules de mémoire (MCA(1,1)...MCA(M,N)); et au cours d'une deuxième opération de programme de la pluralité d'opérations de programme après la première opération de programme, générer une deuxième impulsion de programme pour programmer la pluralité de cellules de mémoire (MCA(1,1)...MCA(M,N));
    la deuxième impulsion de programme ayant une tension supérieure à la première impulsion de programme.
  4. Système de mémoire (100) comprenant
    une pluralité de cellules de mémoire (MCA(1,1)...MCA(1,N) couplées à au moins une ligne de mot (WL1), dans lequel la pluralité de cellules de mémoire comprend une première cellule de mémoire et une deuxième cellule de mémoire, dans lequel la pluralité de cellules de mémoire sont des cellules à niveaux multiples (MLC); et
    un circuit de commande (110) couplé à au moins une ligne de mot (WL1), et configuré pour:
    - effectuer une pluralité d'opérations de programme pour programmer la pluralité de cellules de mémoire (MCA(1,1)...MCA(1,N) en fournissant des tensions de programme à travers au moins une ligne de mot (WL1), dans lequel le circuit de commande (110) est configuré pour programmer la première cellule de mémoire par la pluralité d'opérations de programme à un premier état de programmation inférieur à un état de programmation prédéterminé et pour programmer la deuxième cellule de mémoire par la pluralité d'opérations de programme à un deuxième état de programmation supérieur ou égal à l'état de programmation prédéterminé;
    le circuit de commande étant en outre configuré pour, après chaque opération de programme de la pluralité d'opérations de programme:
    - effectuer au moins un test de tension de seuil (S220) pour déterminer si les tensions de seuil de la pluralité de cellules de mémoire (MCA(1,1)...MC(1,N) sont supérieures à ladite au moins une tension de vérification d'un ensemble de vérification, l'ensemble de tensions de vérification comprenant une première tension de vérification correspondant au premier état de programmation et une deuxième tension de vérification correspondant au deuxième état de programmation;
    - déterminer si le nombre d'opérations de programmation effectuées de la pluralité d'opérations de programmation a atteint un nombre prédéterminé;
    - inhiber la programmation de la première cellule de mémoire (MCA(1,1)) pendant les opérations de programmation suivantes correspondantes de la pluralité d'opérations de programmation si une tension de seuil de la première cellule de mémoire (MCA(1,1)) est déterminée comme étant supérieure à la première tension de vérification; et
    - inhiber la programmation de la deuxième cellule de mémoire pendant l'opération de programme suivante correspondante de la pluralité d'opérations de programme (S250) si le nombre d'opérations de programmation effectuées n'a pas atteint le nombre prédéterminé et si une tension de seuil de la deuxième cellule de mémoire (MCA(1,2)) est déterminée comme étant supérieure à la deuxième tension de vérification; et
    - continuer à programmer la deuxième cellule de mémoire (MCA(1,2)) pendant l'opération de programme suivante correspondante en réponse à une tension de seuil de la deuxième cellule de mémoire (MCA(1,2)) déterminée comme devenant nouvellement supérieure à une deuxième tension de vérification et au nombre d'opérations de programmation effectuées de la pluralité d'opérations de programme déterminé comme étant égal ou supérieur au nombre prédéterminé.
  5. Système de mémoire (100) selon la revendication 4, dans lequel le circuit de commande (110) est en outre configuré pour effectuer une opération de programme suivante de la pluralité d'opérations de programme s'il y a plus qu'un nombre cible de cellules de mémoire de la pluralité de cellules de mémoire qui n'ont pas passé les tests de tension de seuil correspondants.
  6. Système de mémoire (100) selon la revendication 4 ou 5, en outre configuré pour:
    générer une première impulsion de programme pour programmer la pluralité de cellules de mémoire (MCA(1,1)...MCA(1,N)) au cours d'une première opération de programme de la pluralité d'opérations de programme; et
    générer une deuxième impulsion de programme pour programmer la pluralité de cellules de mémoire (MCA(1,1)...MCA(1,N)) au cours d'une deuxième opération de programme de la pluralité d'opérations de programme après la première opération de programme;
    la deuxième impulsion de programme ayant une tension supérieure à la première impulsion de programme.
EP19915722.3A 2019-02-20 2019-02-20 Procédé permettant de programmer un système de mémoire Active EP3853855B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/075549 WO2020168478A1 (fr) 2019-02-20 2019-02-20 Procédé permettant de programmer un système de mémoire

Publications (3)

Publication Number Publication Date
EP3853855A1 EP3853855A1 (fr) 2021-07-28
EP3853855A4 EP3853855A4 (fr) 2022-04-27
EP3853855B1 true EP3853855B1 (fr) 2023-07-12

Family

ID=67243936

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19915722.3A Active EP3853855B1 (fr) 2019-02-20 2019-02-20 Procédé permettant de programmer un système de mémoire

Country Status (7)

Country Link
US (3) US11037642B2 (fr)
EP (1) EP3853855B1 (fr)
JP (3) JP7148727B2 (fr)
KR (1) KR20210066899A (fr)
CN (1) CN110036446A (fr)
TW (1) TWI702608B (fr)
WO (1) WO2020168478A1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210066899A (ko) * 2019-02-20 2021-06-07 양쯔 메모리 테크놀로지스 씨오., 엘티디. 메모리 시스템을 프로그래밍하기 위한 방법
CN110970082B (zh) * 2019-11-29 2022-03-15 深圳大普微电子科技有限公司 降低闪存滞留错误的方法、装置及固态硬盘
CN113228186B (zh) * 2021-03-29 2023-09-29 长江存储科技有限责任公司 多遍编程中的负栅极应力操作机器存储器件
CN114913906A (zh) * 2021-06-17 2022-08-16 长江存储科技有限责任公司 存储器系统及其编程方法
US11790994B2 (en) * 2021-09-22 2023-10-17 Western Digital Technologies, Inc. Non-volatile memory with reverse state program
CN114400035A (zh) * 2021-12-02 2022-04-26 长江存储科技有限责任公司 存储器的编程方法、存储器及存储系统
CN116547759A (zh) 2021-12-02 2023-08-04 长江存储科技有限责任公司 存储器设备、存储器系统及其程序操作方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005009700A1 (de) * 2004-02-26 2005-09-22 Samsung Electronics Co., Ltd., Suwon Programmier-und Betriebsverfahren sowie Lesetoleranzeinstellverfahren für Speicherzellen und nichtflüchtiger Speicher

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990066130A (ko) * 1998-01-21 1999-08-16 윤종용 불 휘발성 메모리 장치 및 그것의 프로그램 방법
KR100721012B1 (ko) * 2005-07-12 2007-05-22 삼성전자주식회사 낸드 플래시 메모리 장치 및 그것의 프로그램 방법
KR100851853B1 (ko) * 2006-11-22 2008-08-13 삼성전자주식회사 플래시 메모리 장치 및 그것의 프로그램 및 프로그램 검증방법
US7548462B2 (en) 2007-06-29 2009-06-16 Macronix International Co., Ltd. Double programming methods of a multi-level-cell nonvolatile memory
ITRM20080114A1 (it) 2008-02-29 2009-09-01 Micron Technology Inc Compensazione della perdita di carica durante la programmazione di un dispositivo di memoria.
KR101506655B1 (ko) * 2008-05-15 2015-03-30 삼성전자주식회사 메모리 장치 및 메모리 데이터 오류 관리 방법
US8223555B2 (en) 2009-05-07 2012-07-17 Micron Technology, Inc. Multiple level program verify in a memory device
US8248850B2 (en) * 2010-01-28 2012-08-21 Sandisk Technologies Inc. Data recovery for non-volatile memory based on count of data state-specific fails
US20150348633A1 (en) * 2010-02-11 2015-12-03 Samsung Electronics Co., Ltd. Nonvolatile memory devices and methods of programming nonvolatile memory devices
KR101676816B1 (ko) * 2010-02-11 2016-11-18 삼성전자주식회사 플래시 메모리 장치 및 그것의 프로그램 방법
US8208310B2 (en) 2010-05-04 2012-06-26 Sandisk Technologies Inc. Mitigating channel coupling effects during sensing of non-volatile storage elements
US8493792B2 (en) * 2010-12-02 2013-07-23 Hynix Semiconductor Inc. Programming method of non-volatile memory device
KR101211840B1 (ko) 2010-12-30 2012-12-12 에스케이하이닉스 주식회사 반도체 메모리 장치의 프로그램 방법
KR101855169B1 (ko) * 2011-10-13 2018-05-09 삼성전자주식회사 불휘발성 메모리 장치, 불휘발성 메모리 장치의 프로그램 방법, 불휘발성 메모리 장치를 포함하는 메모리 시스템
KR101942863B1 (ko) * 2012-06-19 2019-01-28 삼성전자주식회사 불휘발성 메모리 장치 및 그것의 프로그램 방법
KR102083450B1 (ko) * 2012-12-05 2020-03-02 삼성전자주식회사 페이지 버퍼를 포함하는 불휘발성 메모리 장치 및 그것의 동작 방법
KR20140088386A (ko) * 2013-01-02 2014-07-10 에스케이하이닉스 주식회사 반도체 장치 및 이의 동작 방법
US8929142B2 (en) 2013-02-05 2015-01-06 Sandisk Technologies Inc. Programming select gate transistors and memory cells using dynamic verify level
KR102112596B1 (ko) * 2013-03-15 2020-05-19 삼성전자주식회사 비휘발성 메모리 장치 및 이의 프로그래밍 방법
KR102175039B1 (ko) * 2013-06-25 2020-11-05 삼성전자주식회사 불휘발성 메모리 장치의 데이터 기입 방법
KR102118979B1 (ko) * 2013-09-13 2020-06-05 삼성전자주식회사 불휘발성 메모리 장치 및 그것의 프로그램 방법
KR102285994B1 (ko) 2014-05-13 2021-08-06 삼성전자주식회사 불휘발성 메모리 시스템 및 메모리 컨트롤러의 동작 방법
KR102290448B1 (ko) * 2014-09-04 2021-08-19 삼성전자주식회사 불휘발성 메모리 및 불휘발성 메모리의 동작 방법
KR20160047667A (ko) 2014-10-22 2016-05-03 삼성전자주식회사 불휘발성 메모리 장치 및 그것의 프로그램 방법
KR102396053B1 (ko) * 2015-04-20 2022-05-10 삼성전자주식회사 비휘발성 메모리 장치 및 그것의 동작 방법
KR102274280B1 (ko) 2015-06-22 2021-07-07 삼성전자주식회사 불휘발성 메모리 장치의 동작 방법
KR102470606B1 (ko) * 2015-11-26 2022-11-28 삼성전자주식회사 불휘발성 메모리 장치 및 불휘발성 메모리 장치를 포함하는 스토리지 장치
KR102432483B1 (ko) * 2015-12-31 2022-08-12 에스케이하이닉스 주식회사 데이터 저장 장치 및 이의 구동 방법
CN107633865B (zh) * 2016-07-19 2024-02-20 兆易创新科技集团股份有限公司 一种非易失性存储器的数据读取装置及方法
JP6652470B2 (ja) * 2016-09-07 2020-02-26 キオクシア株式会社 半導体記憶装置
KR102565888B1 (ko) * 2016-09-12 2023-08-11 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그것의 동작 방법
CN107689245B (zh) * 2017-08-31 2019-02-22 长江存储科技有限责任公司 一种nand闪存装置的编程方法
TWI635499B (zh) * 2017-09-11 2018-09-11 旺宏電子股份有限公司 編程非揮發性記憶體的方法及記憶體系統
JP2020038738A (ja) * 2018-09-03 2020-03-12 キオクシア株式会社 不揮発性メモリ及びメモリシステム
KR20210066899A (ko) * 2019-02-20 2021-06-07 양쯔 메모리 테크놀로지스 씨오., 엘티디. 메모리 시스템을 프로그래밍하기 위한 방법

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005009700A1 (de) * 2004-02-26 2005-09-22 Samsung Electronics Co., Ltd., Suwon Programmier-und Betriebsverfahren sowie Lesetoleranzeinstellverfahren für Speicherzellen und nichtflüchtiger Speicher

Also Published As

Publication number Publication date
KR20210066899A (ko) 2021-06-07
EP3853855A4 (fr) 2022-04-27
CN110036446A (zh) 2019-07-19
WO2020168478A1 (fr) 2020-08-27
US12033708B2 (en) 2024-07-09
US11386970B2 (en) 2022-07-12
JP2022511447A (ja) 2022-01-31
TWI702608B (zh) 2020-08-21
TW202032572A (zh) 2020-09-01
US20200342947A1 (en) 2020-10-29
JP7148727B2 (ja) 2022-10-05
US20210264995A1 (en) 2021-08-26
JP7414921B2 (ja) 2024-01-16
JP2022171971A (ja) 2022-11-11
US20200265904A1 (en) 2020-08-20
JP2024019722A (ja) 2024-02-09
EP3853855A1 (fr) 2021-07-28
US11037642B2 (en) 2021-06-15

Similar Documents

Publication Publication Date Title
EP3853855B1 (fr) Procédé permettant de programmer un système de mémoire
JP2008027511A (ja) 半導体記憶装置およびその制御方法
US10998062B2 (en) Method for programming a memory system
KR100673025B1 (ko) 고온 스트레스로 인한 읽기 마진의 감소를 보상할 수 있는플래시 메모리의 프로그램 방법
JP6115740B1 (ja) 半導体記憶装置
US10796777B1 (en) Method for programming in non-volatile memory device by applying multiple bitline bias voltages
CN110431633B (zh) 非易失性存储器器件和用于通过施加多个位线偏置电压在非易失性存储器器件中编程的方法
KR20130072517A (ko) 불휘발성 메모리 장치 및 이의 소거 방법
US10811111B1 (en) Non-volatile memory device and method for programming in non-volatile memory device by applying multiple bitline bias voltages
KR101184830B1 (ko) 반도체 메모리 장치 및 이의 동작 방법
US7274595B2 (en) Nonvolatile memory device for storing data and method for erasing or programming the same
KR20090105605A (ko) 불휘발성 메모리 장치의 패스 전압 설정 방법 및 프로그램방법
US11119854B2 (en) Method of controlling verification operations for error correction of non-volatile memory device, and non-volatile memory device
CN110827904A (zh) 存储器装置及其编程方法

Legal Events

Date Code Title Description
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE

PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20210420

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

REG Reference to a national code

Ref country code: DE

Ref legal event code: R079

Ref document number: 602019032822

Country of ref document: DE

Free format text: PREVIOUS MAIN CLASS: G11C0016100000

Ipc: G11C0011560000

Ref country code: DE

Ref legal event code: R079

Free format text: PREVIOUS MAIN CLASS: G11C0016100000

Ipc: G11C0011560000

A4 Supplementary search report drawn up and despatched

Effective date: 20220328

RIC1 Information provided on ipc code assigned before grant

Ipc: G11C 16/34 20060101ALI20220322BHEP

Ipc: G11C 11/56 20060101AFI20220322BHEP

DAV Request for validation of the european patent (deleted)
DAX Request for extension of the european patent (deleted)
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

17Q First examination report despatched

Effective date: 20220729

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

INTG Intention to grant announced

Effective date: 20230202

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE PATENT HAS BEEN GRANTED

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

P01 Opt-out of the competence of the unified patent court (upc) registered

Effective date: 20230527

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602019032822

Country of ref document: DE

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG9D

REG Reference to a national code

Ref country code: NL

Ref legal event code: MP

Effective date: 20230712

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 1587998

Country of ref document: AT

Kind code of ref document: T

Effective date: 20230712

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230712

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231013

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230712

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231112

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230712

Ref country code: RS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230712

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231113

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231012

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230712

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230712

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231112

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230712

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231013

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230712

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230712

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230712

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230712

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602019032822

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SM

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230712

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230712

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230712

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230712

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230712

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230712

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20240216

Year of fee payment: 6

Ref country code: GB

Payment date: 20240118

Year of fee payment: 6

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230712

26N No opposition filed

Effective date: 20240415

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230712

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230712

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20240220