Classifications

• • C—CHEMISTRY; METALLURGY
  • C30—CRYSTAL GROWTH
  • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
  • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
  • C30B23/02—Epitaxial-layer growth
  • C30B23/025—Epitaxial-layer growth characterised by the substrate
• • C—CHEMISTRY; METALLURGY
  • C30—CRYSTAL GROWTH
  • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
  • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
  • C30B25/02—Epitaxial-layer growth
  • C30B25/18—Epitaxial-layer growth characterised by the substrate
  • C30B25/183—Epitaxial-layer growth characterised by the substrate being provided with a buffer layer, e.g. a lattice matching layer
• • C—CHEMISTRY; METALLURGY
  • C30—CRYSTAL GROWTH
  • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
  • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
  • C30B29/10—Inorganic compounds or compositions
  • C30B29/16—Oxides
  • C30B29/22—Complex oxides
• • C—CHEMISTRY; METALLURGY
  • C30—CRYSTAL GROWTH
  • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
  • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
  • C30B33/06—Joining of crystals
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
  • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N30/00—Piezoelectric or electrostrictive devices
  • H10N30/01—Manufacture or treatment
  • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
  • H10N30/074—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing
  • H10N30/079—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing using intermediate layers, e.g. for growth control
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N30/00—Piezoelectric or electrostrictive devices
  • H10N30/704—Piezoelectric or electrostrictive devices based on piezoelectric or electrostrictive films or coatings
  • H10N30/706—Piezoelectric or electrostrictive devices based on piezoelectric or electrostrictive films or coatings characterised by the underlying bases, e.g. substrates
  • H10N30/708—Intermediate layers, e.g. barrier, adhesion or growth control buffer layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N30/00—Piezoelectric or electrostrictive devices
  • H10N30/80—Constructional details
  • H10N30/85—Piezoelectric or electrostrictive active materials
  • H10N30/853—Ceramic compositions
  • H10N30/8548—Lead-based oxides
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N30/00—Piezoelectric or electrostrictive devices
  • H10N30/80—Constructional details
  • H10N30/85—Piezoelectric or electrostrictive active materials
  • H10N30/853—Ceramic compositions
  • H10N30/8548—Lead-based oxides
  • H10N30/8554—Lead-zirconium titanate [PZT] based

Definitions

• the present invention relates to a method of manufacturing a crystalline layer of Titano-Lead Zirconate (PZT) material and a substrate for the epitaxial growth of such a crystalline layer of PZT material.
• PZT Titano-Lead Zirconate
• Some materials are not currently available as a crystalline substrate and even less as a large diameter wafer monocrystalline substrate. And some materials are possibly available in large diameter but not according to certain characteristics or specifications in terms of quality, particularly vis-à-vis the density of defects or the electrical or optical properties required.
• the present invention aims to overcome these limitations of the state of the art by proposing a method of manufacturing a crystalline layer of PZT material, preferably a monocrystalline layer of PZT material, and a substrate for growth by epitaxial growth of such a crystalline layer of PZT material, preferably of such a monocrystalline layer of PZT material.
• a method for producing a crystalline layer of PZT material comprising the transfer of a monocrystalline seed layer of SrTiO 3 material to a support substrate of silicon material followed by an epitaxial growth of the crystalline layer of PZT material. .
• the crystalline layer of PZT material is monocrystalline.
• the monocrystalline seed layer has a thickness of less than 10 ⁇ m, preferably less than 2 ⁇ m, and more preferably less than 0.2 ⁇ m.
• the transfer of the monocrystalline seed layer of SrTiO 3 material to the silicon material support substrate comprises a step of assembling a monocrystalline substrate of SrTiO 3 material on the support substrate followed by a step of thinning said monocrystalline substrate of SrTiO 3 material.
• the thinning step comprises the formation of an embrittlement zone delimiting a portion of the monocrystalline substrate of SrTiO 3 material intended to be transferred onto the support substrate of silicon material.
• the formation of the embrittlement zone is obtained by implantation of atomic and / or ionic species.
• the thinning step comprises a detachment at the level of the weakening zone so as to transfer said portion of the monocrystalline substrate of SrTiO 3 material to the support substrate of silicon material, in particular the detachment comprises the application of a thermal and / or mechanical stress.
• the assembly step is a molecular adhesion step.
• the monocrystalline seed layer of SrTiO 3 material is in the form of a plurality of blocks each transferred to the silicon material support substrate.
• the silicon material support substrate comprises a removable interface configured to be disassembled by laser peeling and / or chemical etching and / or mechanical biasing.
• the invention also relates to a substrate for growth by epitaxy of a crystalline layer of P2T material characterized in that it comprises a monocrystalline seed layer of SrTiO 3 material on a support substrate of silicon material.
• the crystalline layer of PZT material is monocrystalline.
• the monocrystalline seed layer of SrTiO 3 material is in the form of a plurality of blocks.
• the silicon material support substrate comprises a removable interface configured to be disassembled by laser peeling and / or chemical etching and / or mechanical biasing.
• the invention also relates to a method for manufacturing a crystalline layer of material comprising PMN-PT and / or PZN-PT having a mesh parameter close to that of the PZT material comprising the transfer of a monocrystalline seed layer of SrTiO 3 material. on a support substrate of silicon material followed by growth by epitaxy of the crystalline layer of PMN-PT or PZN-PT material.
• the invention also relates to a method of manufacturing a crystalline layer of material comprising PMN-PT and / or PZN-PT having a mesh parameter close to that of the PZT material comprising the transfer of a monocrystalline seed layer of YSZ material or Ce0 2 or MgO or Al 2 0 3 on a support substrate of silicon material followed by growth by epitaxy of the crystalline layer of PMN-PT or PZN-PT material.
• the invention also relates to a substrate for growth by epitaxy of a crystalline layer of material comprising PMN-PT and / or PZN-PT having a mesh parameter close to that of the PZT material, characterized in that it comprises a monocrystalline seed layer of material SrTi0 3 or YSZ or Ce0 2 or MgO or Al 2 0 3 on a support substrate of silicon, sapphire, Ni or Cu material.
• FIG. 1 illustrates a method of manufacturing a crystalline layer of PZT material according to one embodiment of the invention as well as a substrate for the epitaxial growth of such a crystalline layer of PZT material according to this embodiment. of the invention
• FIG. 2 illustrates a method of manufacturing a crystalline layer of PZT material according to another embodiment of the invention as well as a substrate for the epitaxial growth of such a crystalline layer of PZT material according to this other mode. embodiment of the invention
• FIG. 3 illustrates a method of manufacturing a crystalline layer of PZT material according to yet another embodiment of the invention as well as a substrate for the epitaxial growth of such a crystalline layer of PZT material according to this other embodiment of the invention;
• FIG. 4 illustrates a method of manufacturing a crystalline layer of PZT material according to yet another embodiment of the invention as well as a substrate for the epitaxial growth of such a crystalline layer of PZT material according to this other embodiment of the invention;
• FIG. 5 illustrates a method of manufacturing a crystalline layer of PZT material according to yet another embodiment of the invention as well as a substrate for the epitaxial growth of such a crystalline layer of PZT material according to this other embodiment of the invention;
• the different layers are not necessarily represented on the scale.
• FIG. 1 illustrates a support substrate 100 of silicon material onto which a monocrystalline seed layer 200 of SrTiO 3 material is transferred.
• Other materials of the monocrystalline seed layer 200 may be envisaged, such as YSZ, CeO 2 , MgO or Al 2 O 3 , the latter having a mesh parameter close to that of the PZT material.
• the support substrate 100 of silicon material may also be replaced by a support substrate 100 of sapphire, Ni or Cu material.
• the use of silicon has the advantage of opening the field of application of the layers of PZT material not only to large equipment type 300 mm but also to make compatible the microelectronics industry for which the requirements in terms of acceptance on the production line of exotic material other than silicon, in particular PZT, are high.
• the assembly step T of the monocrystalline seed layer 200 of SrTiO 3 material on the support substrate 100 of silicon material is preferentially done by a molecular adhesion step.
• This molecular adhesion step comprises a bonding step, preferably at ambient temperature, and is followed by a consolidation annealing of the bonding interface which is usually carried out at elevated temperatures up to 900 ° C. or even 1100 ° C. C for a period of minutes to hours.
• the assembly step T of the monocrystalline seed layer on the support substrate is also preferentially done by a molecular adhesion step using typical conditions of the same order of magnitude as mentioned above. -above.
• the assembly step 1 'of the monocrystalline seed layer on the support substrate is replaced by a step of deposition of the Ni or Cu material on the monocrystalline seed layer, for example via electrodeposition or electroforming (electroplating (ECD) according to the English terminology).
• ECD electroforming
• This technique usually includes the use of tie layer and stripping and is known per se and will not be described in more detail here.
• FIG. 1 schematically represents the assembly step 1 'of a monocrystalline substrate 20 of SrTiO 3 material on the support substrate 100 of silicon material. It follows a thinning step 2 'of the monocrystalline substrate 20 of SrTiO 3 material after being assembled on the support substrate 100 of silicon material.
• FIG. 1 schematically represents the thinning step 2 'which can be implemented for example by chemical and / or mechanical etching (polishing, grinding, milling, etc.).
• the monocrystalline seed layer 200 of SrTiC 3 material which will serve as a monocrystalline seed of a 3 'growth stage by epitaxial growth of the crystalline layer 300 of PZT material made on the substrate for epitaxial growth of a layer.
• crystalline material PZT 10 shown schematically in Figure 1.
• Those skilled in the art would be able to adjust the parameters used for epitaxial growth of a crystalline layer of PZT material usually used during homoepitaxy or heteroepitaxy on a bulk crystalline substrate in order to optimize the 3 'growth step by epitaxy. of the crystalline layer 300 of PZT material made on the substrate for epitaxial growth of a crystalline layer of PZT material 10 of the present invention.
• the epitaxial growth of the PZT material is by cathodic sputtering (sputtering in English terminology), for example by magnetron sputtering, known to those skilled in the art.
• sol-gel process including a low temperature deposition followed by different annealing at temperatures between 350 ° C and 650 ° C or 700 ° C, the growth by epitaxy by MOCVD to usual temperatures of about 550 ° C in using precursors known to those skilled in the art.
• the presence of the monocrystalline seed layer makes it possible to favorably influence the crystalline quality of the crystalline layer of PZT material.
• a monocrystalline layer of PZT material can be obtained.
• the present invention is moreover not limited to an epitaxy of the PZT material but extends to certain piezoelectric crystals of the perovskite type such as PMN-PT or PZN-PT having a mesh parameter close to that of the PZT material. .
• the thermal expansion coefficient of the support substrate 100 predominates the thermal behavior of the substrate for epitaxial growth of a crystalline layer of PZT material 10 during the 3 'growth step by epitaxy of the crystalline layer 300. of PZT material. This is due to the thin thickness, preferably less than 1 ⁇ m, of the monocrystalline seed layer 200 of SrTiO 3 material relative to the total thickness of the substrate for epitaxial growth of a crystalline layer of PZT material which is of the order of several tens to hundreds of pm.
• the SrTiO 3 material is moreover chosen to provide a monocrystalline seed layer having a mesh parameter as close as possible to the mesh parameter chosen for the crystalline layer 300 of PZT material, preferably the mesh parameter in the relaxed state in order to allow epitaxial growth inducing the least possible defects in the crystalline layer 300 of PZT material.
• the material of the support substrate 100 advantageously also has a thermal expansion coefficient that is particularly close to the thermal expansion coefficient of the PZT material for the same reasons of reducing defects in the crystalline layer 300 obtained by epitaxy.
• a support substrate 100 of sapphire material for the present invention would be used.
• FIG. 2 diagrammatically represents an embodiment of the method for manufacturing a crystalline layer of PZT material that differs from the embodiment described with reference to FIG. 1 in that the substrate 20 'monocrystalline material SrTi0 3 undergoes a step 0' implantation of atomic and / or ionic species to form an embrittlement zone delimiting a portion 200 'of the single crystal substrate 20' of SrTiO3 material intended to be transferred to the substrate support 100 'of silicon material, and in that the thinning step 2' comprises a detachment at this weakening zone so as to transfer said portion 200 'of the single crystal substrate 20' of SrTiO 3 material to the support substrate 100 'of silicon material, in particular this detachment comprises the application of a thermal and / or mechanical stress.
• the advantage of this embodiment is thus to be able to recover the remaining portion 201 of the monocrystalline substrate 20 'of SrTiO 3 starting material that can be used again to undergo the same process again and thus reduce costs.
• the substrate for epitaxial growth of a crystalline layer of PZT material 10 'thus illustrated in FIG. 2 serves for the growth step 3 "of the crystalline layer 300' of PZT material as already described during the process described in connection with Figure 1.
• the implantation step 0 is done with hydrogen ions.
• An interesting alternative well known to those skilled in the art is to replace all or part of the hydrogen ions with helium ions.
• a hydrogen implantation dose will typically be between 6x10 16 cm 2 and 1 x 10 17 cm 2 .
• the implantation energy will typically be between 50 to 170 keV.
• the detachment is typically at temperatures between 300 and 600 ° C. Thicknesses of the monocrystalline seed layer of the order of 200 nm to 1.5 ⁇ m are thus obtained.
• additional technological steps are advantageously added in order either to reinforce the bonding interface, or to recover a good roughness, or to heal the defects possibly generated during the implantation step or else to prepare the seed layer surface for resumption of epitaxy. These steps are, for example, polishing, chemical etching (wet or dry), annealing, chemical cleaning. They can be used alone or in combination that those skilled in the art can adjust.
• FIG. 3 differs from the embodiments described with reference to FIG. 1 and FIG. 2 in that the substrate for epitaxial growth of a crystalline layer of PZT material (10, 10 ') comprises a demountable interface 40' configured to to be dismantled.
• a support substrate 100 of silicon material it may be a rough surface, for example silicon material assembled with the monocrystalline seed layer during the assembly step. Or a rough interface may be present within the support substrate 100 of silicon material, the latter for example obtained by assembling two silicon wafers.
• Another embodiment would be to introduce at the level of the face to be assembled with the monocrystalline seed layer a porous silicon layer capable of fracturing during the application of a mechanical and / or thermal stress, for example by insertion of a plate edge blade known to those skilled in the art or by the application of annealing.
• this interface is chosen so as to withstand the other mechanical and / or thermal stresses undergone during the process of the present invention (eg detachment, growth by epitaxy, etc.).
• a sapphire material support substrate it may be a stack of silicon oxide, silicon nitride and silicon oxide (so-called ONO type structure) made on the face of the sapphire to assemble with the monocrystalline seed layer.
• FIG. 4 schematically represents an embodiment of the process for manufacturing a crystalline layer of PZT material that differs from the embodiments described with reference to FIG. 1, FIG. 2 and FIG. 3 in that the seed layer Monocrystalline 2000 'SrTiO3 material is in the form of a plurality of blocks (200T, 2002', 2003 ') each transferred to the support substrate 100 "of silicon material.
• the different pavers can be in any form (square, hexagonal, strips, ...) and with different sizes ranging from a few mm 2 to several cm 2 .
• the spacing between the chips may also vary significantly depending on whether a maximum density of coverage is sought (in this case preferentially a spacing of less than 0.2 mm will be chosen) or, on the contrary, maximum dissemination of the blocks within the substrate ( in this case the spacing may be several millimeters and even centimeters).
• a maximum density of coverage in this case preferentially a spacing of less than 0.2 mm will be chosen
• maximum dissemination of the blocks within the substrate in this case the spacing may be several millimeters and even centimeters.
• the skilled person could apply the transfer he wants and is not limited to a particular method. Thus one could consider applying the technical information described in connection with the method illustrated schematically in Figure 1 or the technical information described in connection with the method illustrated schematically in Figure 2, see even a combination of both.
• the latter may simply be a silicon substrate, but it may also be an SOI type substrate comprising a silicon oxide layer separating a silicon substrate from a thin layer of silicon.
• access to the support substrate can be done simply by lithography and etching known to those skilled in the art.
• FIG. 5 schematically represents an embodiment that differs from the embodiment described with reference to FIG. 4 in that the support substrate 100 "as well as subsequently the substrate for growth by epitaxy of a crystalline layer of PZT material 10 "comprises a demountable interface 40 configured to be disassembled, for example by a laser lift off technique and / or chemical etching and / or mechanical biasing.
• substrate 100 "as already mentioned in connection with FIG 3.
• An example would be the use of a support substrate 100 of the SOI type comprising a silicon oxide layer separating a silicon substrate from a thin layer of silicon.
• the oxide layer could be used as a demountable interface 40 by selective etching of this oxide layer, for example by immersion in a hydrofluoric acid (HF) bath.
• HF hydrofluoric acid
• the chemical etching removal of a buried layer is particularly advantageous when it comes in combination with the treatment of a plurality of small substrates.
• the radius of action of the under-engraving is generally limited to a few centimeters or even a few millimeters if it is desired to maintain conditions and processing times that are industrially reasonable.
• the treatment of a plurality of small substrates allows the start of several chemical etching fronts thanks to possible access of the buried layer between each block, and no longer only on the extreme edges of the substrates which can be up to 300mm in diameter. In the case of an SOI support substrate it is thus possible to partially remove the thin layer of silicon between the blocks to allow the start of several etching fronts.
• the thin silicon layer having a predetermined thickness (which can vary between 5 nm and 600 nm, or even thicker depending on the intended application) could thus be used to form microelectronic components and thus enable the co-integration of components with base of PZT materials in the same substrate.
• the removable interface is not necessarily located inside the support substrate but may also be at the interface with the seed material layer SrTiC> 3 assembled on this support substrate (for example a stack a layer of silicon nitride between two silicon oxide layers allows a laser detachment, particularly suitable for a sapphire-type support substrate) as already described in connection with FIG.

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