Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
  • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
  • H01L23/367—Cooling facilitated by shape of device
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
  • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
  • H01L23/427—Cooling by change of state, e.g. use of heat pipes
• • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
  • F28—HEAT EXCHANGE IN GENERAL
  • F28D—HEAT-EXCHANGE APPARATUS, NOT PROVIDED FOR IN ANOTHER SUBCLASS, IN WHICH THE HEAT-EXCHANGE MEDIA DO NOT COME INTO DIRECT CONTACT
  • F28D15/00—Heat-exchange apparatus with the intermediate heat-transfer medium in closed tubes passing into or through the conduit walls ; Heat-exchange apparatus employing intermediate heat-transfer medium or bodies
  • F28D15/02—Heat-exchange apparatus with the intermediate heat-transfer medium in closed tubes passing into or through the conduit walls ; Heat-exchange apparatus employing intermediate heat-transfer medium or bodies in which the medium condenses and evaporates, e.g. heat pipes
  • F28D15/04—Heat-exchange apparatus with the intermediate heat-transfer medium in closed tubes passing into or through the conduit walls ; Heat-exchange apparatus employing intermediate heat-transfer medium or bodies in which the medium condenses and evaporates, e.g. heat pipes with tubes having a capillary structure
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
  • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
  • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
  • H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
  • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
  • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
  • H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
  • H01L2023/4037—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws characterised by thermal path or place of attachment of heatsink
  • H01L2023/4068—Heatconductors between device and heatsink, e.g. compliant heat-spreaders, heat-conducting bands
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
  • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/42—Wire connectors; Manufacturing methods related thereto
  • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
  • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
  • H01L2224/4805—Shape
  • H01L2224/4809—Loop shape
  • H01L2224/48091—Arched
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
  • H01L2224/732—Location after the connecting process
  • H01L2224/73251—Location after the connecting process on different surfaces
  • H01L2224/73253—Bump and layer connectors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
  • H01L2924/181—Encapsulation

Definitions

• the invention generally relates to the field of power electronics. More particularly, the invention relates to an electronic power module with a 3D architecture for the arrangement of power switching electronic chips. The invention also relates to electric power converters such as inverters.
• the power modules are constructed with a planar arrangement of the electronic chips.
• the rear faces of the chips are fixed on a substrate and interconnection wires, so-called “bonding wires", are used to establish electrical connections on the front faces of the chips.
• the substrate for example, in the form of a ceramic coated with copper plates, performs a thermal interface function with a cooling device and an electrical insulation function.
• This traditional planar architecture is not optimized in terms of compactness and cost and has other disadvantages.
• the cooling of the chips intervenes only by one of their faces.
• the parasitic inductances, introduced in particular by the bonding wires and the electrical connection strips generate overvoltages which increase the heat released and which are potentially destructive.
• parasitic inductances oppose higher switching frequencies, while these are favorable to compactness, especially in power converters.
• the 3D stack of chips is a promising way to improve the compactness of power modules and reduce parasitic inductances.
• An increased level of integration is generally conducive to cost reduction as well.
• the 3D architecture accentuates the thermal stresses on the components.
• US20160005675A1 there is disclosed a power module with a 3D architecture.
• This power module is shown here in FIG. 1 and marked 100.
• the module 100 is cooled by its high and low faces.
• the high and low faces respectively comprise high heat sinks 106 and low 1 10.
• the 3D stack of the module 1 00 comprises a high electronic chip 220, a low electronic chip 210 and an intermediate interconnection substrate 212 sandwiched between the chips 220 and 221.
• the chips 220 and 210 are respectively welded to the dissipators 106 and 1 10 by one of their faces and the intermediate interconnection substrate 212 by another of their face.
• An overmolding resin 108 provides sealing and mechanical cohesion of the module.
• the intermediate interconnection substrate 212 is here a DCB (Direct Copper Bond) or DBA (Direct Bonded Aluminum) type substrate which comprises a central dielectric plate 215 coated on both sides. metal layers 216 and 217, copper (DCB) or aluminum (DBA).
• the central dielectric plate 215 is a ceramic or a polyimide such as Kapton (trademark).
• the 3D stack made in the power module 100 of the prior art allows more compactness. However, electronic chips 210 and 220 are cooled only through one side. Such an arrangement may prove to be insufficient to guarantee, at acceptable costs, good reliability at high power, by maintaining the junction temperatures of the electronic chips below critical values. [009] It is desirable to provide an improved power module of the 3D stack type of the electronic chips and having an architecture that guarantees efficient cooling.
• the invention relates to an electronic power module having a 3D stack architecture, comprising first and second dielectric substrates intended to come into thermal contact with first and second heat sinks respectively, at least one pair first and second stacked power switching electronic chips and a common intermediate substrate, the first and second power switching chips being sandwiched respectively between the first dielectric substrate and the common intermediate substrate and between the common intermediate substrate and the second dielectric substrate.
• the common intermediate substrate is a one-piece metallic element and comprises a central portion for the implantation of power switching electronic chips and at least one thermal conduction portion in thermal contact with the first dielectric substrate and / or the second dielectric substrate.
• the term "electronic power switching chip” used in the present application means any semiconductor power component operating in a switching manner such as a transistor, diode or other components.
• the common intermediate substrate has an H-shaped section and comprises two lateral thermal conduction portions on either side of the central portion, the lateral thermal conduction portions being in thermal contact. with the first and second dielectric substrates.
• the common intermediate substrate comprises at least one heat pipe, of capillary or pulsed type, which is arranged to ensure heat transfer from the central portion to the lateral thermal conduction portions.
• the common intermediate substrate comprises a coolant circulation coil which is arranged to ensure a heat transfer from the common intermediate substrate to an external heat exchanger.
• first electrode faces of the first and second power switching electronic chips are soldered directly on corresponding faces of the common intermediate substrate.
• second electrode faces of the first and second power switching electronic chips are respectively welded to first and second metal electrical connection plates, the first and second metal electrical connection plates being respectively fixed against the first and second dielectric substrates.
• the power electronic module comprises at least a third power switching electronic chip having a difference in height with at least one of the first and second power switching electronic chips, and the common intermediate substrate and / or at least one of the first and second metal electrical connection plates comprise at least one difference in thickness difference compensation for the implantation of the power switching electronic chips.
• the power electronic module comprises semisphere-shaped posts on which are welded power switching electronic chips.
• the common intermediate substrate and the first and second metal electrical connection plates are copper or aluminum.
• the invention also relates to a power converter comprising at least one power electronic module as briefly described above.
• FIG. is a sectional view of an electronic power module of the prior art, with a 3D stack architecture
• Fig.2 shows a circuit diagram of a transistor bridge branch, with IGBT transistors
• Figs.3 and 4 are simplified sectional views showing a first embodiment of an electronic power module according to the present invention
• Fig.5 is a top view showing an implantation of power switching electronic chips in a common intermediate substrate included in the power electronic module of Figs.3 and 4
• Fig.6A to 6C are top views, in section, showing three embodiments of the common intermediate substrate of Fig.5 incorporating capillary-type, pulsed heat pipes and a heat transfer fluid coil, respectively
• Fig.7 is a simplified sectional view showing a second embodiment of an electronic power module according to the present invention
• FIG.7 is a simplified sectional view showing a second embodiment of an electronic power module according to the present invention
• FIG. 8 is a top view showing an implantation of poles in the shape of a half-sphere for welding the electronic chips switching of power in a common intermediate substrate included in the electronic power module of Fig.7;
• Fig.9 shows a circuit diagram of an electric power converter in the form of a three-phase inverter, with IGBT transistors;
• Figs. 10 and 11 show two embodiments of the three-phase inverter of Fig. 9, respectively with a horizontal arrangement and a vertical arrangement of the power modules according to the invention.
• a power module in the form of a bridge branch, or half bridge, switching transistor.
• a bridge branch constitutes an electrical power converter in the form of a single-phase inverter.
• These modules can be associated to form complete switching bridges such as polyphase inverters, or be connected in parallel to pass the desired current.
• An electrical diagram of such a PM power module, with IGBT type transistors, is shown in Fig.2.
• the PM power module comprises a high IGBT transistor, identified ITHS, and a low IGBT transistor, identified ITLS, respectively said transistor "low side” and transistor “high side” in English.
• IDHS and IDLS diodes called “freewheeling", are respectively associated with the ITHS and ITLS transistors.
• the IDHS diode, IDLS is mounted between the collector electrode CHS, CLS, and the emitter electrode EHS, ELS, of the transistor ITHS, ITLS, respectively.
• the collector electrode CHS of the transistor ITHS is connected to a positive DC voltage + DC and the emitter electrode ELS of the transistor ITLS is connected to a negative DC voltage -DC.
• the ITHS and ITLS transistors are switched-controlled through their respective gate electrodes GHS and GLS.
• the output OUT of the PM module corresponds to the point of interconnection of the emitter electrodes EHS and collector CLS of the ITHS and ITLS transistors and delivers an alternating voltage.
• the transistors ITHS and ITLS and their associated diodes IDHS and IDLS are separate chips. It will be noted that in certain configurations, the diodes associated with the transistors will already be integrated in the chips of the transistors, so that their implantation will not be necessary. It will also be noted that the power module according to the invention can be made equally well with other power switches, such as MOSFET transistors or GTO thyristors.
• the PM1 power module is formed with a 3D stack of electronic chips ITHS, IDHS, and ITLS, IDLS.
• the power module PM1 comprises a high part PHS and a low part PLS in which are arranged the transistor ITHS and its associated diode IDHS and the transistor ITLS and its associated diode IDLS, respectively.
• the high parts PHS and low PLS share a common intermediate substrate SC.
• the high part PHS essentially comprises a so-called “high” SH dielectric substrate, a so-called “high” PH electrical connection plate and a first "high” DH heat sink.
• the low part PLS essentially comprises a so-called “low” dielectric substrate SL, a so-called “low” electrical connection plate PL and a second so-called “low” heat sink DL.
• the dielectric substrates SH and SL are typically ceramic substrates.
• the metal electrical connection plates PH and PL are typically copper plates for the electrical connection of the electronic chips.
• the substrate SH, SL comprises a first face SHi, SLi, against which is fixed the heat sink DH, DL, and a second face SH2, SL2, against which is fixed the metal plate PH, PL.
• Techniques known to those skilled in the art are used to make the fasteners of heatsinks and metal plates on high and low dielectric substrates with very good thermal conductivity.
• the common intermediate substrate SC is a one-piece metal element, which must be an excellent electrical and thermal conductor.
• the common intermediate substrate SC is copper.
• the common intermediate substrate SC has an H-shaped cross-section and comprises a central portion SCc and two lateral portions of thermal conduction SCL and SCR which are perpendicular to the central portion SCc and located on either side of the central portion SCc.
• the central portion SCc is dedicated to the implementation of electronic chips.
• the lateral portions SCL and SCR, here called “left” and “right”, are dedicated to the transfer of heat from the central portion SCc to the dissipators DH and DL.
• the chips ITHS and IDHS are located in the upper part PHS of the PM1 module.
• Fig. 5 shows the implantation of the chips ITHS and IDHS on the common intermediate substrate SC.
• the collector electrode (CHS, FIG. 2) of the transistor ITHS and the cathode electrode of the diode IDHS are soldered to the high metal plate PH.
• the emitter electrode (EHS, FIG. 2) of the ITHS transistor and the anode electrode of the IDHS diode are soldered on a high face SCci of the central portion SCc of the common intermediate substrate SC.
• welded or "solder” used for the description of the invention must be interpreted broadly and cover various techniques for producing electrical connections with material input used in power electronics, such as stirring, sinter brazing and other techniques.
• the chips ITLS and IDLS are located in the lower part PLS of the PM1 module.
• the emitter electrode (ELS, Fig. 2) of the transistor ITLS and the anode electrode of the IDLS diode are soldered to the low metal plate PL.
• the collector electrode (CLS, FIG. 2) of the transistor ITLS and the cathode electrode of the diode IDLS are soldered on a low face SCc2 of the central portion SCc of the common intermediate substrate SC.
• the gate electrodes GHS, GLS, ITHS transistors, ITLS, (not shown in FIG. 3) are typically connected to copper connection patterns supported by the SH, SL dielectric substrates.
• Fig.4 which is a view along the sectional plane AA (Fig.3), the metal plates PH, PL and the central portion SCc extend outside the PM1 module to form electrical connection tabs, for DC + DC, -DC, and OUT.
• the thermal conduction side portions SCL, SCR, of the common intermediate substrate SC, dedicated to the evacuation of heat comprise high and low faces which are fixed to the high dielectric substrates and low SH, SL. More precisely, for the left lateral portion SCL, a high face SCu thereof is fixed to the second face SH2 of the high dielectric substrate SH and a lower face SCi_2 is fixed to the second face SL2 of the low dielectric substrate SL. For the right side portion SCR, a high face SCRI thereof is attached to the second face SH2 of the high dielectric substrate SH and a bottom face SCR2 is fixed to the second face SL2 of the low dielectric substrate SL.
• the technique used to carry out the fixing of the lateral portions of thermal conduction SCL, SCR, to the dielectric substrates SH, SL, will be chosen to guarantee a very good thermal conductivity. Thanks to the common intermediate substrate SC, with its lateral portions of thermal conduction SCL, SCR, in thermal conduction with the heatsinks DH, DL, the invention allows a true double-sided cooling of the electronic chips in a 3D stack architecture.
• the evacuation of the calories generated by the PM1 module is as follows:
• the upper faces of the ITHS transistor and the IDHS diode dissipate calories through the top heatsink DH.
• FIGS. 6A to 6C show three alternative embodiments SC1, SC2 and SC3 of the common intermediate substrate which allow an increase in the quantity of calories evacuated by this substrate.
• Figs.6A-6C are views according to the sectional plane BB shown in Fig.4.
• the common intermediate substrates SC1 and SC2, shown in FIGS. 6A and 6B, incorporate heat pipes CA1 L, CA1 R, and CA2L, CA2R, in their copper body, so as to increase their thermal conductivity and evacuate more heat. calories. The temperature of the electronic chips can thus be reduced.
• the heat pipes CA1 L, CA1 R, of the substrate SC1 are of capillary type.
• the heat pipes CA2L, CA2R, of the substrate SC2 are of the pulsed type.
• the micro-channels heat pipes are made by techniques known to those skilled in the art that will not be detailed here.
• the calories are removed from the central portion of the common intermediate substrates SC1, SC2, to the side portions of thermal conduction SCL, SCR, which lead them to to the dissipators DH, DL.
• the transfer of calories is effected through the evaporation-condensation cycle of the coolant contained in the heat pipes.
• the heat pipes may have small dimensions because a large part of the calories is discharged directly to the two heatsinks DH, DS, by the copper mass of the common intermediate substrate, without going through the heat pipes.
• This arrangement makes it possible to obtain a power module with good mechanical rigidity, despite the presence of the micro-channels of the heat pipes.
• the heat pipes are replaced by a liquid coolant circulation coil CAL to be connected to an external heat exchanger (not shown).
• This variant embodiment is suitable for example for very high powers. Referring to Figs.7 and 8, there is now described a second particular embodiment PM2 of the power module according to the invention. Of course, the variants with heat pipe or coil described above also apply to this embodiment.
• the architecture of the PM2 power module is suitable when chips having different thicknesses are integrated in the module, for example, different thicknesses between the transistor chips and the diode chips.
• shims In the state of the art, it is usually uses shims to compensate for a difference in thickness between the chips. These shims require to be welded on two sides, namely, one face on the copper plane of the support (substrate or copper plate) and another on the chip.
• the introduction of wedges decreases the thermal conductivity between the chips and heat sinks and increases the joules losses, because of the additional solder layers necessary for their attachment to the supports.
• the differences in thickness between the chips are compensated by introducing localized unevenness on the supports.
• the PM2 power module which comprises IDHS diode chips, IDLS, having a thickness less than that of the transistor chips ITHS, ITLS, differences in elevations D1 and D2 are introduced into the common intermediate substrate SC4 and the metal plate PL1. , respectively.
• the elevations D1, D2 are located here in the soldering zones of the diode chips and compensate for the lower thickness of the diode chips. It is thus avoided the introduction of shims and, correlatively, additional solder layers.
• MT and MD units comprising PT poles in the shape of a half-sphere are made on the substrate.
• SC4 and PL1 metal plate common intermediate SC4 and PL1 metal plate.
• the MT patterns are made in the solder area of the transistors and the MD patterns are made in the solder area of the diodes.
• the poles in the shape of a half-sphere provide better adhesion of the connection of the chips to their supports, vis-à-vis the thermomechanical stresses.
• elevations D1, D2 and the MT, MD patterns with the poles PT in the shape of a half-sphere will be made for example by etching the SC4 supports PL1.
• the metallized faces of the chips ITHS and IDHS are soldered directly on the metal plate PH (corresponding to the voltage + DC), whereas their opposite faces are welded to the half-spheres PT etched on the common intermediate substrate SC4, typically by means of solder by sintering.
• metallized faces of the chips ITLS and IDLS are soldered directly on the common intermediate substrate SC4, while their opposite faces are welded on the half-spheres PT etched on the metal plate PL1 (corresponding to the voltage-DC), typically by means of solder by sintering.
• FIG.9 to 1 there are now described two embodiments of an electric power converter in the form of a three-phase inverter obtained by combining three power modules according to the invention.
• the invention applies generally to the production of an inverter having any number of phases.
• the electrical diagram of the three-phase inverter, marked OT, is shown in Fig.9. It comprises three power modules PMA, PMB and PMc associated in parallel and each forming a switching branch of the inverter OT.
• a first embodiment shown in FIG. 10 is obtained by arranging the power modules horizontally.
• the high metal plates PH power modules PMA, PMB and PMc are attached to a heat sink common DHc PHS high part through a common dielectric substrate SHc typically ceramic.
• the low metal plates PL1 of the modules are fixed to a common heat sink DLc PLS low part through a common dielectric substrate SLc typically ceramic.
• Insulating dielectric walls IS, typically made of ceramic, are provided to electrically insulate the lateral sections of thermal conduction facing common substrates SC4.
• the electrical connections between the modules for obtaining the inverter are made with external connections (not shown), which may be integrated in certain applications.
• a second embodiment shown in FIG. 1 is obtained by placing the power modules vertically.
• intermediate heat sinks D and D are shared between the lower part PLS of the PMA module and the upper part PHS of the PMB module and between the lower part PLS of the module PMB and the upper part PHS of the module PMc.
• the electrical connections between the modules for obtaining the inverter are made with external connections, which may possibly be integrated in some applications.
• the metal electrical connection plates and / or the common intermediate substrate can be made of aluminum, instead of copper.
• it will be used to different techniques well mastered by those skilled in the art to achieve a power module according to the invention.
• techniques such as etching, mechanical material removal by machining, laser or plasma cutting, forging, molding or copper or aluminum.
• the invention is not limited to the particular embodiments which have been described here by way of example. Those skilled in the art, according to the applications of the invention, may make various modifications and variations which fall within the scope of the appended claims.

Applications Claiming Priority (2)

Publications (1)

Family

ID=60302156

Family Applications (1)

Country Status (5)

Families Citing this family (6)

Family Cites Families (9)

• 2017
  • 2017-04-13 FR FR1753254A patent/FR3065319B1/fr active Active
• 2018
  • 2018-04-09 EP EP18723901.7A patent/EP3610503A1/fr not_active Withdrawn
  • 2018-04-09 CN CN201880025047.XA patent/CN110506330B/zh active Active
  • 2018-04-09 WO PCT/FR2018/050883 patent/WO2018189468A1/fr unknown
  • 2018-04-09 US US16/604,524 patent/US10714406B2/en active Active

Also Published As

Similar Documents

Legal Events