GB2613794A

GB2613794A - Power semiconductor module

Info

Publication number: GB2613794A
Application number: GB2118061.7A
Authority: GB
Inventors: Li Yun; Ma Yaqing; Li Jianfeng; Yu Jun; Zhao Zhenglong; Du Yuekang; Dong Fangfang
Original assignee: Zhuzhou CRRC Times Electric Co Ltd
Current assignee: Zhuzhou CRRC Times Electric Co Ltd
Priority date: 2021-12-14
Filing date: 2021-12-14
Publication date: 2023-06-21
Also published as: GB202118061D0; WO2023109604A2; WO2023109604A3

Abstract

A power semiconductor integrated circuit module 100 comprises first (Fig. 2: 110) and second (Fig. 2: 120) half-bridge switches arranged between opposing first and second substrates and electrically connected in parallel between DC positive 15 and negative 14/16 power input terminals. The first half-bridge switch comprises a first high side device (Fig. 2: 112), a first low side device (Fig. 2: 116) and a first output terminal (AC1) 13 10, and the second half-bridge switch comprises a second high side device (Fig. 2: 122), a second low side device (Fig. 2: 126) and a second output terminal (AC2) 12. The first substrate comprises a first insulating layer 20 with a first patterned conductive layer 201-215 arranged on the surface facing the half-bridge switches; the second substrate comprises a second insulating layer (Fig. 8: 30) with a second patterned conductive layer (Fig. 8: 301-303) arranged on a surface facing the half-bridge switches. The first patterned conductive layer comprises a first conductive track (Fig. 7: 205 which electrically connects high side terminals of the first and second high side devices to the DC positive power terminal; and the second patterned conductive layer comprises a second conductive track (Fig. 8: 301) which electrically connects, via conductive shims, low side terminals of the first and second low side devices to the DC negative power terminal. The module may comprise one phase of an IGBT-based 3-phase dual inverter circuit in electric/hybrid vehicle (EV/HEV) applications, the two AC outputs driving a generator motor and a traction motor. Plural power modules may be stacked between coolers to form a stack unit. Slots (Fig. 9: 310, 320) in the conductive tracks (Fig. 9: 301-303) allow control of the current flow, enabling a parasitic inductance of commutation loops to be reduced.

Description

Power Semiconductor Module

Technical Field

The present disclosure relates to a power semiconductor module and a method for manufacturing the same. More particularly, but not exclusively, the present disclosure relates to a power semiconductor module which integrates two or more half-bridge switches in a single package for multi-inverter applications.

Background

Power semiconductor modules have been considered as one of the most delicate components in electric drive systems of electric vehicles (EVs) and hybrid electric vehicles (HEVs). For such applications, there has been an increasing demand for power semiconductor modules with increased power density, improved electrical performance and thermal performance, high reliability and reduced costs. The following known solutions have been provided in response to this demand.

EP 2 178 117 Al discloses a power semiconductor module which comprises multiple IGBT devices. The disclosed structure of EP 2 178 117 Al utilises one heat sink to perform double side cooling. In particular, the IGBT devices are soldered on separated first metallization parts of an insulating substrate, and a cooling member covering top sides of the IGBT devices is soldered on a second metallization part of the substrate. Therefore, the operational heat of the IGBT devices can be transferred from the top side over the cooling member to the substrate.

EP 2 533 284 A2 discloses a power semiconductor package with double-sided cooling. In particular, the package is a three-phase inverter module which comprises high side devices and low side devices of three half-bridge switches. These devices are attached on direct bonded copper (DBC) substrate and their top sides are interconnected with conductive clips for facilitating the double-sided cooling. A bottom side of a heat sink is directly mounted under the DBC substrate with a layer of thermal interface material. A top side of the heat sink is placed also with a layer of thermal interface material over a cap layer or another DBC substrate which is mounted on the conductive clips. The double-sided heat sink reduces the size and improves the cooling performance and power density of the module.

US 2011/0241198 Al discloses a power semiconductor module with a two-metal (such as aluminium and cooper) laminated conductor. The aluminium side of the conductor forms a straight section and can be ultrasonically welded on a top side of a semiconductor device. The copper side of the conductor forms an arch-like protrusion and acts as a stress release structure when it is soldered on an electrode which is coupled to a cooling device. A bottom side of the semiconductor device is soldered on another electrode which is coupled to a further cooling device. Therefore, the two-metal laminated conductor is used to save the costs needed for providing solderable metallization on the top side of the semiconductor device and improving the reliability of the power module where both the bottom and top sides of the semiconductor device are connected to cooling devices.

The known solutions focus upon directly improving the thermal performance of the power modules. Consequently, the power density and electrical performance of the power modules would be indirectly improved. Further, in the aforementioned prior art, each of the modules comprises either single switch, a half-bridge switch or three phase half-bridge switches, and each single switch or half-bridge switch owns its independent structural and conductive paths and power terminals.

It is generally desirable to further improve the power density, the electrical and thermal performances as well as the reliability of power semiconductor modules in EV and HEV electric drive applications. It is an object of the present disclosure, among others, to provide such an improved power semiconductor module.

Summary

According to a first aspect of the present disclosure, there is provided a power semiconductor module, comprising: a first substrate and a second substrate arranged at opposite sides of the power semiconductor module; a first half-bridge switch and a second half-bridge switch arranged between the first substrate and the second substrate, wherein the first half-bridge switch and the second half-bridge switch are electrically connected in parallel between a DC positive power terminal and a DC negative power terminal of the power semiconductor module, and wherein the first half-bridge switch comprises a first high side device, a first low side device and a first output terminal connected therebetween, and wherein the second half-bridge switch comprises a second high side device, a second low side device and a second output terminal connected therebetween; wherein: the first substrate comprises a first insulating layer and a first patterned conductive layer arranged on a surface of the first insulating layer which faces the half-bridge switches; the second substrate comprises a second insulating layer and a second patterned conductive layer arranged on a surface of the second insulating layer which faces the half-bridge switches; the first patterned conductive layer comprises a first conductive track which electrically connects high side terminals of the first and second high side devices to the DC positive power terminal; and the second patterned conductive layer comprises a second conductive track which electrically connects low side terminals of the first and second low side devices to the DC negative power terminal.

Advantageously, the power semiconductor module has integrated the first and second half-bridge switches which share the first and second conductive tracks of the opposing substrates and also share the DC positive and DC negative power terminals. The shared conductive tracks and power terminals lead to not only reduced volume and weight (thus improved power density) of the power semiconductor module but also simplified connections to an external DC power supply. The layout of the shared power terminals may be easily optimised so as to reduce the parasitic inductance and resistance parameters of commutation loops of the half-bridge switches, thereby improving the electrical performance of the power semiconductor module. The opposing first and second substrates allow double side cooling to be provided and hence improve the thermal performance of the power semiconductor module.

At least one of the first and second conductive tracks may be a single continuous conductive track. It would be understood that the term "continuous" means that the conductive track is not broken into more than one isolated track.

The term "electrically connected" used in the present disclosure encompasses both direct connections and indirect connections (where further electrically conductive element(s) are placed between the two connected elements).

At least one of the first and second conductive tracks may comprise a slot.

The slot may be configured to affect a characteristic of a power current flow path through at least one of the devices that is electrically connected to the respective conductive track.

The slot may be configured to impede a current flow through the power current flow path. It would be understood that by the expression "impede a current flow", it is meant that the slot is positioned to increase an inductance and/or a resistance of the power current flow path.

Advantageously, the slot is useful to balance the performances (e.g., wiring inductances and/or wiring resistances) of commutation loops of the half-bridge switches, thereby improving the switching performance of the power semiconductor module.

It would be understood that the "devices" refer to the first and second high side devices and the first and second low side devices.

Each of the high side devices and the low side devices may comprise at least one power transistor.

The slot may partially surround the at least one of the devices. It would be appreciated that "partially surround" means that the slot extends around up to three sides of the at least one of the devices.

Alternatively, the slot may partially surround one or more of the power transistor(s) of the at least one of the devices.

A width of the slot may be as narrow as possible, such as, not greater than about 3mm.

Advantageously, a narrow slot allows the conductive track to maintain its electrical continuity as well as thermal conductance. The term "width" of a slot means a width measured perpendicularly to a longitudinal direction of the slot or to a centre line of the slot.

The term "about" or "approximately" used in the present disclosure indicate a degree of variability (e.g., 20%) in the stated numerical values.

The at least one of the devices may comprise two or more power transistors which are connected in parallel to one another, and the slot is configured to affect a characteristic of a power current flow path through at least one but not all of the two or more power transistors.

The slot may be configured to impede a current flow through the power current flow path.

Advantageously, the slot is useful to improve the current distribution between the power transistors connected in parallel, thereby improving the switching performance of the power semiconductor module.

The characteristic may comprise an inductance of the power current flow path. The characteristic may further comprise a resistance of the power current flow path.

The first patterned conductive layer may comprise: a third conductive track which electrically connects a high side terminal of the first low side device to the first output terminal; and a fourth conductive track which electrically connects a high side terminal of the second low side device to the second output terminal.

The second patterned conductive layer may comprise: a fifth conductive track which electrically connects a low side terminal of the first high side device to the first output terminal; and a sixth conductive track which electrically connects a low side terminal of the second high side device to the second output terminal.

The first substrate may comprise a plurality of separated substrates which support the first, third and fourth conductive tracks respectively.

Alternatively, the second substrate may comprise a plurality of separated substrates which support the second, fifth and sixth conductive tracks respectively.

At least one of the third to sixth conductive tracks may comprise a slot.

The features and characteristics of the slot of the first and second conductive tracks similarly apply to the slot of the third to sixth conductive tracks.

The power semiconductor module may further comprise: a first conductive shim extending between the first and second substrates and electrically connecting the third conductive track to the fifth conductive track; and a second conductive shim extending between the first and second substrates and electrically connecting the fourth conductive track to the sixth conductive track.

Advantageously, the conductive shims are able to carry a high level of current, and thus are useful for improving the electrical performance and the reliability of the power semiconductor module.

The power semiconductor module may further comprise: conductive shims extending between at least some of the devices and the second substrate and electrically connecting low side terminals of the respective devices to the corresponding conductive tracks of the second patterned conductive layer; and/or conductive shims extending between at least some of the devices and the first substrate and electrically connecting high side terminals of the respective devices to the corresponding conductive tracks of the first patterned conductive layer.

The conductive shims are useful for replacing wire bonds as the topside interconnection of the semiconductor chips, and have an improved ability of carrying higher current.

The conductive shims may be made of a material with a coefficient of thermal expansion which matches the coefficients of thermal expansion of the devices and/or the substrates.

Advantageously, matching coefficients of thermal expansion mitigate or eliminate the stress and strain developments in the joints between the conductive shims and the devices and in the joints between the conductive shims and the respective substrate. Accordingly, the thermo-mechanical reliability of the power semiconductor module is improved.

One of the DC positive power terminal and the DC negative power terminal may comprise two or more first power terminals which are electrically connected to one another. The other of the DC positive power terminal and the DC negative power terminal may comprise one or more second power terminals which are electrically connected to one another. The two or more first power terminals and the one or more second power terminals may be arranged in an alternating manner.

Having more than one positive/negative power terminal achieves local anti-parallel current flows and allows the power current flowing into/from that terminal to branch into multiple paths, thereby effectively reducing the parasitic inductance of the commutation loops of the half-bridge switches and improving the switching performance of the first and second half-bridge switches.

The power semiconductor module may further comprise an encapsulant encapsulating the first half-bridge switch and the second half-bridge switch. The encapsulant may comprise a moulding compound.

As compared to a conventional technique which uses a plastic housing and silicone gel as the encapsulant, using the moulding compound as the encapsulant reduces the volume of the power semiconductor module and ensures sufficient insulating and creepage distances between the conductive tracks and between the terminals of the power semiconductor module with smaller or similar dimensions or volumes. Further, the moulding compound provides additional mechanical support to the power semiconductor module, and hence improves the structural strength and thermo-mechanical reliability of the power semiconductor module.

The moulding compound may comprise thermally conductive fillers.

One or more of the first and second insulating layers may be made of an electrically insulating and thermally conductive material.

The power semiconductor module may further comprise a first heat removal body thermally coupled to the first insulating layer, and a second heat removal body thermally coupled to the second insulating layer.

One or more of the first and second heat removal bodies may comprise a heat sink.

The term "thermally coupled" used in the present disclosure means that one or more intervening elements may be connected between the coupled elements.

The DC positive power terminal and the DC negative power terminal may be arranged at a first side of the power semiconductor module. The first and second output terminals may be arranged at a second side of the power semiconductor module. Control terminals of the first and second half-bridge switches may be arranged at a third side of the power semiconductor module. No terminals may be arranged at a fourth side of the power semiconductor module. The first to fourth sides of the power semiconductor module may be defined by a boundary of the first and/or the second substrate.

The control terminals may be configured to control ON/OFF statuses of power transistors of the devices.

Advantageously, having a fourth side where no terminals are arranged facilitates the installation of heat sinks where inlets and outlets of the heat sinks may be arranged at the fourth side of the power semiconductor module.

One or more of the first and second substrates may comprise a silicon nitride based active brazed metal substrate.

Advantageously, silicon nitride based ABM substrates have high mechanical strength and can withstand high mechanical stresses for sealing or mounting the double side heat sinks and have good thermo-mechanical reliability. Thus, silicon nitride based ABM substrates can be used for high performance and high reliability applications The first half-bridge switch may be part of a generator inverter of an electric vehicle or a hybrid electric vehicle electric drive system, and the second half-bridge switch may be part of a motor inverter of the electric vehicle or the hybrid electric vehicle electric drive system.

According to a second aspect of the present disclosure, there is provided an electric drive system for an electric vehicle or a hybrid electric vehicle, comprising: at least three power semiconductor modules each of which being according to the first aspect; wherein: the first half-bridge switches of the at least three power semiconductor modules collectively form a generator inverter for driving a first electric motor; and the second half-bridge switches of the at least three power semiconductor modules collectively form a motor inverter for driving a second electric motor.

According to a third aspect of the present disclosure, there is provided an electric vehicle comprising an electric drive system according to the second aspect.

According to a fourth aspect of the present disclosure, there is provided a hybrid electric vehicle comprising an electric drive system according to the second aspect.

According to a fifth aspect of the present disclosure, there is provided a stack unit, comprising: a plurality of power semiconductor modules, at least some of which being according to the first aspect; and a plurality of coolers stacked with the power semiconductor modules along a stacking direction, wherein each of the power semiconductor modules is thermally coupled to at least one of the coolers.

According to a sixth aspect of the present disclosure, there is provided a method of manufacturing a power semiconductor module, comprising: attaching a first half-bridge switch and a second half-bridge switch between opposing first and second substrates, wherein the first substrate comprises a first insulating layer and a first patterned conductive layer arranged on a surface of the first insulating layer which faces the half-bridge switches, and the second substrate comprises a second insulating layer and a second patterned conductive layer arranged on a surface of the second insulating layer which faces the half-bridge switches, and wherein the attaching comprises: electrically connecting a high side terminal of a first high side device of the first half-bridge switch and a high side terminal of a second high side device of the second half-bridge switch to a first conductive track of the first patterned conductive layer; electrically connecting the first conductive track to a DC positive power terminal of the power semiconductor module; electrically connecting a low side terminal of a first low side device of the first half-bridge switch and a low side terminal of a second low side device of the second half-bridge switch to a second conductive track of the second patterned conductive layer; electrically connecting the second conductive track to a DC negative power terminal of the power semiconductor module; and electrically connecting the first half-bridge switch and the second half-bridge switch in parallel between the DC positive power terminal and the DC negative power terminal; and encapsulating the first half-bridge switch and the second half-bridge switch by an encapsulant.

Where appropriate any of the features described above in relation to one aspect of the present disclosure may be applied to any other aspect of the disclosure.

It would also be understood that the terms "first", "second"..."sixth" are simply used in the present disclosure to label the relevant elements for the ease of description, and do not imply any limitations to the sequence or locations of the relevant elements.

Brief Description of the Drawings

In order that the disclosure may be more fully understood, a number of embodiments of the disclosure will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 schematically illustrates a circuit diagram of an electric control system for use in EV and HEV applications; Figure 2 schematically illustrates a circuit diagram of a power semiconductor module according to an embodiment of the present disclosure; Figure 3 schematically illustrates a top perspective view of a power semiconductor module according to an embodiment of the present disclosure which implements the circuit diagram of Figure 2; Figure 4 schematically illustrates a bottom perspective view of the power semiconductor module of Figure 3; Figure 5 schematically illustrates a side view of the power semiconductor module of Figure 3; Figure 6 schematically illustrates a top perspective view of the power semiconductor module of Figure 3 with an encapsulant and a top substrate being invisible; Figure 7 schematically illustrates a plan view of the power semiconductor module of Figure 6; Figure 8 schematically illustrates a bottom perspective view of the top substrate of the power semiconductor module of Figure 3; Figure 9 schematically illustrates a plan view of the top substrate of Figure 8; Figure 10 schematically illustrates a spatial relationship between a patterned conductive layer on the bottom of the top substrate and conductive shims used in the module; Figure 11 shows process steps of a method for manufacturing a power semiconductor module according to an embodiment of the present disclosure.

In the figures, like parts are denoted by like reference numerals. It will be appreciated that the drawings are for illustration purposes only and are not drawn to scale.

Detailed Description of the Preferred Embodiments

Figure 1 shows a high-level circuit diagram of an electric control system 800 which is suitable for use in EV and HEV applications. The electric control system 800 incudes, from left to right, a battery, a variable voltage converter (also called "VVC") 820, and a dual 3-phase inverter circuit (also called "dual inverter circuit") which drives two electric motors. The two electric motors generally comprise a generator motor (shown as "G") and a traction motor (shown as "M"). The generation motor may be for example an integrated starter generator. However, in some cases, both of the electric motors may be traction motors if needed.

The VVC is a bi-directional DC/DC boost converter which boosts up an input voltage from the battery to a system required level. The VVC includes an input capacitor Cl, an inductor Lin, and a half-bridge IGBT power module based converter.

The dual inverter circuit includes two independent inverters, i.e., a generator inverter 840 and a motor inverter 860, each providing three-phase AC output for driving a respective electric motor. The DC-link capacitor C2 supports both inverters by providing a stable input voltage. Both inverters are bi-directional.

During the start, acceleration and cruising operations of HEV/EV, the VVC 820 boosts up the input voltage from the battery to the system required level, and electric power flows from the battery, through the VVC 820 and the dual inverter circuit 840, 860, to one or both of the motors G, M. The dual inverter circuit converts DC power to AC power for driving the motor(s).

During the braking operation of HEV/EV, a propulsion system (not shown in Figure 1) of the HEV/EV will have a slower speed than a rotation speed of the electromagnetic field within the traction motor. This means that the traction motor is charging the battery. The inverter then converts AC power to DC power and utilities the VVC to reduce the converted DC voltage level before charging the battery. During this process, power/energy flows from the traction motor back to the battery through the corresponding inverter.

In a typical electric control system in HEV/EV applications, the VVC may handle a higher current than the generator inverter or the motor inverter. This is because the VVC aims to provide power for both the traction motor and the generator motor during the maximum power output operations. However, in some cases, the traction motor can be designed to have higher power output by using the generator motor as part of the input source. Although the generator inverter and the motor inverter are illustrated as three-phase inverters in Figure 1, it would be understood that one or more of the inverters may be a multi-phase inverter.

Figure 2 shows a circuit diagram of a power semiconductor module 100 (also referred to as "power module" for brevity) according to an embodiment of the present disclosure.

The power module 100 comprises a first half-bridge switch 110 and a second half-bridge switch 120 electrically connected in parallel between a DC positive power terminal DC+ and a DC negative power terminal DC-of the power module 100. The first half-bridge switch 110 comprises a first high side device 112, a first low side device 116 and a first output terminal AC1 connected therebetween. The second half-bridge switch 120 comprises a second high side device 122, a second low side device 126 and a second output terminal AC2 connected therebetween.

The power module 100 provides one phase of the generator inverter 840 and one phase of the motor inverter 860 as shown in Figure 1. Three instances of the power module 100 shown in Figure 2 can be connected together to provide the generator inverter 840 and the motor inverter 860. Further, the power module 100 may also provide the half-bridge structure of the VVC 820. In an example, the first half-bridge switch 110 belongs to the generator inverter 840, and the second half-bridge switch 120 belongs to the motor inverter 860. In a typical electric control system of HEV/EV applications, the generator inverter handles a lower current than the motor inverter. Therefore, each of the first high side device 112 and the first low side device 116 comprises one power transistor chip (i.e., Ti or T2) in anti-parallel connection with one diode chip (i.e., D1 or D2), and each of the second high side device 122 and the second low side device 126 comprises two power transistor chips (i.e., T3&T4, or T5&T6) in anti-parallel connection with two diode chips (i.e., D3&D4 or D5&D6). In an example, the power transistor chips are insulated gate bipolar transistor (IGBT) chips, and the diode chips are fast recovery diode (FRD) chips. It would be appreciated that depending on power and current ratings, each of the half-bridge switches 110, 120 may have different numbers of power transistor chips and diode chips from those shown in Figure 2. Further, the power transistor chips and diode chips may be wide bandgap semiconductor power chips, such as silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET), and Schottky diode chips. Furthermore, the body diodes of the SiC MOSFETs may be used such that the Schottky diode chips may be eliminated. A negative temperature coefficient (NTC) thermistor 130 is integrated in the module 100 as a temperature sensor.

The first high side device 112 has a high side power terminal 113 (also referred to herein as "collector terminal" and "collector/cathode terminal") that is coupled to DC+ terminal, a low side power terminal 114 (also referred to herein as "emitter terminal" and "emitter/anode terminal") that is coupled to the first output terminal Ad, and control terminals Gl, Cl and El for switching on and off its power transistor chip Ti. Similarly, the first low side device 116 has a high side power terminal 117 that is coupled to the first output terminal AC1, a low side power terminal 118 that is coupled to the DC-terminal, and control terminals G2, 02 and E2 for switching on and off its power transistor chip 12. The second high side device 122 has a high side power terminal 123 that is coupled to DC+ terminal, a low side power terminal 124 that is coupled to the second output terminal AC2, and control terminals G3, 03 and E3 for switching on and off its power transistor chips T3 and T4. The second low side device 126 has a high side power terminal 127 that is coupled to the first output terminal AC2, a low side power terminal 128 that is coupled to the DC-terminal, and control terminals G4, 04 and E4 for switching on and off its power transistor chips T5 and T6.

The physical structure of the power module 100 that implements the circuit diagram of Figure 2 is shown in Figures 3 to 10. In the physical structure, the power transistor chips Ti to T6 are embodied as IGBT chips, and the diode chips Di to D6 are embodied as FRD chips.

The power module 100 has a bottom substrate which comprises an electrically insulating layer 20 (Figures 6 and 7), a patterned electrically conductive layer arranged on an inner surface of the insulating layer 20, and another electrically conductive layer 21 (Figure 4) arranged on an outer surface of the insulating layer 20. The "outer surface" used in the present disclosure refers to a surface which faces away from the IGBT chips or the FRD chips and is typically exposed to an exterior of the power module 100. The "inner surface" used herein refers to a surface opposite to the outer surface, and is typically encapsulated by an encapsulant 80 (Figure 3). The patterned electrically conductive layer of the bottom substrate forms conductive tracks 201 to 215 on the inner surface of the insulating layer 20. The conductive tracks 201 to 215 are separated, thus electrically isolated, from one another. Each of the conductive tracks 201 to 215 is a single continuous (i.6., unbroken) track.

With reference to Figures 6 and 7, collector pads of the IGBT chips Ti, T3 and T4 and cathode pads of the FRD chips D1, D3 and D4 (i.e., the high side terminals 113, 123 of Figure 2) are securely attached (or bonded) to the conductive track 205 of the bottom substrate. Terminal 15 (i.e., the DC+ terminal of Figure 2) is further bonded to the conductive track 205 which also holds Terminal 5 (i.e., the C1/C3 terminal of Figure 2). The collector pad of the IGBT chip T2 and the cathode pad of the FRD chip D2 (i.e., the high side terminal 117 of Figure 2) are attached to the conductive track 213. Terminal 13 (i.e., the AC1 terminal) is bonded to the conductive track 213. Collector pads of the IGBT chips 15, T6 and cathode pads of the FRD chips D5, D6 (i.e., the high side terminal 127 of Figure 2) are attached to the conductive track 212. Terminal 12 (i.e., the AC2 terminal) is further bonded to the conductive track 212.

With further reference to Figures 6 and 7, a wire bond 71 is used to connect the gate pad of the IGBT chip Ti to the conductive track 201 holding Terminal 1 (i.e., the G1 terminal of Figure 2). Wire bonds 73, 74 are used to connect the gate pads of the IGBT chips 13 and T4 to the conductive track 203 holding Terminal 3 (i.e., the G3 terminal). A wire bond 72 is used to connect the gate pad of the IGBT chip T2 to the conductive track 206 holding Terminal 6 (i.e., the G2 terminal). Wire bonds 75, 76 are used to connect the gate pads of the IGBT chips T5 and 16 to the conductive track 208 holding Terminal 8 (i.e., the G4 terminal).

Conductive shims 41 to 46, 51 to 56 and 601 to 610 in combination with conductive tracks 301 to 303 of a top substrate are used to achieve the remaining interconnections required by the circuit diagram of Figure 2.

With reference to Figures 6 and 7, conductive shims 41 to 46 are bonded to topside bond pads (i.e., power emitter pads) of IGBT chips Ti to T6, respectively, and conductive shims 51 to 56 are bonded to topside bond pads (i.e., anode pads) of FRD chips D1 to 06, respectively. The topside bond pads of the IGBT chips Ti to T6 and the FRD chips D1 to D6 correspond to the low side terminals 114, 124, 118 and 128 of Figure 2.

The conductive shims 601 to 603 and 606 to 608 are bonded to conductive tracks 204, 207, 209, 213, 215, 202, respectively. Conductive shims 604, 605 and Terminal 14 are both bonded to the conductive track 214. Terminal 16 is bonded to the conductive track 215. As described below in more detail, Terminals 14, 16 collectively provide the DC-terminal of Figure 2. Conductive shims 609, 610 are both bonded to the conductive track 212.

As shown in Figure 6 which is a perspective view of the power module 100 with the top substrate and the encapsulant 80 being invisible, the conductive shims 41 to 46, 51 to 56 and 601 to 610 extend upwards along a direction that is generally perpendicular to the insulating layer 20 of the bottom plate. A height of each of the conductive shims 601 to 610 is substantially the same as a sum of a height of each IGBT chip Ti to 16 and a height of each of the conductive shims 41 to 46, and also substantially the same as a sum of a height of each FRD chip D1 to D6 and a height of each of the conductive shims Si to 56. In this way, the top surfaces of the conductive shims 41 to 46, 51 to 56 and 601 to 620 are generally aligned at the same level with respect to the bottom substrate. It would be understood that the height of each of the conductive shims 601 to 610 is greater than a thickness of each of Terminals 1 to 16, such that Terminals 1 to 16 would not directly contact conductive tracks on the top substrate of the power module 100.

The top substrate of the power module 100 comprises an electrically insulating layer 30 (Figures 8 and 9), a patterned electrically conductive layer (Figures 8 and 9) arranged on an inner surface of the insulating layer 30, and another electrically conductive layer 31 (Figure 3) arranged on an outer surface of the insulating layer 30. As shown in Figures 8 and 9, the patterned electrically conductive layer of the top substrate forms conductive tracks 301 to 303 on the inner surface of the insulating layer 30. The conductive tracks 301 to 303 are separated, thus electrically isolated, from one another. Each of the conductive tracks 301 to 303 is a single continuous (i.e., unbroken) track.

In Figures 6 and 7, the encapsulant 80 and the top substrate have been omitted from the drawings in order to clearly illustrate the layout of the IGBT chips, the FRD chips and the conductive shims with respect to the bottom substrate. To assemble the power module 100, the top substrate shown in Figure 9 is flipped over with the conductive tracks 301 to 303 facing the structure as shown in Figure 7, and the conductive tracks 301 to 303 are then bonded to the top surfaces of the conductive shims 41 to 46, 51 to 56 and 601 to 610. The spatial relationship of the conductive tracks 301 to 303 and the conductive shims is schematically illustrated by Figure 10. It would be understood that in reality, once the top substrate is placed on top of the conductive shims, the components between the top and bottom substrates would not be visible as they would be covered by the top substrate. The diagram of Figure 10 is provided to conceptually illustrate how the conductive tracks 301 to 303 are aligned with the conductive shims 41 to 46, 51 to 56 and 601 to 610.

With reference to Figure 10, the conductive shims 42, 45, 46, 52, 55, 56 are bonded to the conductive track 301, and thus electrically connect the emitter pads of the IGBT chips T2, T5, T6 and the anode pads of the FRD chips 02, 05, 06 to the conductive track 301. The conductive shims 604, 605 and 607 are further bonded to the conductive track 301 and thus electrically connect the conductive track 301 to Terminals 14 and 16 (i.e., the DC-terminal of Figure 2). The conductive shims 602 and 603 are also bonded to the conductive track 301, and thus electrically connect the conductive track 301 to the conductive tracks 207 and 209 of the bottom substrate, respectively. The conductive track 207 holds Terminal 7 (i.e., the auxiliary emitter terminal E2 of Figure 2). The conductive track 209 holds Terminal 9 (i.e., the auxiliary emitter terminal E4 of Figure 2). The term "auxiliary emitter terminal" refers to a control terminal of an IGBT, and differs from a power emitter terminal where power current flows through (e.g., the low side terminals described above). It is generally desirable to separate the auxiliary emitter terminal from the power emitter terminal, so as to avoid the power circuit from influencing the control circuit.

The conductive shims 41, 51 are bonded to the conductive track 303, and thus electrically connect the emitter pad of the IGBT chip Ti and the anode pad of the FRD chip D1 to the conductive track 303. The conductive shim 606 is further bonded to the conductive track 303, and thus electrically connect the conductive track 303 to the conductive track 213 of the bottom substrate (which holds Terminal 13, the AC1 terminal). The conductive shim 608 is also bonded to the conductive track 303, and thus electrically connect the conductive track 303 to the conductive track 202 of the bottom substrate. As shown in Figure 7, the conductive track 202 holds Terminal 2 (i.e., the auxiliary emitter terminal El of Figure 2).

The conductive shims 43, 44, 53, 54 are bonded to the conductive track 302, and thus electrically connect the emitter pads of the IGBT chips T3, T4 and the anode pads of the FRD chips D3, D4 to the conductive track 302. The conductive shims 609, 610 are further bonded to the conductive track 302, and thus electrically connect the conductive track 302 to the conductive track 212 of the bottom substrate (which holds Terminal 12, the AC2 terminal). The conductive shim 601 is also bonded to the conductive track 302, and thus electrically connect the conductive track 302 to the conductive track 204 of the bottom substrate. As shown in Figure 7, the conductive track 204 holds Terminal 4 (i.e., the auxiliary emitter terminal E3 of Figure 2). Conventional power modules house either a single switch, a single half-bridge switch, two-phase half-bridge switches or three-phase half-bridge switches. The single switch and single half-bridge switch modules would readily be designed and manufactured using the conventional techniques while maintaining sufficient reliability. This is because small numbers of power semiconductor chips are involved in these modules and the footprints of these modules are small so that the bending/warpage and thermo-mechanical stress/strain developments of these modules could be at a relatively low level. It is generally critical to arrange the layouts of power semiconductor chips, internal wiring and terminals, design the packaging structures and select the assembling processes of the two-phase and three-phase half bridge switch modules with large footprints for achieving good electrical performance and thermal performance while maintaining sufficient thermo-mechanical reliability. For this reason, even though the two-phase and three-phase half-bridge switch modules house more than one half-bridge switch, each half-bridge switch owns its independent conductive tracks and power terminals.

Unlike the conventional power modules in which each half-bridge switch owns its independent conductive tracks and power terminals, the power module 100 of the present disclosure comprises two (or more) half-bridge switches 110, 120 sharing conductive tracks and power terminals. In particular, the high side power terminals 113, 123 of the high side devices 112, 122 (i.e., the bottom pads of the IGBT chips Ti, T3 and T4 and the FRO chips D1, 03 and D4 as shown in Figures 6 and 7) within each of the two half-bridge switches 110, 120 are attached to the same conductive track 205 of the bottom substrate. The low side power terminals 118, 128 of the low side devices 116, 126 (i.e., the top pads of the IGBT chips T2, T5 and T6, and the FRD chips, D2, D5 and D6 as shown in Figures 6 and 7) within each of the two half-bridge switches 110, 120 are connected to the same conductive track 301 of the top substrate (through six conductive shims 42, 45, 46, 52, 55 and 56). Furthermore, the two half-bridge switches 110, 120 share the same DC positive power terminal (i.e., Terminal 15) and DC negative power terminal (i.e., collectively provided by the Terminal 14 and Terminal 16).

The shared conductive tracks and power terminals lead to not only reduced volume and weight of the power module 100 but also simplified connections to an external DC power supply. Specifically, by utilising the conductive tracks formed on both of the bottom and the top substrates to electrically connect the components of the half-bridge switches, the power module 100 becomes more compact and achieves a smaller dimension than conventional power modules. This means that the power module 100 provides an increased power density than conventional power modules.

An external DC power supply may be connected to Terminals 14 to 16 by screw connections or a bonding technology such as laser welding. With simplified connections to the external DC power supply, multiple instances of the power module 100 can be easily connected to construct a multi-inverter system (e.g., the dual-inverter system shown in Figure 1). The conductive shims 41 to 46, 51 to 56 and 601 to 610 have the ability of carrying significantly higher level current than the wire bonds attached to the top surfaces of the IGBT and FRO chips as used in the conventional power modules, and thus are useful for improving the reliability of the power module 100 The conductive layer 21 on the outer surface of the bottom substrate and the conductive layer 31 on the outer surface of the top substrate can be used as the two cooling surfaces to achieve double side cooling. They can be sealed on two heat sinks in direct contact with coolant or mounted on the cold plates of two heat sinks with thermal interface material (TIM) and/or bonding technology such as lead-free soldering or sintering technology. Accordingly, the power module 100 achieves an improved thermal performance.

To improve the switching performance of the half-bridge switches 110, 120, the power module 100 employs the particular arrangement of Terminals 14 to 16 (power terminals DC+ and DC-of Figure 2) as shown in Figure 7 and also provides slots 310, 320 in the conductive tracks of the top substrate as shown in Figures 9 and 10. This is described in more detail below.

With reference to the circuit diagram of Figure 2, parameters indicating the switching performance of the first half-bridge switch 110 include parasitic inductances of the commutation loops (i) DC+ -> Ti -> D2 -> DC-and (ii) DC-F-> Di -> T2 -> DC-.

In particular, the output at the AC1 terminal is an AC power, so output current can either flow out of the AC1 terminal (to the right direction) or flow into the AC1 terminal (to the left direction). When the output current flows out of the AC1 terminal, there is a current discontinuity for both Ti and D2 during the switching process of Ti. For example, when Ti is ON, current flows from DC+ -> Ti -> AC1, but when Ti is OFF, current flows from DC--> D2 -> AC1. In other words, the output current will always flow through one device, either at the high side or the low side, before flowing out of the AC1 terminal. Therefore, when Ti switches from one status to the other status (i.e., ON to OFF, or OFF to ON), the current flowing through Ti and the current flowing through D2 change in opposite manners. Thus, there is a current discontinuity for both Ti and D2 when Ti switches. This current discontinuity causes an extra voltage drop across Ti due to the parasitic inductance of the commutation loop (i). On the other hand, when the output current flows into the AC1 terminal, there is a current discontinuity for both T2 and D1 during the switching process of T2, and the current discontinuity causes an extra voltage drop across T2 due to the parasitic inductance of the commutation loop (ii).

Similarly, parameters indicating the switching performance of the second half-bridge switch 120 include parasitic inductances of the commutation loops (hi) DC+ -> T3&T4 -> D5&D6 -> DC-; (iv) DC+-> D3&D4 -> T5&T6 -> DC-.

Turning to the physical structure of the power module 100 as shown in Figures 3 to 10, the commutation loop (i) is formed by: Terminal 15 (DC+) -> the conductive track 205 of the bottom substrate -> the IGBT chip Ti and the conductive shim 41 -> the conductive track 303 of the top substrate -> the conductive shim 606 -> the conductive track 213 of the bottom substrate -> the FRD chip D2 and the conductive shim 52 -) the conductive track 301 of the top substrate -) three conductive shims 604, 605 and 607 on two conductive tracks 214 and 215 of the bottom substrate -> Terminals 14 and 16 (DC-).

The commutation loop (ii) is formed by: Terminal 15 (DC+) -> the conductive track 205 of the bottom substrate -) the FRD chip D1 and the conductive shim 51 -> the conductive track 303 of the top substrate -) the conductive shim 606 -> the conductive track 213 of the bottom substrate -> the IGBT chip T2 and the conductive shim 42 -> the conductive track 301 of the top substrate -> three conductive shims 604, 605 and 607 on two conductive tracks 214 and 215 of the bottom substrate -) Terminals 14 and 16 (DC-).

The commutation loop OD is formed by: Terminal 15 (DC+) the conductive track 205 of the bottom substrate -> the IGBT chips T3&T4 and the conductive shims 43&44 -) the conductive track 302 of the top substrate -> the conductive shims 609, 610 -) the conductive track 212 of the bottom substrate -) the FRD chips D5&D6 and the conductive shims 55, 56 -> the conductive track 301 of the top substrate -> three conductive shims 604, 605 and 607 on two conductive tracks 214 and 215 of the bottom substrate -> Terminals 14 and 16 (DC-).

The commutation loop (iv) is formed by: Terminal 15 (DC+) -> the conductive track 205 of the bottom substrate -) the FRD chips D3&04 and the conductive shims 53&54 -> the conductive track 302 of the top substrate -> the conductive shims 609&610 -> the conductive track 212 of the bottom substrate -> the IGBT chips T5&T6 and the conductive shims 45&46 -) the conductive track 301 of the top substrate -) three conductive shims 604, 605 and 607 on two conductive tracks 214 and 215 of the bottom substrate -> Terminals 14 and 16 (DC-).

The parasitic inductances of the commutation loops (i) to (iv) should preferably be reduced so as to improve the switching performance (more specifically, to reduce the extra voltage drop and hence the voltage overshoots during the switching off stages). Further, it is generally beneficial to equalise the parasitic inductances of the commutation loops for the same half-bridge switch, thereby allowing the half-bridge switch to have a balanced switching performance regardless of the flowing direction of the output current. Regarding the commutation loops (iii) and (iv), it is also useful to improve the current distribution between the IGBT chips or FRD chips which are connected in parallel. An improved current distribution improves the switching performance of the second half-bridge switch 120. These are achieved by the following features of the power module 100: As shown in Figure 7, the power terminals of the power module 100 include two interconnected Terminals 14 and 16 (DC-), which are provided at the two sides of Terminal 15 (DC+). The arrangement of Terminals 14 to 16 achieves local anti-parallel current flows. More specifically, because Terminals 14 to 16 are arranged at the same side of the power module 100 (i.e., at the top side with reference to the orientation shown in Figure 7), and Terminal 15 (DC+) is sandwiched by Terminals 14 and 16 (DC-), the power current flowing through the conductive track 205 from Terminal 15 flows in a direction substantially opposite to that of the power current flowing through the conductive track 301 into Terminals 14 and 16. The opposite flowing directions of the power currents cause cancellation of magnetic fluxes generated by the power currents, thereby reducing the wiring inductances of Terminals 14 to 16. Further, providing one extra DC negative power terminal allows the power current flowing through the conductive track 301 to branch into two paths. The current branching avoids concentration of the power current in a limited part of the conductive track 301, thereby effectively reducing the wiring inductance of Terminals 14 and 16. The reduction of wiring inductances caused by the arrangement of Terminals 14 to 16 applies to each of the commutation loops (i) -(iv). The reduction is more than 30% in an example as compared to a scenario where only Terminal 14 is used as the DC negative power terminal.

With further reference to Figures 9 and 10, a slot (or narrow gap) 310 is formed in the conductive track 301 of the top substrate for guiding current flow in the conductive track 301. As shown in Figure 10, the slot 310 surrounds a top side and a left side of the conductive shim 42 which is bonded to the emitter pad of the IGBT chip T2. As such, with the slot 310, current flowing out of the emitter pad of the IGBT chip T2 must follow a path P1 which extends around a, lower, free end of the slot 310 before flowing back to Terminals 14, 16 (DC-). In contrast, if the slot 310 were omitted, current flowing out of the emitter pad of the IGBT chip T2 would take a much shorter and wider route to reach Terminals 14, 16 (DC-). Therefore, by partially obstructing the current flow path between the IGBT chip T2 and Terminals 14, 16 (DC-), the slot 310 slightly increases the parasitic inductance of the commutation loop (ii), thereby bringing the parasitic inductances of the commutation loops (i) and 00 to similar levels. Therefore, the slot 310 improves the switching performance of the first half-bridge switch 110.

A slot (or narrow gap) 320 is formed in the conductive track 302 of the top substrate for guiding current flow in the conductive track 302. As shown in Figure 10, the slot 320 surrounds a right side of the conductive shim 53 which is bonded to the anode pad of the FRD chip 03. With the slot 320, current flowing out of the emitter pad of the IGBT chip T3 or the anode pad of the FRD chip D3 must follow a slightly longer and narrower path P2 as compared to a scenario where the slot 320 is omitted, before flowing to the conductive shims 609, 610. Therefore, by partially obstructing the current flow path between the IGBT chip 13 and Terminal 12 (AC2), the slot 320 increases the wiring inductance and the wiring resistance of a power current flow path through the IGBT chip T3, and thus improves the current distribution between the IGBT chips T3 and T4 which are connected in parallel. Similarly, by partially obstructing the current flow path between the FRD chip D3 and Terminal 12 (AC2), the slot 320 increases the wiring inductance and the wiring resistance of a power current flow path through the FRD chip D3, and thus improves the current distribution between the FRD chips D3 and D4 which are connected in parallel. Therefore, the slot 320 improves the switching performance of the second half-bridge switch 120.

Generally, the parasitic inductance and resistance values of the commutation loops depend on the size of the IGBT and FRD chips. In an example, the sizes of each IGBT chips and each FRD chip are 12 mm by 12 mm and 12 mm by 6 mm, respectively, and each of the commutation loops described above has a parasitic inductance value of 8 to 15 nH and a parasitic resistance value of 0.15 to 0.50 mOhm. The wiring inductance/resistance of a commutation loop may be obtained by simulation methods well known in the field.

It would be understood that the locations/shapes of the slots 310, 320 may vary, and that the number of slots within the conductive tracks may vary. Further, slot(s) may be provided on the conductive tracks of the bottom substrate. For example, the slot 320 may be replaced by a slot formed in the conductive track 205 which is suitably positioned to impede a current flow between Terminal 15 and the IGBT chip T3 (or the FRD chip 03). The locations/shapes/numbers of the slots may be suitably determined based upon the simulation results in connection with the commutation loops.

Each of the slots 310, 320 should be as narrow as possible. This is because a narrow slot would allow the conductive track at the two sides of the slot to be electrically continuous with substantially the same electrical potential or voltage, and on the other hand, a wider slot would somewhat reduce the spreading of the heat dissipated by the IGBT and FRD chips. Preferably, the width of each slot may not be greater than approximately 3mm in order for the conductive track to have satisfactory electrical continuity and thermal conductance. More preferably, the width of each slot may not be greater than approximately 2mm. From the manufacturing technique used to produce the substrates, the narrowest slot which can be achieved may have a width of about 0.8 to about 1 mm.

As shown in Figure 2, the second half-bridge switch 120 contains two IGBT chips (i.6., T3 and T4 or 15 and T6) and two FRD chips (i.e., D3 and D4 or D5 and D6), which are connected in parallel in each of its high side and low side devices 122 and 126. The IGBT chips connected in parallel and their gate wire bonds (i.e., 73 and 74 or 75 and 76) are arranged in such a way that the conducting loops between the gate and auxiliary emitter terminals of each IGBT chip have similar parasitic inductance and resistance values. For example, as shown in Figure 7, the wire bonds 73, 74 are arranged substantially symmetrically between the IGBT chips T3, 14, and the wire bonds 75, 76 are arranged substantially symmetrically between the IGBT chips T5, T6.

It would be appreciated that in the event that more than two IGBT chips (or SIC MOSFET chips) are connected in parallel, the gate wire bonds may be surrounds by the chips such that each chip experiences gate control loops with similar parasitic inductance and resistance values.

With reference to Figure 7, it can be seen that Terminals 14 to 16 (DC+ and DC-) are placed at a first, top, side of the power module 100, and that Terminals 1 to 11 (i.e., the signal and control terminals) are placed at a second, bottom, side of the power module 100. The signal and control terminals are organized into five groups: (i) Terminal 1 (G1) and Terminal 2 (E1/C2); (ii) Terminal 3 (G3) and Terminal 4 (E3/C4); (iii) Terminal 5 (C1/C3); (iv) Terminal 6 (G2), Terminal 7 (E2), Terminal 8 (G4) and Terminal 9 (E4); and (v) Terminal 10 (Ni) and Terminal 11 (N2). Here the symbols in the parentheses stand for the ports illustrated in Figure 2. Terminals 10 and 11 are two nodes of the NTC thermistor 130. It would be understood that sufficient physical distances should be maintained between the terminals of the different groups. These terminals with such placement and organization can be connected to a drive and control printed circuit board (PCB) with relatively simple structure while still keeping sufficient insulating and creepage distances. In particular, no additional consideration of insulating and creepage distances is needed for the PCB Both of the AC output terminals -Terminal 12 (AC2) and Terminal 13 (AC1) -of the two half-bridge switches 110, 120 are placed at a third, right, side of the power module 100. No terminals are placed at a fourth, left, side of the power module 100.

The power terminals 12 to 16 can be connected to external DC source and electric motors by screw connections or a bonding technology such as laser welding. The above-described arrangement of Terminals 1 to 16 may facilitate the sealing or mounting of double side heat sinks on the top surface (i.e., a surface of the conductive layer 31 as shown in Figure 3) and bottom surface (i.e., a surface of the conductive layer 21 as shown in Figure 4) of the power module 100. This is because the inlets and outlets of the double side heat sinks may be conveniently placed at the fourth, left, side of the power module 100.

As shown in Figures 3 to 5, the encapsulant 80 fills the gaps between the top and bottom substrates, and encapsulates the semiconductor chips T1-T6 and D1-D6, the wire bonds 71-76, the conductive shims, and the joints between Terminals 1 to 16 and the conductive tracks of the bottom substrate. In this way, the encapsulant 80 protects the internal components of the power module 100. The encapsulant 80 is made of an electrically insulating but preferably thermally conductive material. It would be understood that a majority Cif not all) of the conductive layer 21 of the bottom substrate and a majority (if not all) of the conductive layer 31 of the top substrate are exposed from the encapsulant 80 in order to form a direct contact with two-side heat removal bodies (e.g., heat sinks).

The encapsulant 80 may be made of a moulding compound, rather than conventionally used silicone gel. Using a moulding compound as the encapsulant 80 is useful for improving the reliability of the power module 100.

More specifically, silicone gel is a soft material and would not be able to improve the strength of the power module when used alone. Thus, a rigid plastic housing is typically used to further enclose the silicone gel. A moulding compound can eliminate the use of the plastic housing. Hence, using the moulding compound allows the volume On particular, the thickness) of the power module 100 to be reduced as compared to using the silicone gel, or provides better insulation with similar dimensions or volume of the power module. The moulding compound, once cured, may lead to additional compressive stresses for enhancing the joints between the chips, shims and substrates in the module, and hence reduce the formation and growth of fatigue cracks which are due to shear and/or tensile stress and strain developments. Accordingly, using a moulding compound may improve the reliability of the power module 100. The moulding compound may comprise epoxy, other polymer based materials, or inorganic materials with high insulating strength. Preferably, a polymer-based moulding compound may contain fillers such as silica, aluminium nitride or boron nitride fillers having high thermal conductivity and low coefficient of thermal expansion (CTE) to improve the thermal conductivity and constrain the GTE of the moulding compound. The curing temperature of the moulding compound may be at least 20°C lower than the lowest melting point of the solder alloys used to attach the semiconductor chips and bond the conductive shims and terminals.

One or both of the bottom substrate and the top substrate of the power module 100 may be chosen from direct bonded copper (DBC), directed bonded aluminium (DBA) or active brazed metal (ABM) substrates. In that case, one or each of the insulating layers 20, 30 may comprise 0.2 mm to 1 mm thick alumina, aluminium nitride or silicon nitride ceramic tiles. The conductive layers on both sides of the insulating layers may comprise 0.1 mm to 1 mm thick pure copper, pure aluminium, copper-molybdenum alloy, copper-tungsten alloy, or other pure metals or alloys with similar thermal, electrical and thermo-mechanical properties. The conductive layer on one side of the top substrate may be patterned (e.g., by dry or wet etching) to form the conductive tracks 301 to 303. The conductive layer on one side of the bottom substrate may be patterned (e.g., by dry or wet etching) to form the conductive tracks 201 to 215. Alternatively, one or each of the bottom substrate and the top substrate may be an insulated metal substrate (IMS). In that case, one or each of the insulating layers 20, 30 may comprise 0.05 mm to 0.25 mm thick resin compound, or other organic-based materials with high insulating strength and high thermal conductivity. The conductive layers on both sides of the insulating layers are in general made of pure copper, pure aluminium, copper alloy, aluminium alloy, or other pure metals or alloys with similar thermal, electrical and thermo-mechanical properties, and may have the same or different thicknesses in the range of 0.05 mm to several millimetres.

Of the above-described DBC, DBA, ABM substrates and IMSs, silicon nitride based ABM substrates may be used for high performance and high reliability applications. This is because silicon nitride based ABM substrates have high mechanical strength and can withstand high mechanical stresses for sealing or mounting the double side heat sinks and have good thermo-mechanical reliability.

The conductive shims 41 to 46, 51 to 56 and 601 to 610 may be made of pure metal (such as pure copper and pure aluminium), alloy (such as copper-molybdenum alloy and copper-tungsten alloy), metal-matrix composite (such as copper-graphite composite and aluminium-carbon fibre composite), or other materials with high thermal conductivity and high electrical conductivity. Preferably, the conductive shims are made of materials with CTEs matched or close to those of the substrates and/or semiconductor chips.

The semiconductor chips, Ti to T6 and D1 to D6, and the NTC thermistor may be attached to the conductive tracks of the bottom substrate with lead-free solder alloys (such as tin-silver, fin-copper, fin-silver-copper, fin-antimony, bismuth-silver solder alloys). Alternatively, they may be attached to the bottom substrate with sintering technologies (such as silver sintering and copper sintering technologies). Similarly, the conductive shims 41 to 46, 51 to 56 and 601 to 610 may be bonded between the top surfaces of the semiconductor chips and the conductive tracks of the top substrate or between the conductive tracks of the bottom substrate and the conductive tracks of the top substrate with lead-free solder alloys or the sintering technologies. It would be understood that the conductive shims 41 to 46, 51 to 56 and 601 to 610 may be bonded with the same solder alloy or several solder alloys with different melting points, or combined sintering technology and solder alloys.

The power terminals 12 to 16 and the signal/control terminals 1 to 11 may be made of materials similar to those of the conductive shims with high thermal conductivity and high electrical conductivity. They may be bonded on the corresponding conductive tracks of bottom substrate with solder alloys or sintering technologies in a way similar to attaching the semiconductor chips and bonding the conductive shims. Alternatively, they may be bonded on the conductive tracks of bottom substrate with ultrasonic welding technology. Preferably, the terminals 1 to 16 may be made of metals or alloys such as pure copper, pure aluminium, copper alloy or aluminium alloy with sufficient strength and good ductility.

Using lead-free solder joints to attach the semiconductor chips and to bond the conductive shims and the terminals is preferred for low cost applications where the junction temperatures of the semiconductor chips are in general lower than 150 °C. Using sintered silver or copper joints to attach the semiconductor chips and to bond the conductive shims and the terminals is preferred for high temperature and high reliability applications where the junction temperatures of the semiconductor chips may be higher than 150°C As described above, the power module 100 has integrated two half-bridge switches 110, 120 which share conductive tracks of the substrates and also share power terminals 14 to 16. In this way, the volume and weight of the power module 100 can further be reduced, and better layout of the power terminals can be realized for achieving low wiring inductance and resistance. Further, conductive shims 41-46 and 51-56 are used to replace conventional wire bonds for topside interconnection of semiconductor chips and are able to carry higher currents. Furthermore, layouts of the conductive tracks connecting to the semiconductor chips are designed to include slots 310, 320. The slots 310, 320 improve the switching performances of the half-bridge switches. The slot 320 in particular improves the current distribution between two IGBTs (e.g., T3, T4) which are connected in parallel. In addition, a moulding compound is used as the encapsulant 80. The moulding compound not only ensures sufficient insulating and creepage distances between the related conductive tracks and between the terminals, but also adds mechanical support and hence improves reliability of the power module 100. All these factors contribute to the power module 100 with further improved power density, electrical/thermal performance and thermo-mechanical reliability, and benefit the construction of smaller and lighter dual-inverter systems for EV and HEV electric drive applications.

The power module 100 may be manufactured with following assembling steps: (i) a bonding process (e.g., a soldering process or sintering process) to bond all the IGBT chips Ti to T6 and FRD chips D1 to 06 and the NTC thermistor to the conductive tracks 205 and 210 to 213 of the bottom substrate, and to bond the conductive shims 41 to 46, 51 to 56 and 601 to 610 to the conductive tracks 301-303 of the top substrate; (ii) a ultrasonic bonding process to bond the wires 71-76 between the gate pads of the IGBT chips Ti to T6 and the corresponding conductive tracks 201, 203, 206 and 208 of the bottom substrate; (iii) a second bonding process (i.e. a soldering process or sintering process) to bond Terminals 1 to 16 and the free sides of the conductive shims 601 to 610 to the corresponding conductive tracks of the bottom substrate, and to bond the free sides of the conductive shims 41 to 46 and 51 to 56 to the topsides of the IGBT chips Ti to T6 and FRD chips D1 to D6; and (iv) a transfer moulding process to inject and form the moulding compound encapsulation 80.

A plurality of the power modules 100 may be inserted between multiple coolers (e.g., heat sinks) to form a stack unit. For example, the power modules 100 and the coolers (not shown) may be alternately stacked one by one, with two coolers in contact with both sides of each power module 100 thereby achieving double sided cooling. The stack unit is able to construct the generator inverter 840, the motor inverter 860 as well as the half-bridge structure of the VVC 820. Because each of the power modules 100 has integrated two half-bridge switches as described above, only four such power modules 100 (e.g., inserted between five coolers) would be sufficient to form the electric control system 800 shown in Figure 1. This is in contrast to prior techniques which would require eight or sixteen power modules (each of which includes either a single half-bridge switch or a single power transistor) inserted between nine or seventeen coolers in order to construct the same electric control system 800. Thus, the use of the power modules 100 allow the electric control system 800 to have a much reduced volume and weight as compared to prior techniques.

It would be appreciated that the arrangement of the power modules 100 and the coolers within the stack unit may be modified in any suitable manner. In an example, the number of coolers may be identical to the number of power modules, such that one of the power modules at an end of the stack unit benefits from single sided cooling.

In the power module 100, each of the top and bottom substrates has electrically conductive layers provided at both sides of the substrate. It would be appreciated that one or more of the top and bottom substrates may be modified such that only one side of the substrate is provided with an electrically conductive layer. It would also be understood that the conductive shims may be modified or replaced in any suitable manner, as long as they still allow electrical connections to be made between the top and bottom substrates or between the semiconductor chips and one substrate.

Further, it would be appreciated that rather than being a single substrate, the top/bottom substrate may be split into two or more smaller substrates. In that case, the dimension of the modified power module may be slightly larger than that of the power module 100, and the interconnection between the different substrates may be added and/or modified. For example, the top substrate may be replaced by three smaller substrates which support the conductive tracks 301-303, respectively. By splitting one substrate into two or more smaller substrates, the smaller substrates are allowed to experience different degrees of deformations without causing substantial thermal stress to the power module. Therefore, the deformation of the power module as a whole tends to be more elastic and less plastic. In this way, the thermo-mechanical reliability of the power module is improved.

In the power module 100, the collector terminals of the IGBT chips Ti to T6 and the cathode terminals of the FRD chips D1 to D6 are directly attached to the conductive tracks of the bottom substrate, and the conductive shims 41-46 and 51-56 are then used to connect the emitter/anode terminals of the chips to the conductive tracks 301303 of the top substrate. It would of course be understood that the power module 100 may be modified such that the emitter/anode terminals of at least some of the chips are directly attached to the conductive tracks 301-303 of the top substrate, while conductive shims are used to connect the collector/cathode terminals of the chips to the bottom substrate. Further, before the top and bottom substrates are bonded to one another, some of the chips may be bonded to the bottom substrate and other chips may be bonded to the top substrates.

It would further be understood that Figures 3 to 10 merely provide one example of the physical structure of the power module 100. The shapes and layout of the terminals 1 to 16 may be modified suitably. For example, some or all of the power terminals and signal/control terminals may be bonded to the top substrate. Further, the arrangement of the power terminals 14-16 as shown in Figs. 3 to 7 may be modified such that two DC positive power terminals are placed at opposite sides of one DC negative power terminal, or that two or more DC positive power terminals and two or more DC negative power terminals are arranged in an alternating matter.

It would also be appreciated that the circuit topology of the first and/or second half-bridge switches 110, 120 may be modified to differ from that shown in Figure 2. For example, the first and second half-bridge switches 110, 120 may share the same circuit topology. Further, the first and second half-bridge switches 110, 120 may switch on at the same time interval or at different time intervals. Depending upon the specific circuit topology of the power module, the layout of the semiconductor chips and the shapes of the conductive tracks on each substrate may be modified suitably. Further, the locations of the slots 310, 320 may vary accordingly.

While the power module 100 has integrated two half-bridge switches, it would be appreciated that the power module may integrate more than two half-bridge switches.

While the power module 100 includes an NTC thermistor 130 as a temperature sensor, it would be understood that the NTC thermistor 130 may be replaced by other types of temperature sensors, or may be omitted completely.

The bottom substrate and the top substrate may also be referred to as "first substrate" and "second substrate", respectively. The conductive tracks 205 and 301 may be referred to as "first conductive track" and "second conductive track", respectively. The conductive tracks 213, 212, 303 and 302 may be referred to "third conductive track", "fourth conductive track", "fifth conductive track" and "sixth conductive track", respectively. The conductive shim 606 may be referred to as "first conductive shim" while the conductive shims 609, 610 may be collectively referred to as "second conductive shim".

Figure 11 schematically illustrates processing steps of a method for manufacturing a power module (e.g., the power module 100).

At step Si, a first half-bridge switch (e.g., 110) and a second half-bridge switch (e.g., 120) are attached between a first substrate (e.g., the bottom substrate) and a second substrate (e.g., the top substrate). The first substrate comprises a first insulating layer (e.g., 20) and a first patterned conductive layer (e.g., 201-215) arranged on a surface of the first insulating layer which faces the half-bridge switches.

The second substrate comprises a second insulating layer (e.g., 30) and a second patterned conductive layer (e.g., 301-303) arranged on a surface of the second insulating layer which faces the half-bridge switches.

Attaching the first half-bridge switch and the second half-bridge switch comprises the following sub-steps M1 to M5: At sub-step M1, a high side terminal (e.g., 113) of a first high side device (e.g., 112) of the first half-bridge switch and a high side terminal (e.g., 123) of a second high side device (e.g., 122) of the second half-bridge switch are electrically connected to a first conductive track (e.g., 205) of the first patterned conductive layer.

At sub-step M2, the first conductive track (e.g., 205) is electrically connected to a DC positive power terminal (e.g., Terminal 15) of the power semiconductor module. At sub-step M3, a low side terminal (e.g., 118) of a first low side device (e.g., 116) of the first half-bridge switch (e.g., 110) and a low side terminal (e.g., 128) of a second low side device (e.g., 126) of the second half-bridge switch (e.g., 120) are electrically connected to a second conductive track (e.g., 301) of the second patterned conductive layer.

At sub-step M4, the second conductive track (e.g., 301) is electrically connected to a DC negative power terminal (e.g., Terminals 14, 16) of the power semiconductor module.

At sub-step M5, the first half-bridge switch and the second half-bridge switch are electrically connected in parallel between the DC positive power terminal and the DC negative power terminal.

At step 52, the first half-bridge switch and the second half-bridge switch are encapsulated by an encapsulant (e.g., 80).

The encapsulant may comprise a moulding compound. The moulding compound may be applied by transfer moulding.

It would be appreciated that the sub-steps M1 to M5 may be performed in a temporal order that is different from the order of description. For example, sub-steps M3 and M4 may be performed earlier than or simultaneously with sub-steps M1 and M2, and/or sub-steps M2 and M4 may be performed earlier than or simultaneously with sub-steps M1 and M3, respectively.

The terms "having", "containing", "including", "comprising" and the like are open and the terms indicate the presence of stated structures, elements or features but not preclude the presence of additional elements or features. The articles "a", "an" and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

The skilled person will understand that in the preceding description and appended claims, positional terms such as 'top', 'bottom', 'left', 'right' etc. are made with reference to conceptual illustrations of a power module, such as those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to a power module when in an orientation as shown in the accompanying drawings.

Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the disclosure, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

Claims

CLAIMS: 1. A power semiconductor module, comprising: a first substrate and a second substrate arranged at opposite sides of the power semiconductor module; a first half-bridge switch and a second half-bridge switch arranged between the first substrate and the second substrate, wherein the first half-bridge switch and the second half-bridge switch are electrically connected in parallel between a DC positive power terminal and a DC negative power terminal of the power semiconductor module, and wherein the first half-bridge switch comprises a first high side device, a first low side device and a first output terminal connected therebetween, and wherein the second half-bridge switch comprises a second high side device, a second low side device and a second output terminal connected therebetween; wherein: the first substrate comprises a first insulating layer and a first patterned conductive layer arranged on a surface of the first insulating layer which faces the half-bridge switches; the second substrate comprises a second insulating layer and a second patterned conductive layer arranged on a surface of the second insulating layer which faces the half-bridge switches; the first patterned conductive layer comprises a first conductive track which electrically connects high side terminals of the first and second high side devices to the DC positive power terminal; and the second patterned conductive layer comprises a second conductive track which electrically connects low side terminals of the first and second low side devices to the DC negative power terminal.
2. A power semiconductor module according to claim 1, wherein at least one of the first and second conductive tracks comprises a slot.
3. A power semiconductor module according to claim 2, wherein the slot is configured to affect a characteristic of a power current flow path through at least one of the devices that is electrically connected to the respective conductive track.
4. A power semiconductor module according to claim 2 or 3, wherein the at least one of the devices comprises two or more power transistors which are connected in parallel to one another, and the slot is configured to affect a characteristic of a power current flow path through at least one but not all of the two or more power transistors.
5. A power semiconductor module according to claim 3 or 4, wherein the characteristic comprises an inductance of the power current flow path.
6. A power semiconductor module according to any preceding claim, wherein the first patterned conductive layer comprises: a third conductive track which electrically connects a high side terminal of the first low side device to the first output terminal; and a fourth conductive track which electrically connects a high side terminal of the second low side device to the second output terminal.
7. A power semiconductor module according to any preceding claim, wherein the second patterned conductive layer comprises: a fifth conductive track which electrically connects a low side terminal of the first high side device to the first output terminal; and a sixth conductive track which electrically connects a low side terminal of the second high side device to the second output terminal.
8. A power semiconductor module according to claim 7 as dependent from claim 6, wherein at least one of the third to sixth conductive tracks comprises a slot.
9. A power semiconductor module according to any preceding claim as dependent from claims 6 and 7, further comprising: a first conductive shim extending between the first and second substrates and electrically connecting the third conductive track to the fifth conductive track; and a second conductive shim extending between the first and second substrates and electrically connecting the fourth conductive track to the sixth conductive track.
10. A power semiconductor module according to any preceding claim, wherein the power semiconductor module further comprises: conductive shims extending between at least some of the devices and the second substrate and electrically connecting low side terminals of the respective devices to the corresponding conductive tracks of the second patterned conductive layer; and/or conductive shims extending between at least some of the devices and the first substrate and electrically connecting high side terminals of the respective devices to the corresponding conductive tracks of the first patterned conductive layer.
11. A power semiconductor module according to claim 9 or 10, wherein the conductive shims are made of a material with a coefficient of thermal expansion which matches the coefficients of thermal expansion of the devices and/or the substrates. 10
12. A power semiconductor module according to any preceding claim, wherein: one of the DC positive power terminal and the DC negative power terminal comprises two or more first power terminals which are electrically connected to one another; the other of the DC positive power terminal and the DC negative power terminal comprises one or more second power terminals which are electrically connected to one another; the two or more first power terminals and the one or more second power terminals are arranged in an alternating manner.
13. A power semiconductor module according to any preceding claim, further comprising an encapsulant encapsulating the first half-bridge switch and the second half-bridge switch, wherein the encapsulant comprises a moulding compound.
14. A power semiconductor module according to claim 13, wherein the moulding compound comprises thermally conductive fillers.
15. A power semiconductor module according to any preceding claim, wherein one or more of the first and second insulating layers is made of an electrically insulating and thermally conductive material.
16. A power semiconductor module according to any preceding claim, further comprising a first heat removal body thermally coupled to the first insulating layer, and a second heat removal body thermally coupled to the second insulating layer.
17. A power semiconductor module according to any preceding claim, wherein: the DC positive power terminal and the DC negative power terminal are arranged at a first side of the power semiconductor module; the first and second output terminals are arranged at a second side of the power semiconductor module; control terminals of the first and second half-bridge switches are arranged at a third side of the power semiconductor module; and no terminals are arranged at a fourth side of the power semiconductor module, wherein the first to fourth sides of the power semiconductor module are defined by a boundary of the first and/or the second substrate.
18. A power semiconductor module according to any preceding claim, wherein one or more of the first and second substrates comprises a silicon nitride based active brazed metal substrate.
19. A power semiconductor module according to any preceding claim, wherein the first half-bridge switch is part of a generator inverter of an electric vehicle or a hybrid electric vehicle electric drive system, and the second half-bridge switch is part of a motor inverter of the electric vehicle or the hybrid electric vehicle electric drive system.
20. An electric drive system for an electric vehicle or a hybrid electric vehicle, comprising: at least three power semiconductor modules each of which being according to any preceding claim; wherein: the first half-bridge switches of the at least three power semiconductor modules collectively form a generator inverter for driving a first electric motor; and the second half-bridge switches of the at least three power semiconductor modules collectively form a motor inverter for driving a second electric motor.
21. An electric vehicle comprising an electric drive system according to claim 20.
22. A hybrid electric vehicle comprising an electric drive system according to claim 20.
23. A stack unit, comprising: a plurality of power semiconductor modules, at least some of which being according to any of claims 1 to 19; and a plurality of coolers stacked with the power semiconductor modules along a stacking direction, wherein each of the power semiconductor modules is thermally coupled to at least one of the coolers.
24. A method of manufacturing a power semiconductor module, comprising: attaching a first half-bridge switch and a second half-bridge switch between opposing first and second substrates, wherein the first substrate comprises a first insulating layer and a first patterned conductive layer arranged on a surface of the first insulating layer which faces the half-bridge switches, and the second substrate comprises a second insulating layer and a second patterned conductive layer arranged on a surface of the second insulating layer which faces the half-bridge switches, and wherein the attaching comprises: electrically connecting a high side terminal of a first high side device of the first half-bridge switch and a high side terminal of a second high side device of the second half-bridge switch to a first conductive track of the first patterned conductive layer; electrically connecting the first conductive track to a DC positive power terminal of the power semiconductor module; electrically connecting a low side terminal of a first low side device of the first half-bridge switch and a low side terminal of a second low side device of the second half-bridge switch to a second conductive track of the second patterned conductive layer; electrically connecting the second conductive track to a DC negative power terminal of the power semiconductor module; and electrically connecting the first half-bridge switch and the second half-bridge switch in parallel between the DC positive power terminal and the DC negative power terminal; and encapsulating the first half-bridge switch and the second half-bridge switch by an encapsulant.