EP3384533A1 - Procédé de production d'une surface de mise en contact plane libre pour nanostructures semi-conductrices - Google Patents

Procédé de production d'une surface de mise en contact plane libre pour nanostructures semi-conductrices

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Publication number
EP3384533A1
EP3384533A1 EP16798073.9A EP16798073A EP3384533A1 EP 3384533 A1 EP3384533 A1 EP 3384533A1 EP 16798073 A EP16798073 A EP 16798073A EP 3384533 A1 EP3384533 A1 EP 3384533A1
Authority
EP
European Patent Office
Prior art keywords
layer
nanostructure
nanostructures
substrate
hsq
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP16798073.9A
Other languages
German (de)
English (en)
Inventor
Sebastian HEEDT
Julian GERHARZ
Thomas SCHÄPERS
Detlev GRÜTZMACHER
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Forschungszentrum Juelich GmbH
Original Assignee
Forschungszentrum Juelich GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Forschungszentrum Juelich GmbH filed Critical Forschungszentrum Juelich GmbH
Publication of EP3384533A1 publication Critical patent/EP3384533A1/fr
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66469—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET

Definitions

  • the invention relates to a novel method for planarizing nanostructures, in particular nanowires, for example, prior to electrical contacting.
  • the invention further relates to a method for vertically stacking a plurality of nanostructures, that is to say for producing one or more layers with embedded nanowires or nanowire networks or other nanostructures which can be electrically contacted.
  • the aforementioned method has the advantage that individual nanowires can be planarized by embedding in an oxide layer (FIG. 2).
  • the etching time has to be adapted exactly and, between several etching steps, the etching progress is to be controlled in an elaborate manner by atomic force microscopy.
  • the reactive ion etching / plasma etching may under certain circumstances adversely affect the nanostructures / nanowires (in particular their surface properties).
  • CMP chemical mechanical planarization
  • HSQ has already been used for layer transfer [4, 5].
  • the method uses HSQ to bond two wafers by wafer bonding.
  • the purpose of the HSQ is not to transfer or planarize nanostructures, but to allow only a connection between a silicon wafer and a layer of GaN.
  • the starting substrate is not removed by dissolving a contact layer (eg PMMA) in a solvent, but the complete transfer wafer (ie the starting substrate) is removed by reactive ion etching.
  • a contact layer eg PMMA
  • the nanowire is vapor-deposited with aluminum, and with an adhesive the transfer wafer with the aluminum layer is glued onto another Si wafer. Since the bond between alumina When silicon and silicon are only weak, the glued-on wafer with the aluminum layer and the nanowires embedded therein can be detached by mechanical shearing forces. The nanowires are in the aluminum layer and this is flat on the surface, since it originally formed the interface with the silicon. This method also leads to a planarization of nanowires. However, there the nanowire is embedded in a metallic electrode. This shorts the nanowire electrically short along its growth axis and thus does not allow application in the sense of the present invention.
  • the object of the invention is to provide a method for planarizing nanostructures, in particular nanowires, which overcomes the previous disadvantages of the prior art.
  • electronic functionality is to be ensured within the layer.
  • the invention relates to a method for planarizing nanostructures, in particular nanowires.
  • a method for planarizing nanostructures in particular nanowires.
  • Such a method can advantageously be used as a preliminary step for an electrical contacting of nanostructures and also permits a vertical integration of nanostructures, in particular of nanowires or nanowire networks.
  • nanostructure can be understood, for example, a single nanowire or a network of connected nanowires.
  • Suitable nanostructures include, for example, InN, InAs, InSb, Si, Ge or Au.
  • CNTs carbon nanotubes
  • rene eg C 6 o
  • graphene flakes graphene nanoribbons
  • MoS 2 2 Al
  • Ag ZnO
  • CdS, CdSe, Bi 2 Te 3 , Bi 2 Se 3 , Sb 2 Te 3 or HgTe as material suitable for a nanostructure.
  • mixtures of the abovementioned compounds are also conceivable.
  • planarization is understood to mean both the production of a planarized surface, by means of which electrical contacting with, for example, titanium / gold or ferromagnets is possible. On the other hand, this also means the alignment of different sized nanostructures at one level.
  • the possibility of vertical layering is, inter alia, a central aspect of the invention.
  • the invention is based on the idea, unlike Sheng et al. [6] does not apply the nanostructures directly to a transfer substrate (starting substrate), which must be mechanically separated from the nanostructure at a later time.
  • the nanostructures are therefore not arranged directly on a transfer substrate, for example a Si wafer, but instead on a lacquer layer which is readily dissolvable in a solvent and has been previously applied to the transfer substrate.
  • position markers defined first by means of electron beam lithography and subsequently etched into the starting substrate can be generated in the substrate in order to later position the nanowires / nanostructures.
  • stray markers z. B. realized as a negative marker, are shown in Figure 3.
  • suitable starting substrates include substrates comprising Si, GaAs, InP, Ge, InAs, InGaAs, AlGaAs, GaN, as well as quartz, sapphire, diamond or even metals.
  • Si and other elemental semiconductors of the fourth main chemical group, compound semiconductors of the third and fifth, and the second and sixth main chemical groups are suitable as substrates.
  • the substrate surfaces should be expediently flat and undergo conventional cleaning steps of clean-room technology before use.
  • the surfaces may also have oxide or nitride layers or be combined with layers of boron nitride and / or graphene.
  • a lacquer layer which can be removed or dissolved by a solvent, is applied to the previously cleaned surface in a planar manner on a starting substrate (transfer substrate).
  • a lacquer layer suitable for this purpose can in particular be made from polymethyl methacrylate (PMMA) or a polymer from methyl methacrylate and methacrylic acid (copolymer PMMA / MA) or from optical photo resists such as AZ 5214 E, AZ P4620, AZ 4562, AZ nLOF 20xx or the like, consist.
  • the required layer thickness of the lacquer layer can be a few nanometers, but can also be in the range of a few micrometers.
  • Advantageous lacquer layer thicknesses are between 50 and 200 nm.
  • the application of the lacquer layer can be effected by methods already known, such as spin-coating, dripping or brushing.
  • the applied paint is first baked together with the transfer substrate in order to allow the outgassing of any solvent present, such as ethyl lactate, from the paint layer.
  • any solvent present such as ethyl lactate
  • a temperature increase to about 180 ° C can be made.
  • the time for outgassing is usually between 5 and 30 minutes, depending on the layer thickness of the paint layer, but is usually not critical. Temperatures well above 200 ° C can adversely affect the curing of the paint. For example, with a paint layer thickness of 120 nm, outgassing of 10 minutes at a maximum temperature of 180 ° C is completely sufficient.
  • the paint in several steps, d. H. be applied in several layers, which may optionally include different types of paint.
  • the heating for the outgassing of any existing solvents is typically carried out after each individual applied layer.
  • an additional adhesion promoter layer is applied to the lacquer.
  • a suitable primer layer could include, for example, hexamethyldisilazane (HMDS).
  • the adhesion promoter layer can also be dissolved or dissolved during later treatment with a solvent. But this is not mandatory.
  • an applied adhesion promoter layer has only a very small layer thickness, in particular it is advantageously formed as a monolayer on the lacquer layer.
  • the application of the optional adhesion promoter layer can be carried out by methods already known, such as chemical vapor deposition of HMDS.
  • the nanostructures are or are then applied to the paint or adhesion promoter layer.
  • This can be done as known from the literature in the usual way.
  • This includes, for example, the mechanical transfer using a clean room cloth or by a method in which the wafer with the (PMMA) lacquer layer as the starting substrate is first brought into contact with a growth substrate on which the nanostructures are epitaxially produced, or even the Applying the nanostructures to the starting substrate by means of a solvent, such as isopropanol, in which the solvent is subsequently evaporated.
  • a solvent such as isopropanol
  • a spin-on glass spin-on glass, SOG
  • SOG spin-on glass
  • a flowable oxide is applied to the lacquer or adhesion promoter layer with the arranged nanostructures in such a way that the nanostructures are completely or partially embedded in the carrier matrix.
  • SOG spin-on glass
  • a flowable oxide is applied to the lacquer or adhesion promoter layer with the arranged nanostructures in such a way that the nanostructures are completely or partially embedded in the carrier matrix.
  • Conceivable and suitable as a carrier matrix for embedding the nanostructures would also be other flowable dielectrics, besides oxides, for example, nitrides.
  • HSQ hydrogen silsesquioxane
  • quartz Si0 2
  • hydrogens H 8 Si 8 0 12 ao
  • HSQ paints are usually baked at about 90 ° C to evaporate solvent.
  • the HSQ coating XR-1541 is used by Dow Corn- ing ®.
  • the HSQ is dissolved in the solvent methyl isobutyl ketone (MIBK).
  • the carrier matrix can be generated by Dow Corning ® or other flowable oxides 1x and 2x exemplary Similar coatings, such as paints the HSQ FOx ®.
  • HSQ coatings are characterized by optical transparency and a high resolution of about 6 nm as an electron beam-sensitive negative resist for electron beam lithography. If this property is not required in subsequent optional steps, other variants are also possible, for example using polymers which serve as spin-on-glass. This includes an example polymethyl the brand Honeywell ACCUGLASS ® or silicate-based spin-on glass which may also serve the purpose of planarizing nanostructures.
  • the application of the carrier matrix can be carried out in one step or in several steps.
  • the typical layer thickness of an applied lacquer layer is about 180 nm for z.
  • By using multiple layers, or other similar coating materials such as FOx ® 1x and 2x advantageously layer thicknesses in the micrometer range can be achieved.
  • the required layer thickness of the carrier matrix to be applied depends inter alia on the cross section of the nanostructures used. If the thickness of the nanostructures makes this necessary, the spin coating and the heating of the lacquers can be repeated iteratively until the nanostructure is optimally confined by the HSQ or SOG.
  • the method according to the invention may be carried out prior to Waferbonden a prior structuring, in the z. B. cache-shaped structures are written by electron beam lithography or EUV lithography in the HSQ layer (see Figure 3).
  • a developer z. MF® CD-26, MF®-24A, AZ 326MIF or AZ 400K, which do not attack or develop the lacquer layer under the nanostructures.
  • the lacquer layer under the nanostructures is designed as a positive lacquer for electron beam lithography (such as PMMA) and the carrier matrix as a negative lacquer for electron beam lithography (such as HSQ).
  • the structured HSQ layer advantageously reduces the contact area to the PMMA, which facilitates later detachment, since the solvent can better attack the PMMA.
  • these structures also advantageously permit improved escape of hydrogen and any solvent residues between the wafers.
  • through-contacts so-called vias, can be lithographically defined before wafer bonding.
  • the then exposed areas of the underlying (organic) lacquer layer can be removed with the aid of an oxygen plasma. This may, similar to the patterning of the HSQ layer described above, allow for easier penetration of the solvent between the two wafers to dissolve the resist layer. The escape of possible gaseous reaction products during wafer bonding is also facilitated.
  • the HSQ layer is then connected as a transfer layer with the embedded nanostructures to a second substrate (target substrate).
  • target substrate The two substrates are pressed together and baked at temperatures above 200 ° C.
  • the substrates were pressed together with about 1.38 MPa overpressure for about 10 min.
  • RTP Rapid Thermal Processing
  • the target substrate is also coated with a thin HSQ layer before the two wafers are pressed together and baked at 90 ° C. for a few minutes.
  • the quality of the HSQ layer between the two wafers can be further enhanced by rapid thermal processing (RTP) in an RTP oven to complete the chemical conversion of the HSQ layer. It is important that the dissolvable (PMMA) coating does not harden. However, complete conversion of the HSQ layer is not advantageous for many applications since, without this step, the HSQ or SOG can ensure the lowest possible electrical capacitance between the layers of a multilayer.
  • RTP rapid thermal processing
  • the lacquer layer or adhesion promoter layer located underneath the layer with the embedded nanostructures can then advantageously be easily dissolved or dissolved under the action of a suitable solvent, for example acetone.
  • a suitable solvent for example acetone.
  • the nanostructures or nanowires, which were previously arranged precisely at the interface between the paint or adhesion promoter and the carrier matrix, are thus (directly) directly on the new surface of the second substrate.
  • the HSQ lacquer which is actually soluble in a solvent is removed by the process steps preceding the delamination, such as, for example, electron beam lithography or EUV lithography and / or a thermal treatment, for example. B. modified in an RTP oven so that it can no longer be in the peeling process by a solvent or dissolve.
  • the two substrates which have been brought into contact with each other can be treated with the lacquer layer located therebetween before dissolving the lacquer layer in an isotropic oxygen plasma.
  • This dissolving of the layer can facilitate the dissolution of the lacquer layer in a solvent.
  • the lacquer layer can advantageously be dissolved with the aid of a suitable solvent, and the substrate can thus be gently removed from the previously arranged nanostructures without attacking the HSQ matrix in the process.
  • Gentle means in particular, without mechanical influence and without high temperature load.
  • a suitable solvent for dissolving or dissolving the lacquer layer for example, acetone and acetone-containing solvents and cyclopentanone and dimethyl sulfoxide (DMSO) or mixtures thereof may be mentioned.
  • DMSO dimethyl sulfoxide
  • This gentle removal can ensure that the nanostructures / nanowires - in particular their surface properties - are not adversely affected.
  • the nanostructures lie on the plane surface of the HSQ layer, which previously formed the interface with the lacquer layer. Since the surface of the HSQ layer is flat, the nanostructures arranged on it are automatically aligned flat on this plane, regardless of their size or their cross-section.
  • nanostructures in particular also with different thicknesses and / or geometries, can be arranged flat on the surface of the transfer layer embedding the nanostructures after removal of the varnish.
  • the nanostructures can also be partially embedded embedded in the paint. This can be done by applying the nanostructures and reheating, in which the nanostructures then partially sink into the lacquer (see FIG. 6). This could possibly be done by mechanical pressure. During the subsequent dissolution of the lacquer layer, the nanostructures do not then close off with the surface but at least partially protrude beyond it. Such an arrangement may in particular dere be advantageous if an electrical contacting or metallization of round nanowires requires a sufficient contact surface (see Figure 2). Although it can not be spoken of a planarization in the strict sense, this particular embodiment should still be included in the invention.
  • the method according to the invention for planarization also works in particular for nanostructures which have a different size and / or geometry. Unlike in the known methods [1, 2], in which the ⁇ tzfort suits must be extensively checked, the removal of the substrate by means of a solvent is completely uncritical, since except for the lacquer layer to be dissolved or optionally the adhesive layer none of the other materials, ie neither the substrates, nor the nanostructures or the HSQ or glass layer, are attacked by the solvent. In addition, the nanowires in the non-conductive carrier matrix are not electrically short-circuited [6].
  • the method according to the invention makes it possible in a simple manner to planarize / laminate nanostructures and to subsequently facilitate electrical contacting.
  • the steps of the planarization method according to the invention can advantageously also be repeated iteratively in order to achieve a vertical integration of the nanostructures or nanowires.
  • Layer by layer multiple layers of horizontally aligned nanowire networks can be constructed.
  • the method according to the invention has the advantage that the transfer substrate used is not ablated or destroyed, but remains completely intact after detachment with the aid of a solvent, and for further planarizations or for further iterations with vertical integration of several nanostructures. or nanowire layers is available.
  • the method according to the invention is thus particularly suitable for the production of nanowire components for nanowire-based logic, in particular novel, reconfigurable logic [8].
  • ferromagnetic metal contacts such as Co, Ni or Permalloy z. B. by means of molecular beam epitaxy are evaporated on a flat surface.
  • the plane must be as level as possible, otherwise the magnetization of the ferromagnet will be prevented by the Application of an external magnetic field between two discrete orientations back and forth can be switched (see Figure 1b).
  • the inventive method can find application in the field of conventional micro- and nanoelectronics.
  • the focus here is on the vertical integration of semiconductor nanostructures in computer chip processing (see FIG. 11).
  • the process of the invention can be easily scaled up and is transferable to larger substrates.
  • the transfer Due to the possibility of being able to selectively convert HSQ into the oxide matrix by electron beam lithography and development, the transfer also produces free-floating nanostructures which only come into contact with the substrate at the ends. This can be of great importance for use in gas sensors, as this allows the entire nano wire surface to come into contact with the gas to be detected.
  • water splitting components would benefit from the entire wire surface available for chemical reactions while allowing electrical contact at the wire ends.
  • nanowires or nanostructures exposed on one side may be of importance.
  • the resulting channels in the field of micro- and nanofluidics may play a role. This could be z.
  • the nanowires embedded in the oxide matrix can be used as a diode array.
  • Metallic nanowires integrated into the oxide matrix could also be used as an antenna arrangement.
  • the buried nanowires could also serve as gate electrodes that electrostatically control graphene layers or similar two-dimensional layers deposited on the planarized surface.
  • buried contacted nanowires would act as control electrodes, whereupon the graphene layer would be deposited. Subsequently, no further lithography step would be necessary to contact the control electrodes.
  • Figure 1 (a) Scanning electron microscope photograph of a conventional vapor deposition of nanowires with thin metal layers with breaks in the electrical contacts due to shading effects.
  • Figure 2 Scanning electron micrograph of a planarized and contacted
  • Figure 3 Example layout for a conventional starting substrate.
  • Figure 4 Example layout for a conventional target substrate.
  • Figure 5 Schematic representation of an embodiment of the method according to the invention. In the upper part: process steps according to the invention for the planarization of nanostructures. In the lower part: optional further process steps for the vertical integration of several nanostructure layers.
  • FIG. 6 Scanning electron microscope photograph of an indium nitride nanowire according to FIG.
  • PMMA polymethyl acrylate
  • FIG. 7 Optical microscopy image according to the invention of selectively developed cache-shaped HSQ structures on the PMMA layer with a typical edge length of 1.44 mm before wafer bonding.
  • FIG. 8 Optical microscopy image of a starting substrate on a
  • Target substrate transmitted HSQ tile.
  • Figure 9 Representation of examples of successfully transferred to a target substrate
  • Nanowires embedded in an oxide matrix Nanowires embedded in an oxide matrix.
  • FIG. 10 Illustration of the advantages of the method according to the invention for planarizing nanostructures of different sizes.
  • FIG. 11 Illustration of the advantages of the method according to the invention for the vertical integration of nanostructures with plated-through holes.
  • FIG. 1 (a) the disadvantageous result frequently encountered with conventional vapor deposition of nanowires with thin metal layers is that an interruption in the electrical contacts occurs due to shading effects.
  • ferromagnetic contacts such as of cobalt
  • significant disturbances of the homogeneity of the magnetization which is mandatory for many components of spintronics, and in Figure 1 (b) is shown.
  • FIG. 1 (b) the calculated local magnetization is shown in cross-section along a cobalt contact, which is laid around the circular nanowire cross-section here by conventional vapor deposition (without prior planarization of the nanowire).
  • the specified external magnetic field is applied along the main axis of the cobalt strip, ie perpendicular to the nanowire and parallel to the substrate.
  • FIG. 2 shows a photograph of an indium nitride nanowire which has been planarized and contacted by a method described in [2].
  • the nanowire was completely embedded in HSQ and then re-exposed by means of reactive dry etching, so that it could be electrically contacted at the top.
  • the metal strip of cobalt exhibits only a slight curvature and no interruptions, as in FIG. 1 (a). Immediate switching of the magnetization direction between two discrete states without intermediate domain formation at the contact point to the nanowire, as shown in FIG. 1 (b), thus becomes possible.
  • FIG. 3 and 4 show exemplary designs for a starting substrate (FIG. 3) and for a target substrate (FIG. 4). Shown are the areas with the HSQ tiles, the positioning markers and the markers for electron beam lithography (here negative markers).
  • FIG. 5 the method steps of an exemplary embodiment of the method according to the invention are shown schematically at point A in the upper area.
  • a 2-inch silicon wafer, ie the starting substrate AS (1)) is first cleaned with acetone, isopropanol, piranha (dilution with water in the ratio 1: 1) and 1% hydrofluoric acid.
  • Optical lithography and reactive ion etching produce negative markers for electron beam lithography.
  • the wafer is then baked for at least 10 minutes at 180 ° C so that the paint does not further degas solvent in subsequent steps.
  • nanowires are mechanically transferred to the PMMA layer.
  • the starting substrate can be brought into contact with the growth substrate on which the nanostructures were epitaxially produced.
  • nanostructures can also be applied in solution, for example in isopropanol, to the starting substrate.
  • the solvent then evaporates while the nanostructures remain there.
  • the solvent used for this purpose should be chosen so that the dissolvable lacquer layer (6) is not attacked, which is later in another Amsterdamsmit- tel should be resolved.
  • a targeted transfer by means of micromanipulators or similar methods are possible. In the present case, the transfer was done mechanically with a clean room towel.
  • the transferred nanowires are illustrated in FIG. 5 by way of example in circular cross-section.
  • the spin-on glass or the flowable oxide (HSQ (3)) is applied with a paint spinner, which completely encloses the nanowires.
  • FIG. 5 structures can be seen in FIG. 5 which were written into the HSQ by means of electron beam lithography. Such written by electron beam areas change stoichiometrically, so that an oxide matrix is formed, in which the nanowires or nanostructures are embedded.
  • the converted HSQ can advantageously be developed selectively (using developer MF® CD-26) without attacking the PMMA. By means of reactive ion etching, the selectively developed regions can be transferred into the PMMA by an oxygen plasma. Such a procedure allows for better outgassing in wafer bonding and improved peel since solvent can more easily penetrate between the bonded wafers.
  • a second pre-cleaned 2-inch wafer as the target substrate (ZS (5)) is structured with negative markers for electron beam lithography (see FIG. 4) in order to enable further processing after the planarization process, ie the actual electrical contacting. It is also lacquered (HSQ (4)), briefly baked to evaporate the solvent, and connected in an imprint process upside down with the starting substrate.
  • HSQ (4) lacquered
  • the same systems used for nanoimprinting can be used for wafer bonding.
  • the two wafers (AS (1) and ZS (5)) can be dissolved in acetone from each other, wherein the PMMA layer (PMMA (6) below the nanowires (2) is thereby dissolved.
  • the now planarized nanowires can be electrically contacted by defining electrodes by means of electron beam lithography, which are subsequently metallized.
  • the previously prepared target substrate is re-lacquered with the nanostructures (2) embedded in the HSQ (3) layer and the electrodes arranged thereon ((HSQ (7)).
  • a further starting substrate (AS (1)) is coated with PMMA (PMMA (9)) and further nanostructures (8) are applied thereon. These are completely enclosed by another spin-onable glass or a flowable oxide (HSQ (10)) and this layer is optionally structured by means of electron beam lithography. Both substrates thus produced are connected by wafer bonding and the starting substrate is then removed as in point A.
  • FIG. 6 shows the scanning electron micrograph of an indium nitride nanowire on a PMMA lacquer layer. The nanowire was transferred to the lacquer layer using a clean room cloth. It can be clearly seen that the nanowire has sunk very easily into the PMMA layer.
  • An HSQ tile with nanowires embedded in the target substrate can be seen in the appendix in FIG.
  • FIG. 7 shows an optical microscopy image of the selectively developed HSQ tiles on the PMMA layer. In the HSQ tiles in Figure 7, the embedded indium nitride nanowires are not visible. The edge length of the illustrated tile is 1.44 mm.
  • the HSQ tile in the lower left half of the image has been successfully transferred from the starting substrate to the target substrate.
  • the nanowires embedded in the oxide matrix are located directly underneath the HSQ surface after dissolving the starting substrate already here by dissolving the PMMA layer.
  • the upper right half of the picture shows previously etched negative markers for subsequent electron beam lithography.
  • the applied HSQ Layers advantageously do not hinder the subsequent electron beam lithography steps.
  • the starting substrate can advantageously be used for further process steps in order to transfer further oxide layers with nanostructures / nanowires embedded therein.
  • FIG. 9 shows scanning electron micrographs in which nanowires (light) embedded in an oxide matrix (dark gray) can be seen which were previously successfully transferred from a starting substrate to a target substrate with the aid of the method according to the invention.
  • FIGS. 10 and 11 show in illustrations how nanostructures can be electrically contacted after a planarization according to the invention.
  • FIG. 10 illustrates the aspect of different sizes of the embedded nanostructures. For all nanostructures an optimal planarization takes place, no matter what the size, so that electrical contacts and in particular magnetic electrodes are not impaired by shading effects in their function.
  • the method according to the invention advantageously permits vertical integration with plated-through holes.
  • the transfer of nanostructures embedded in the oxide matrix can be repeated iteratively.
  • vias so-called vias
  • Layer by layer multiple layers of nanowire networks can be constructed iteratively.
  • selective etching steps with a resist mask may be performed between two layers (depending on the specific embodiment of the method according to the invention) in order to guide vias through the layer.

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  • Engineering & Computer Science (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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  • Thin Film Transistor (AREA)
  • Laminated Bodies (AREA)

Abstract

L'invention concerne un procédé de production d'une surface de mise en contact plane libre pour des nanostructures semi-conductrices, selon lequel au moins une nanostructure (2) est agencée sur la surface d'un substrat de transfert (1), une première couche (3) est appliquée sur la même surface du substrat de transfert (1) et incorpore la ou les nanostructures (2), et un second substrat (5) est appliqué sur ladite première couche (3), après quoi le substrat de transfert (1) est séparé de la première couche (3), de sorte que la ou les nanostructures (2) incorporées dans cette dernière présentent une surface plane libre. Selon l'invention, avant l'application de la ou des nanostructures (2) sur le substrat de transfert (1), une couche supplémentaire (6) soluble au moyen d'un solvant est appliquée sur la surface du substrat de transfert (1) et le substrat de transfert (1) est enlevé de la première couche (3) au moyen d'un solvant. Cette solution permet une planarisation/stratification de nanostructure, et facilite ensuite la mise en contact électrique. Une application itérative des étapes du procédé permet de créer avantageusement des systèmes multicouches, par exemple des réseaux de nanofilaments orientés horizontalement.
EP16798073.9A 2015-12-02 2016-10-22 Procédé de production d'une surface de mise en contact plane libre pour nanostructures semi-conductrices Pending EP3384533A1 (fr)

Applications Claiming Priority (2)

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DE102015015452.4A DE102015015452A1 (de) 2015-12-02 2015-12-02 Verfahren zum Planarisieren von Nanostrukturen
PCT/DE2016/000379 WO2017092723A1 (fr) 2015-12-02 2016-10-22 Procédé de production d'une surface de mise en contact plane libre pour nanostructures semi-conductrices

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EP (1) EP3384533A1 (fr)
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WO (1) WO2017092723A1 (fr)

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DE102015015452A1 (de) 2017-06-08
WO2017092723A1 (fr) 2017-06-08
JP6845850B2 (ja) 2021-03-24
CN109075189A (zh) 2018-12-21
JP2019504465A (ja) 2019-02-14
CN109075189B (zh) 2022-03-25
US10714568B2 (en) 2020-07-14

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