Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M3/00—Conversion of analogue values to or from differential modulation
  • H03M3/30—Delta-sigma modulation
  • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
  • H03M3/358—Continuously compensating for, or preventing, undesired influence of physical parameters of non-linear distortion, e.g. instability
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M3/00—Conversion of analogue values to or from differential modulation
  • H03M3/30—Delta-sigma modulation
  • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
  • H03M3/494—Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems
  • H03M3/496—Details of sampling arrangements or methods
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M3/00—Conversion of analogue values to or from differential modulation
  • H03M3/30—Delta-sigma modulation
  • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
  • H03M3/462—Details relating to the decimation process
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M3/00—Conversion of analogue values to or from differential modulation
  • H03M3/30—Delta-sigma modulation
  • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators

Definitions

• the present application relates to the field of analog-to-digital converters, and more particularly to sigma-delta converters.
• a sigma-delta converter typically comprises a sigma-delta modulator and a digital filter.
• the analog signal to be digitized is input to the modulator, and is sampled by the latter at a relatively high frequency (relative to the maximum frequency of the input signal), called the oversampling frequency.
• the modulator produces, at the oversampling frequency, binary samples representative of the input analog signal.
• the output bit stream of the sigma-delta modulator is processed by the digital filter which extracts a numerical value on N-bits (N being the quantization resolution of the sigma-delta converter), representative of the input signal.
• the sigma-delta modulator typically consists of a loop comprising at least one analog integration circuit, a 1-bit analog-digital converter, a 1-bit digital-to-analog converter, and a subtracter.
• the input analog signal is inputted to the integration circuit, which samples it at the oversampling frequency and supplies analog samples at this same frequency which are representative of the difference between the input signal and an analog signal. of feedback.
• the analog output samples of the integration circuit are digitized by the 1-bit analog-to-digital converter (typically a comparator).
• the binary samples thus obtained form the output signal of the modulator. These binary samples are furthermore converted into analog samples by the 1-bit digital-to-analog converter, the analog signal thus obtained forming the feedback signal of the modulator.
• the analog integration circuit may include a single analog integrator, or multiple cascaded analog integrators. It may also include one or more subtractors, one or more summers, and / or one or more weighting coefficients.
• the number of analog integrators generally defines the order of the sigma-delta modulator. The higher the p-order of the modulator, the smaller the number of samples required to obtain an N-bit output digital value (at identical quantization noise levels). In return, the sigma-delta modulators are all the more complex to realize that their order is high (delicate stabilization).
• the digital filter comprises, according to the structure of the modulator, one or more digital integrators (generally at least as much as an analog integrator in the modulator), for example counters, and carries out a filtering function for extracting the useful information from the modulator.
• bit stream produced by the sigma-delta modulator More particularly, the sigma-delta modulator formats the useful signal through its STF signal transfer function, and the quantization noise through its NTF noise transfer function.
• the STF is the transfer function linking the analog input signal to be digitized to the output signal of the modulator
• the NTF is the transfer function linking the quantization noise introduced by the 1-bit analog-to-digital converter from the modulator to the signal. output of the modulator.
• the NTF makes it possible to push the quantization noise outside the band of interest (in which the signal is located).
• the digital filter is designed to extract the signal in the frequency bands where the quantization noise attenuation by the NTF is high (ie say where the signal is located).
• an embodiment provides a sigma-delta converter comprising a sigma-delta modulator adapted to provide a sequence of binary samples representative of an analog input signal to be digitized, the delivery of a binary sample of the sequence of binary samples being taken at the end of a modulator operating cycle, a conversion phase comprising a number of cycles necessary to produce a digital output value of the converter, the modulator comprising at least one analog filter receiving an analog signal internal input from the analogue input signal, in which the contribution to the analog filter of the internal analog signal at a given cycle is smaller than the contribution to the analog filter of the internal analog signal in the previous cycle, the contributions to the different cycles being governed by a first predetermined law depending on the rank of the cycle in the conversion phase.
• the analog filter can be of different types, for example: high pass, low pass, pass band or integrator.
• the converter further comprises a digital filter adapted to process the binary output samples of the modulator, the digital filter receiving an internal digital signal in which the contribution to the digital filter of the digital signal internal to a given cycle is more weak that the contribution to the digital filter of the digital signal internal to the previous cycle, the contributions to the different cycles being governed by a second predetermined law depending on the rank of the cycle.
• the analog filter and the digital filter are advantageously of the same type.
• the first and second predetermined laws are identical.
• the sigma-delta modulator comprises an integrating analog circuit, a 1-bit analog-to-digital converter, and a feedback loop, and the internal analog signal to the modulator is a signal internal to the analog circuit. integration.
• the analog integration circuit comprises several analog cascaded filters.
• the 1-bit analog-to-digital converter comprises a comparator, the analog input signal to be digitized is applied to an input node of the integration analog circuit, and a constant potential is applied to a node. application of a comparison threshold potential of the comparator.
• the 1-bit analog-digital converter comprises a comparator, the analog input signal to be digitized is applied to an application node of a comparison threshold potential of the comparator, and a constant potential is applied to an input node of the analog integration circuit.
• the first predetermined variable law is applied to one or more internal analog signals to the modulator so that all the analog signals which add or subtract from the modulator are at the same scale with respect to the first law.
• the analog signals can vary in the same range of amplitude for a given range of amplitude of the input analog signal.
• the digital filter comprises at least one digital integrator, and the digital signal internal to the digital filter is an input signal of one of the at least one digital integrator.
• the digital filter comprises several cascaded digital integrators.
• the first law comprises at least one decay phase during a conversion phase of an input analog signal into a digital output signal by the converter.
• the first law is an exponentially decreasing law depending on the rank of the cycle.
• the first law is constant during a first part of the conversion phase, and decreases exponentially according to the rank of the cycle during a second part of the conversion phase.
• the first law is constant during a third part of the conversion phase.
• the input analog signal is weighted by an input coefficient of the modulator, the coefficient being non-zero during a first part of the conversion phase, followed by a second part of the conversion phase during which the coefficient is zero .
• the first law is dynamically modified according to predetermined rules during the conversion phase.
• the first law is applied with a phase shift in the number of cycles at the level of the sigma-delta modulator and at the level of the digital filter.
• At least two distinct laws are applied to internal analog signals separate from the modulator.
• the first variable law is applied by varying a variable capacity during the conversion phase.
• variable capacity comprises a plurality of switchable capabilities connected in parallel, whose values respectively correspond to the values obtained by dichotomy from a basic capacity value, the sum of the values of the switchable capacities being equal to the value of the basic capacity.
• the converter comprises, at the input of the filter, a device for weighting the internal analog signal received by the analog filter applying a variable weighting coefficient ⁇ , a function of the rank k of the cycle. During the conversion phase, at least two distinct coefficients Bk-1 and ⁇ k are applied, respectively for two successive cycles of rank k-1 and k, with 3k-1> ⁇ ⁇
• variable weighting coefficient ⁇ k is decreasing with the rank k of the cycle.
• said at least one integrating analog filter is equivalent to a theoretical circuit comprising a summator between the value of an analog signal received at the cycle k and an internal signal of the filter corresponding to a multiplication by a coefficient a of the signal output of the analog filter obtained at cycle k-1.
• at least one value of the coefficient a greater than strictly 1 is applied for at least one cycle.
• the coefficient a is increasing with the rank k of the cycle.
• the converter is configured so that during the conversion phase, the sequence of the following operations is applied at least once:
• N is greater than 1 and less than the number OSR of cycles necessary to produce a digital output value of the converter, after an initial cycle, a decreasingly variable weighting coefficient ⁇ ] ⁇ is applied to the internal analog signal,
• the coefficient a of the analog filter is strictly greater than 1.
• M is equal to 1 and the coefficient of the analog filter takes a value greater than or equal to 1 inverse of the weighting coefficient ⁇ applied to the cycle N, so that the output signal of the analog filter regains amplitude. of variation corresponding to the amplitude of variation at the initial cycle and the coefficient a is reset at the end of the N + 1-th cycle to recover its value at the initial cycle.
• FIGS. 1A and 1B illustrate, in block form, an example of a sigma-delta converter
• FIG. 2 is a detailed electrical diagram of an exemplary embodiment of the sigma-delta modulator of Figure 1A;
• FIG. 3 is a timing diagram illustrating the evolution, as a function of time, of control signals of the modulator of FIG. 2;
• FIG. 4 is a diagram illustrating the evolution of linearity and noise, as a function of the OSR, in a sigma-delta converter of the type described with reference to FIGS. 1 to 3;
• Figs. 5A and 5B illustrate, in block form, an example of an embodiment of a sigma-delta converter
• Fig. 6 is a diagram illustrating the evolution of linearity and noise, as a function of OSR, in a sigma-delta converter of the type described in connection with Figs. 5A and 5B;
• Fig. 7 is a diagram illustrating the evolution of linearity and noise, as a function of OSR, in another example of a sigma-delta converter of the type described in connection with Figs. 5A and 5B;
• Fig. 8 is a diagram illustrating the evolution of linearity and noise, as a function of OSR, in another example of a sigma-delta converter of the type described in connection with Figs. 5A and 5B;
• Fig. 9 illustrates, in block form, another example of an embodiment of a sigma-delta converter
• Figure 10 illustrates, in block form, another example of an embodiment of a sigma-delta converter
• Fig. 11 is a diagram illustrating the behavior of the sigma-delta converter of Fig. 10;
• FIG. 12 is a circuit diagram of an exemplary embodiment of a circuit for dynamically varying a weighting coefficient of a sigma-delta modulator
• Fig. 13 illustrates, in block form, another example of an embodiment of a first-order sigma-delta converter
• FIG. 14 illustrates an exemplary embodiment of an analog filter that can be implemented in the embodiment of FIG. 13;
• FIGS. 15a and 15b illustrate, in the form of a timing diagram, the evolution, as a function of time, of modulator applied coefficients of the converter of FIG. 13;
• FIG. 16 illustrates in block form a generalization of the example of FIG. 13 to converters of higher order than 1.
• FIGS. 1A and 1B illustrate, in block form, an example of a sigma-delta converter of order 4. More particularly, FIG. 1A represents the sigma-delta modulator of the converter, and FIG. 1B represents the digital filter of FIG. converter.
• the sigma-delta modulator of FIG. 1A comprises an input terminal A1 intended to receive an analog input signal Vin to be digitized, and an output terminal A2 intended to provide a series of binary samples BS representative of the signal Vin.
• the analog input signal to be digitized is constant for the duration necessary to produce a digital output value on N-bits, ie 0SR * TQS, TQSR being the period of over-sampling of the converter.
• the embodiments described below are however not limited to this particular case and can be adapted to the conversion of variable analog signals.
• the modulator of FIG. 1A comprises an integration analog circuit 101 comprising a first input connected to the application terminal Al of the signal Vin, and an output A3 connected to the input of an analog-digital conversion circuit 1.
• bit 103 for example a 1-bit comparator.
• the output of the converter 103 is connected to the output A2 of the modulator, and is further connected by a feedback loop to a second input A4 of the integration circuit 101.
• the input signal Vin and the output signal BS of the modulator are normalized, that is to say that the value 0 of the binary signal BS corresponds to a voltage level equal to the smallest value that the analog signal Vin can take, and that the value 1 of the signal BS corresponds to a voltage level equal to the highest value that can take the signal Vin.
• the feedback loop is a simple conductive track connecting terminal A2 to terminal A4, and the feedback signal is directly signal BS.
• the feedback loop may comprise a 1-bit digital-to-analog converter between the terminals A2 and A4, the signal of feedback then being the output signal of the 1-bit digital-to-analog converter.
• the integration circuit 101 takes an analog sample Vin (k) of the signal d input, and the modulator supplies, at the output of the 1-bit analog-to-digital converter 103, a binary sample BS (k) of the output signal.
• the integration circuit 101 comprises four analog cascade integrators 1a, 2a, 1a3 and 1a and a summing circuit ⁇ .
• Each integrator has an input and an output, and has for example a z / (zl) transfer function, that is to say that, at each cycle, the integrated signal, or output signal of the integrator, is increased by the value of the input signal of the integrator.
• the integrator Ia ⁇ receives on its input a signal equal to the difference between the input signal Vin (k) weighted by a coefficient b-, and the feedback signal BS (kl) weighted by a coefficient .
• the integrator Ia2 receives on its input a signal equal to the output signal of the integrator Ia ] weighted by a coefficient C] _.
• the integrator Ia3 receives on its input a signal equal to the output signal of the integrator Ia2 weighted by a coefficient C2.
• the integrator Ia4 receives on its input a signal equal to the output signal of the integrator Ia3 weighted by a coefficient C3.
• the summing circuit adds the input signal Vin (k) weighted by a coefficient 5, and the output signals of the integrators Ia], Ia2, Ia3 and Ia respectively weighted by coefficients C7, cg, C5 and C4. .
• the output of the summing circuit ⁇ is connected to the output terminal A3 of the circuit 101.
• sigma-delta modulator architectures can be envisaged.
• the described embodiments apply to sigma-delta modulators of order p greater than or equal to 1, in which each of the p analog integrators laj, with j integer ranging from 1 to p, receives on its input.
• a signal equal to the difference between the input signal Vin (k) weighted by a coefficient bj and the feedback signal BS (k1) weighted by a coefficient aj, to which is added, if the rank j of the integrator laj is greater than 1, the output signal of modulator Ia-j _i of preceding rank weighted by a coefficient c j-
• the summing circuit ⁇ adds the input signal Vin (k) weighted by a coefficient p +] _, the output signal of the integrator lap of rank p weighted by a coefficient Cp, and, if p is greater than 1, the output signal or signals of the integrators of rank p-1, with 1 integer ranging from 1 to p-1, respectively weighted by coefficients Cp + ] _.
• the embodiments described can also be applied to modulators further comprising one or more analog feedbacks from the output of an analog integrator to the input of an upstream analog integrator, through a specific weighting coefficient, and / or in which the output of an integrator of rank i is added, through a specific weighting coefficient, to the input of a downstream integrator of rank greater than or equal to i + 2 .
• delays can be introduced between the different stages of the circuit 101, and / or between the circuit 101 and the converter 103.
• the digital filter of a sigma-delta converter generally comprises a digital integrator, or several digital integrators in cascade.
• a sigma-delta modulator of order p is associated with a digital filter comprising a number greater than or equal to p of digital integrators.
• the digital filter comprises four cascaded digital integrators I3 ⁇ 4, I3 ⁇ 4,! 3 ⁇ 4 and I3 ⁇ 4.
• Each digital integrator for example a counter, has an input and an output, and, at each cycle, the integrated signal, or output signal of the integrator, is increased by the value of the input signal of the integrator.
• the first integrator I3 ⁇ 4 receives on its input the output binary signal BS of the sigma-delta modulator of FIG. 1A
• the second integrator I3 ⁇ 4 receives on its input a digital output signal of the integrator! 3 ⁇
• the third integrator! 3 ⁇ 4 receives on its input a digital output signal of the integrator! 3 ⁇
• the fourth integrator Ir.4 receives on its input a digital output signal of integrator I113.
• the filter of FIG. 1B performs a low-pass type function for extracting useful information from the bit stream produced by the sigma-delta modulator. More generally, the digital filter extracts the signal at the frequencies where the attenuation of the NTF is greatest. Thus, depending on the structure of the modulator, the digital filter can perform a low-pass function, a band-pass function, or a high-pass function.
• Digital integration is performed at the sigma-delta modulator oversampling frequency.
• the four digital integrators Iiij are simultaneously controlled by the same control signal ⁇ J> CO mp of frequency 1 / TQSR-L output of the last digital integrator In 4 is connected to a normalization block 105 which Its function is to convert the signal supplied by the integrator In 4 into a numerical code over N-bits, N being an integer greater than 1 corresponding to the resolution of the sigma-delta converter.
• the block 105 divides the signal that it receives by a reference value, for example equal to the value that this signal would take for the maximum authorized value of the signal Vin, and supplies on an output terminal A5 of the converter an output value representative of the result of the quantized division on N-bits.
• a reference value for example equal to the value that this signal would take for the maximum authorized value of the signal Vin
• the topology of the digital filter can be modified to approach that of the sigma-delta modulator.
• the normalization circuit 105 can receive a signal equal to the sum of the output signals of the four integrators! 3 ⁇ 4, I3 ⁇ 4,! 3 ⁇ 4 and In 4 .
• the internal digital signals of the digital filter can be weighted by coefficients identical to those of the modulator.
• FIG. 2 is a detailed electrical diagram illustrating a (non-limiting) embodiment of the sigma-delta modulator of FIG. 1A.
• each integrator laj comprises an operational amplifier AO whose input is connected to the output by an integration capacitor Cij.
• the input and output of the operational amplifier respectively form the input and output of the integrator.
• Each integrator laj furthermore comprises, in parallel with its integration capacitance Cij, a reset switch controlled by a gold signal.
• the modulator switches are designated by the same references as their respective control signals.
• the outputs of integrators 1a, 1a, 1a3 and 1a4 are respectively connected to a first electrode of capacitance Col, to a first electrode of capacitance Co2, to a first electrode of capacitance Co3 and to a first electrode of a Co4 capacity, by first, second, third and fourth Old switches.
• the first electrodes of capacitors Col, Co2, Co3 and Co4 are connected to a node R for applying a reference potential, for example equal to the average potential between the high output value DAC U p and the value of low output DA3 ⁇ 4 n of the digital-to-analog feedback converter, respectively by first, second, third and fourth switches ⁇ t> 2d.
• the second electrodes of capacitors Col, Co2 and Co3 are connected to node R respectively by first, second and third switches ⁇ 1.
• the second electrodes of the capacitors Col, Co2 and Co3 are respectively connected to the input of the integrator Ia2, to the input of the integrator Ia3, and to the input of the integrator Ia4, by first second and third switches ⁇ 2.
• the second electrode of the capacitance Co4 is connected to the node R by a fourth switch ⁇ 2, and is further connected to the input A3 of the analog-to-digital converter 103.
• the modulator of FIG. 2 further comprises a capacitance Cs1 whose first electrode is connected to the terminal Al of application of the input signal Vin by a fifth switch Old, and whose second electrode is connected to the input of 1 integrator Ia ⁇ by a fifth switch ⁇ 2.
• the second electrode of the capacitor Cs1 is further connected to the node R by a fourth switch ⁇ 1.
• the first electrode of the capacitor Cs1 is connected to an application node of a potential DACup by an switch Odac, and to an application node of a potential DACdn which is lower than the potential DACup by a switch ⁇ ⁇ 3 ⁇ 4 3 ⁇ .
• the terminal Al of application of the input signal Vin is further connected to a first electrode of a capacitance Cs5 by a sixth switch Old.
• the first electrode of the capacitor Cs5 is further connected to the node R by a fifth switch 02d.
• the second electrode of the capacitor Cs5 is connected to the input node A3 of the analog-to-digital converter 103.
• capacitors Col, Co2 and Co3 are connected to the input node of the analog-to-digital converter 103 respectively by capacitors Cff1, Cff2 and Cff3.
• the 1-bit analog-to-digital converter 103 comprises a comparator 201 and a flip-flop 203.
• the input of the comparator 201 forms the input of the converter 103.
• the output of the comparator 201 is connected to the input of the flip-flop. 203.
• the output of the flip-flop 203 forms the output A2 of the converter 103, supplying the output signal BS of the sigma-delta modulator.
• the output of the comparator 201 goes from a high state to a low state depending on whether the signal applied to the terminal A3 is greater or less than a threshold, for example equal to the reference potential applied to the node R.
• the flip-flop 203 samples the output signal of the comparator 201 and copies it to the output of the modulator at each rising or falling edge of an Ocomp control signal.
• the modulator of FIG. 2 further comprises two AND AND1 and AND2 gates each comprising two binary inputs and one output.
• the inputs of the AND1 gate are respectively connected to the output A2 of the converter 103 and to the control signal 02d, and the inputs of the AND2 gate respectively receive a signal complementary to the output signal of the converter 103 and the control signal 02d.
• the output of the AND1 gate is connected to a control node of the switch Odac, and the output of the AND2 gate is connected to a control node of the switch dac ⁇ .
• Integrators Ia ] _, Ia2, Ia3 and ⁇ the capabilities
• Cs1, Col, Co2, Co3, Co, Cs5, Cff1, Cff2 and Cff3, and the switches ⁇ , ⁇ 2, Old and 02d form the analog integration circuit 101 of the modulator.
• the switches Odac and Odac ⁇ a j; and the AND1 and AND2 gates form the 1-bit digital-to-analog converter of the modulator feedback loop.
• FIG. 3 is a timing diagram illustrating the evolution, as a function of time, of the control signals ⁇ , Old, ⁇ 2, O2d and Ocomp of the modulator of FIG. 2 according to an exemplary control method of this modulator. More particularly, FIG. 3 illustrates the evolution of the signals ⁇ 1, Old, 02, 02d and Ocomp during a TQSR cycle corresponding to an over-sampling period of the modulator.
• the acquisition of an N-bit digital value representative of the input signal Vin may include an initial reset phase of the analog integrators Ia] _, Ia2, Ia3 and Ia4, during which the switches Gold are closed so as to discharge the integration capacities C11, C12, C13 and C14.
• the gold switches can be opened, then the sequence of duration control TGG R illustrated in Figure 3 may be repeated OSR times (in the case of an incremental sigma-delta converter reset between two successive analog to digital conversions or more OSR times if it does s' is no an incremental converter).
• the switches ⁇ 1 and Old are controlled in the closed state (control signals corresponding to state 1 in this example), and the switches ⁇ 2 and ⁇ 2 ⁇ are Controlled in the open state (control signals corresponding to state 0 in this example).
• the sampled signals being voltages, each capacitor stores a quantity of charges proportional to the product of the sampled voltage by the value of the sampling capacitance.
• the signals stored in the capacitors Cs5, Cff1, Cff2, Cff3 and Co4 are summed on the output node A3 of the circuit 101, which constitutes the adder ⁇ of FIG. 1A.
• the weighted summation of the signals stored in these capacities is carried out, the applied weighting resulting from the values of the capacities.
• the signal Ocomp is set high.
• the input signal of the analog-to-digital converter 103 (voltage of the node A3) is quantized on one bit by the converter 103 on the rising edge of the signal Ocomp.
• the binary value of the output signal BS is thus updated.
• ⁇ 1 is set low, and at a time t3 later than time t2, the signal Old is set to low.
• the signals ⁇ 2 and 02d are set high.
• the values of laj integrators,! 3 ⁇ 4! 3 ⁇ 4 Ia4 are updated, c 't that is, the loads sampled in the capacitances Cs1, Col, Co2, Co3 are integrated in the capacitances C11, C12, C13, C14 respectively.
• the feedback is activated, ie the DACup or DACdn signal (depending on whether the signal BS is high or low) is subtracted from the input signal of the capacitance Cs1.
• the signal Ocomp is reset.
• the signal ⁇ 2 is set low, and at a time t7 after t6 the signal 02d is set to low.
• the binary output digital value BS (k) of the modulator obtained at each TQSR cycle is integrated by the digital filter at the modulator's oversampling frequency, for example on the rising edges of the signal ⁇ ⁇ ⁇ ⁇ 3 ⁇ which can be a delayed copy of the signal ⁇ ⁇ (of a delay less than TQSR) ⁇
• the values of the capacitances Cs1, Cs5, Col, Co2, Co3, Co4, Cff1, Cff2, Cff3 set the values of the coefficients b1, b5, a1, c1, C2, C3, C4, C5, cg, C7.
• Cil 2 * Csl / ci
• C12 COI / C2
• Ci3 CO2 / c 3
• Ci4 Co3 / c 4
• Cffl Cs5 ° (c 7 / (C * b 5))
• Cff2 Cs5 * (cg / (c 2 * b 5 ))
• Cff3 Cs5 * (c 5 / (c 3 * b 5 ))
• Co4 Cs5 / b 5 .
• the nonlinearity error is the maximum difference (peak to peak error) over the operating range of the converter between the transfer function of the converter (which corresponds to each value of the input signal analog a digital output code), and the ideal linear transfer function.
• Another important feature of a sigma-delta converter is its output noise B, which can be defined as the average, over the operating range [Vin m -j_ n , Vin max ] of the converter (over a number of conversions significant for each point of the input dynamics), standard deviations of the digital output codes of the converter of each level of the input analog signal.
• FIG. 4 is a diagram illustrating the evolution of the linearity L and of the noise B, as a function of the OSR, in a sigma-delta converter of the type described with reference to FIGS. 1 to 3. More particularly, the curve 401 represents the evolution of the linearity L (in the ordinate on the left) as a function of the OSR (on the abscissa), and the curve 403 represents the evolution of the noise B expressed in LSB (in ordinate on the right) as a function of the OSR.
• N 16 bits.
• an OSR equal to 100 makes it possible to have a linearity value L equal to 15 and a noise level B equal to 0.85 LSB, whereas an OSR equal to 60 only provides linearity L equal to 12 and a noise level B equal to 2, 4 LSB.
• a sigma-delta converter in which, during the acquisition of an N-bit digital value representative of the input analog signal, at least one weighting coefficient of the sigma modulator -delta varies dynamically according to a predetermined law f.
• at least one digital signal internal to the digital filter is further weighted by a predetermined variable law, for example but not necessarily by the same law as that applied in the modulator.
• the weighting coefficient of the modulator to which the law f is applied may for example have an initial value (before modulation by the law f) equal to 1 (to For example, a wire with no apparent coefficient corresponds to a unit coefficient, and one can choose to apply the law f on this coefficient).
• the described embodiments are however not limited to this particular case.
• Figs. 5A and 5B illustrate, in block form, an example of an embodiment of a sigma-delta converter.
• the converter is a fourth-order converter.
• Fig. 5A shows the sigma-delta modulator of the converter
• Fig. 5B shows the digital filter of the converter.
• the sigma-delta converter of FIGS. 5A and 5B has elements in common with the sigma-delta converter of FIGS. 1A and 1B. These items will not be detailed again. Only the differences between the two converters will be explained below.
• the sigma-delta of Figure 5A modulator differs from the sigma-delta of Figure 1A modulator essentially in that, in the modulator of Figure 5A, C2 weighting coefficients, CG, C7 and b ⁇ are modulated by an Act predetermined variable f.
• the value f (k) of the law f is likely to take on a new value.
• the law f (k) is preferably non-binary.
• the OSR values f (k) of the law f are for example stored in a memory of a control circuit (not shown) of the sigma-delta converter.
• An exemplary circuit for applying a law of variable weighting coefficients of the modulator will be described in more detail below in connection with Figure 12.
• the base values (unmodulated by the f act) of coefficients c 2, cg, C7 and b5, as well as the values of fixed coefficients b] _, a ⁇ , C_, C3, C4 and C5, can be determined by the usual methods for determining the coefficients of a sigma-delta modulator, for example according to the sizing rules described in the article entitled “Automatic coefficients design for high-order sigma-delta modulators” by Kuo , TH, Chen, KD, and Chen, JR (Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions, Volume 46, Issue 1), or in the document “Understanding Delta-Sigma Data Converters” (John Wiley & Sons , New York, 2004).
• the digital filter of FIG. 5B differs from the digital filter of FIG. 1B essentially in that, in the filter of FIG. 5B, the variable weighting law f applied to the coefficients C2, cg, C7 and b5 of the sigma-delta modulator is furthermore applied to the digital input signal of the tier 3 digital integrator I113.
• the variable law f is applied at the digital filter with a feed cycle with respect to the modulator, that is, during a TQSR sampling cycle of the sigma-delta converter.
• the weighting value f (k) is applied to the coefficients C2, cg, C7 and b5 of the modulator, the weighting value f (k + 1) is applied to the input signal of the digital integrator I3 ⁇ 4.
• the inventors have indeed found that this shift of a cycle makes it possible to obtain particularly good performances in terms of linearity.
• the described embodiments are however not limited to this particular case.
• the law f may be applied in phase at the modulator and at the digital filter, or at a greater than one cycle advance in the digital filter, or with a delay of one or more cycles in the filter digital.
• the law f can be applied with a phase shift of one or more cycles on coefficients that are distinct from the modulator, or on signals that are distinct from the digital filter. For example, during the same cycle k of a phase of analog-digital conversion of the signal In input, the modulus al of the modulator can be weighted by the value f (k), and the coefficient bl by the value f (k + 1).
• the embodiments described are not limited to the particular example of FIGS. 5A and 5B, in which the sigma-delta converter is a 4-order converter and in which the weighting law f (k) is applied to the coefficients.
• the choice of the modulator coefficient or coefficients on which the weighting law f (k) is applied is preferably such that at least one input coefficient of an analog integrator Iaj of the modulator is modulated by the law f.
• the analog signals added or subtracted from the modulator are on the same scale with respect to the law f (k), that is to say that they have been multiplied or divided. the same number of times (possibly zero) by the law f (k).
• rescaling allows the analog signals to vary in the same amplitude range for a given amplitude range of the input analog signal (Vin).
• the choice of the modulator coefficient or coefficients on which the weighting law f (k) is applied may, for example, be made in such a way that all the samples composing the integrated output signal of the integration analog circuit 101 are on the same scale. to the law f (k).
• At least one input coefficient of an analog integrator Iaj_ is modulated by the law f, and that all the signals being summed or subtracted from the weighted signal, whether at the input of The integrator Iaj . or on the downstream path (after the output of the integrator Iaj), are preferably at the same scale with respect to the law f.
• a signal is considered on a scale vis-à-vis of the law f if it is located on the downstream path of an integrator having an upstream coefficient weighted by the law f, or if it is itself directly weighted by the law f.
• the choice of the modulator coefficient or coefficients on which the weighting law f (k) is applied is carried out so that all the samples composing the integrated output signal of the circuit 101 are multiplied (directly or indirectly). if the sample is an output sample of an integrator having a weighted upstream coefficient f) by the law f (k). This rule is particularly respected in the modulator of FIG.
• the coefficients of the modulator on which the law f (k) is applied can be the coefficients b] _, a] _ and bc ,, or in another variant the coefficients C] _, b5 and C7, or in another variant the coefficients C3, bc ,, C5, cg and C7.
• the weighting of the set of coefficients c4, c5, c6, c7 and c5 by the law f is less advantageous insofar as no upstream coefficient of an analog integrator n 'is modulated by the law f.
• the weighting law f (k) may be applied to a signal other than the input signal of the digital integrator of rank 3! 3 ⁇ 4. More generally and as in the modulator, the choice of the digital signals to which the law f (k) is applied is preferably carried out so that the weighting law f (k) is applied to the input of at least one digital integrator preferably the integrator of the same rank as the analog integrator Ia-j input of which is applied the law f (k) in the modulator. Moreover, as in the modulator, the choice of the digital signals to which the law f (k) is applied is preferably made so that the digital signals added or subtracted in the digital filter are on the same scale vis-à-vis vis-à-vis the law f (k).
• the digital filter comprises a number of cascaded digital integrators greater than or equal to (preferably equal to) the p-order of the sigma-delta modulator.
• the digital filter has a topology similar to that of the modulator, the law f (k) can be applied substantially at the same points in the modulator and in the digital filter.
• some intermediate signals may be multiplied by the law f (k), and others divided by law f (k).
• the coefficient C2 may be multiplied by the law f (k) and the coefficients C4 and C5 divided by the law f (k) so as to maintain the same scale at the summator, the other coefficients of the modulator remaining constant.
• the weighting by the law f (k) at the level of the digital filter may be identical to what has been described above (multiplication of the input signal of the integrator! 3 ⁇ 4 by the law f (k)).
• the inventors have found that, whatever the law f chosen, and provided that the law f exhibits at least one decay phase over the range of indices k ranging from 1 to OSR, the fact of applying a variable weighting coefficient to at least one internal analog signal of the sigma-delta modulator and advantageously at least one internal digital signal of the digital filter makes it possible to significantly improve the linearity of the sigma-delta converter (for a given OSR).
• the decay phase is a function of the rank k of the cycle.
• the decay phase generates a contribution to the analog filter of the internal analog signal at a given cycle (k) which is more weak than the contribution to the analog filter of the same analog signal internal to the previous cycle (k-1). At least one decreasing contribution between two successive rank cycles already brings an advantage.
• the law f can be a decreasing law over the entire range of indices k ranging from 1 to OSR, for example a decreasing exponential law.
• the law f can be a constant law, for example equal to 1, over the range of indices k ranging from 1 to t, with t being an integer between 1 and OSR, and decreasing (for example according to an exponential). on the range of indices k ranging from t + 1 to OSR.
• FIGS. 6, 7 and 8 are diagrams illustrating, for three distinct laws, the evolution of the linearity L and the noise B as a function of the OSR in a sigma-delta converter of the type described with reference to FIGS. 5A. and 5B.
• the curves 601, respectively 701, respectively 801 represent the evolution of the linearity L (in the ordinate on the left) as a function of the OSR (on the abscissa), and the curves 603, respectively 703 , respectively 803, represent the evolution of the noise B expressed in LSB (ordinate on the right) as a function of the OSR.
• L linearity
• LSB ordinate on the right
• the gain in linearity may differ depending on the location of the modulator where the law weighting f (k) is applied.
• the higher the weighting is applied upstream in the modulator the higher the gain in linearity, but the greater the increase in output noise will be significant if we consider a modulator whose each block is subjected to a temporal noise.
• the initial (unweighted) values of the modulator coefficients can be determined by usual methods of determining the coefficients of a sigma-delta modulator. Generally, to maximize the signal-to-noise ratio, the values of the coefficients are chosen so as to maximize the signals internal to the modulator, while being careful not to exceed the saturation threshold of the modulator. The use of a law f having weighting values f (k) greater than 1 then risks leading to the saturation of the modulator. In this case, preference will be given to a law f whose values are less than or equal to 1. If, on the other hand, the modulator coefficients are chosen so that the internal signals of the modulator are still far from the saturation threshold, the law f may have values greater than 1, which in particular makes it possible to increase the signal - to - noise ratio.
• the law f may have constant variation phases and / or increasing variation phases to satisfy the various constraints of the sigma-delta converter, in particular in terms of noise and / or continuity or periodicity (cyclic law). of the law f if the analog and digital integrators are not reinitialized between two successive phases of acquisition of a digital value of the signal (for example in the case of a sigma-delta converter used to digitize variable signals). To obtain the linearity gain sought, however, the law f has at least one decreasing phase of variation during a phase of acquisition of a digital value of the input signal.
• predetermined law is meant that the law is defined in the design of the modulator or during a configuration phase of the latter.
• the law can optionally be adjusted dynamically according to predefined rules, during a phase of acquisition of a digital value of the input signal, for example in order to adapt the law to the characteristics of the signal being converted.
• the coefficient C 1 can be multiplied by a first variable law f 1 (k), and the coefficient C 2 by a second variable law f 2 (k) distinct from the law f 1.
• the coefficient cg is multiplied by the law f2
• the coefficient ⁇ is multiplied by the law f1 and by the law f2
• the coefficient b5 is multiplied by the law f1 and by the law f2.
• the input signal of the digital integrator of rank 2! 3 ⁇ 4 can be multiplied by the law f1, and the input signal of the digital integrator of rank 3! 3 ⁇ 4 is multiplied by the law f2.
• the coefficient C2 may be multiplied by a first variable law f1 (k).
• the coefficients cg and C7 are multiplied by the law f1 (k).
• a second law f2 (k) is applied to the feedback coefficient al.
• the coefficient b5 is weighted by f1 (k) * f2 (k).
• a third law f3 (k) is applied to the coefficient b1 of the input signal Vin.
• the input signal of the digital integrator of rank 1! 3 ⁇ 4 can be multiplied by the law f2 (k + 1) of weighting of the feedback and the input signal of the integrator numerical of rank 3!
• 3 ⁇ 4 can be multiplied by the law f1 (k + 1).
• the scaling rules in this example are not applied at all points, especially between the coefficients bl and al, respectively modulated by two separate laws f2 and f3.
• the application of the law f3 is not here applied to the digital filter.
• the law of weighting of the input signal of the filter differs in this example from that of the modulator. Some weightings can therefore be applied only to one of the modulator coefficients, upstream of an integrator, without scaling downstream and without being applied to the filter.
• the law f3 can be different from zero on the fi rst cycles, then set to 0 from a cycle k (with 1 ⁇ j ⁇ k ⁇ OSR).
• the quantization process can continue with zero weighting of the input signal, without reducing the gain in linearity.
• the proposed weighting process makes it possible to continue the quantization of the residue of the conversion of the input signal Vin, after having weighted Vin non-zero way on the first cycles.
• Such combinations of laws may in particular make it possible to relax the implementation constraints that may result from the use of a single input weighting law of a single analog integrator of the modulator and a single digital integrator of the digital filter.
• FIGS. 5A, 5B, 6, 7 and 8 can be adapted to all known architectures of sigma-delta converters of order p greater than or equal to 1.
• Figure 9 illustrates an example of application to another type of sigma-delta converter architecture.
• FIG. 9 only the sigma-delta modulator of the converter has been shown.
• the digital filter of the converter is for example identical or similar to the digital filter of Figure 5B.
• the sigma-delta modulator of FIG. 9 includes elements common to the sigma-delta modulator of FIG. 5A. In the following, only the differences between these two modulators will be detailed.
• the modulator of FIG. 9 differs from the modulator of FIG. 5A, in particular in that, in the modulator of FIG. 9, the weighting coefficients b 2, a 2, 3, 33, b 4 and a 4 are not zero, and the coefficients C5, cg and C7 are zero.
• the weighting coefficients C2, 3, a ⁇ and b5 are multiplied by the same predetermined variable law f.
• Figure 10 illustrates, in block form, another example of an embodiment of a sigma-delta converter.
• the converter of FIG. 10 is an order 1 converter, comprising a sigma-delta modulator of order 1, and a digital filter of order 1.
• the sigma-delta modulator of FIG. 10 includes an input terminal A1 for receiving an analog input signal Vin to be digitized, and an output terminal A2 for providing a series of binary samples BS representative of the signal Vin.
• the modulator of FIG. 10 comprises an integration analog circuit 101 comprising a first input connected to the application terminal Al of the signal Vin, and a output A3 connected to the input of a 1-bit analog-to-digital conversion circuit 103, for example a 1-bit comparator.
• the output of the converter 103 is connected to the output A2 of the modulator, and is further connected by a feedback loop to a second input A4 of the integration circuit 101.
• the feedback loop comprises a digital converter.
• the integration circuit 101 takes an analog sample Vin (k) of the signal d input, and the modulator supplies, at the output of the 1-bit analog-to-digital converter 103, a binary sample BS (k) of the output signal.
• a binary sample BS (k) of the output signal In the example of FIG.
• the integration circuit 101 comprises a single analog integrator Ia_, for example a simple analog summation circuit comprising an input and an output, this circuit being adapted, at each cycle, to increment the value the output signal (or integrated signal) of the signal value applied to the input of the integrator.
• the integrator Ia receives on its input a signal equal to the difference between the input signal Vin (k) and the feedback signal applied to the terminal A4 (corresponding to the analog value signal BS (k-1)), weighted by a coefficient f (k-1) variable according to a predetermined law f.
• the difference operation is symbolized by a subtractor 108.
• the output of the integrator Ia is connected to the output terminal A3 of the circuit 101.
• the digital filter of the sigma-delta converter of FIG. 10 comprises a digital integrator (not shown), for example a counter, whose input is connected to the output A2 of the modulator via a digital application circuit. a weighting factor f (k) that varies according to the law f.
• the variable law f is applied at the level of the digital filter with a cycle of advance relative to the modulator.
• the input data of the filter is digital is the output binary data of the sigma-delta modulator, and the resolution of the internal data of the digital filter depends on 1 OSR and the resolution of the weighting law f.
• the resolution of the weighting law f in the digital filter is preferably greater than or equal to the resolution of the law f in the modulator.
• the output I (m) of the analog integrator can be written as follows:
• sequence U (m) representing the difference between the accumulated energy from the continuous input signal Vin and the accumulated energy from the feedback made by the sigma-delta modulator is defined as follows.
• This sequence U (m) represents the difference between the energy introduced by the signal and its estimate.
• FIG. 11 is a diagram illustrating the evolution, as a function of the OSR, of the actual number of theoretical bits ENOB defined by
• FIG. 12 is a circuit diagram of an exemplary embodiment of a circuit for dynamically varying a weighting coefficient of a sigma-delta modulator according to a variable law f.
• the capacitor C is, in this example, a digitally controllable capacitance capacitor made with a table. switched capabilities.
• the capacitor C is divided into n + 1 capacitances CP] _ to CP n + 1 .
• Capacities ⁇ to CP n are obtained by dichotomous division of the value of the capacity ⁇ 3 ⁇ 4 ase corresponding to the basic coefficient (unweighted).
• the capacitors CP 1, CP 2,... CP n have the values ⁇ 3 ⁇ 4 ase / 2, 3 ⁇ 4 ase / 4, ... ⁇ 3 ⁇ 4 ase / 2 n, respectively .
• the capacity CP n + i has the same value as the capacity CP n .
• the sum of the values of the capacitances CP_ to CP n + i is equal to ⁇ 3 ⁇ 4 ase .
• the capacitor with variable capacitance C of FIG. 12 comprises, between conduction terminals E1 and E2, n + 1 parallel branches each comprising one of the n + 1 capacitors CP a , with q integer ranging from 1 to n + 1, and two switches Sg controlled by the same control signal (or by very slightly shifted control signals, for example having a time shift of less than 0.1 TQSR), connecting the electrodes of the capacitance CPg respectively at the terminal El and at the terminal E2.
• a control circuit not shown can be provided for controlling the switches Sg so as to dynamically vary the capacitance of a capacitor C during an analog-to-digital conversion phase of the input signal of the sigma-delta converter.
• the switches s n + i are open, and the numerical value on n bits of the law f (k) is applied to the control signals switches S _ to s n , the strongest bit being applied to the switches S] _, and the least significant bit being applied to the switches s n .
• An advantage of the circuit of FIG. 12 is that the weighting law f (k) can easily be reconfigured, for example if the needs of the application change.
• the analog signal to be digitized is a voltage and is sampled on sigma-delta modulator capacitors (example of FIG. 2).
• the described embodiments are not limited to this particular case.
• the proposed solution can be adapted to analog current sigma-delta modulators.
• the weighting of the signals internal to the modulator by a variable law can for example be achieved by modulating the integration times of currents on capacitors. For modulators with continuous time, the law of weighting will not be more discrete (f (k)) but continuous (f (t)).
• the proposed solution can be adapted to MASH sigma-delta modulators (of the English "Multi Stage Noise Shaping"), that is to say that the proposed solution can be adapted to multi-stage noise shaping modulators.
• modulators of order p greater than 1 constituted by the serialization of several sigma-delta modulators of order less than p, each modulator of order less than p having, as in the modulators described above, an analog integration circuit, a 1-bit analog-to-digital converter, and a feedback loop which may include a digital-to-analog converter and a subtracter.
• the operating principle of sigma-delta modulators of the MASH type is for example described in the article "Sturdy MASH ⁇ - ⁇ modulator” by Maghari et al. (ELECTRONICS LETTERS 26th October 2006 Vol.42 No.22).
• the signals on which the weighting law f (k) is applied are chosen so that at least one weighting by the law f (k) is performed upstream of an integrator modulator and preferably so that the different signals added or subtracted in the modulator and / or in the digital filter of the converter are at the same scale.
• the analog input signal is inputted to the analog integration circuit 101 of the modulator, and the 1-bit analog-to-digital converter 103 of the modulator compares an output signal. circuit 101 to a constant reference signal.
• the input signal and the reference signal can be inverted.
• the inventors have found that if the modulator coefficients are fixed, the output noise of the sigma-delta converter is relatively high.
• the application of a variable weighting law to modulator coefficients makes it possible to significantly improve the accuracy of the converter.
• An advantage of this embodiment is that the reference input of the comparator 103 is a high impedance input.
• the application of the signal to be converted directly on the comparator makes it possible to avoid drawing power on the signal to be digitized.
• sigma-delta modulators comprising one or more cascaded analogue integrators.
• the described embodiments are not limited to this particular case. More generally, in the embodiments described, the analog integrators of the sigma-delta modulators can be replaced by other types of analog filters.
• Figure 13 illustrates, in block form, another example of an embodiment of a sigma-delta converter of order 1.
• the analog integration circuit 101 As is shown in FIG. 10, the analog integration circuit 101, the 1-bit analog-to-digital conversion circuit 103 and the 1-bit digital-to-analog converter 107 and the subtractor 108.
• the analog filter 106 of the circuit The integration analog 101 shown in FIG. 13 comprises an adder 109, a unity gain delay operator 111 denoted by Z 1 and a multiplier 113 making it possible to multiply the output signal of the operator 111 by a factor a.
• the adder 109 adds the received analog signal to the cycle k and an internal signal to the analog filter from the operator 111 multiplied by the coefficient a.
• the output of the summator 109 feeds the input of the operator 111 and forms the output A3 of the integration circuit 101.
• the signal internal to the analog filter from the operator 111 forms the output of the analog filter at the cycle k-1.
• a value of the coefficient a greater than strictly equal to 1 the contribution to the output value of the analog filter at the point A3 of the input analog signal of the summator 109 coming from the subtractor 108 to the cycle k is smaller than its contribution to the analog filter. in the previous cycle k-1. It is sufficient that during at least one cycle during the conversion phase, the coefficient a is strictly greater than 1 for the contribution condition to be satisfied. It is of course possible to provide a coefficient a strictly greater than 1 for several cycles see for all the cycles of a conversion phase.
• FIG. 13 The functional blocks shown in FIG. 13 can be realized in many ways, one of which is explained in FIG. 14. It is of course possible to make the summator 109, the operator 111 and the multiplier 113 in other forms depending existing components on the market and their ease of implementation.
• the summator, 109, the operator 111 and the multiplier 113 are made from an operational amplifier 115 receiving on its inverting input the internal signal from the subtractor 108 via a capacitance Cin.
• Switches ⁇ 1 and ⁇ 2 make it possible to connect the capacitor Cin either to the output of the adder 108, or to a reference voltage Vref or to the inverting input.
• the inverting input is connected to the output of the operational amplifier 115 via a capacitor Cfb which can be short-circuited by a switch ⁇ -r.
• the inverting input is also connected to the output of the operational amplifier 115 through a Cout capacitance which can be switched by switches also called ⁇ 1 and ⁇ 2.
• FIG. 14 A timing diagram is shown in Figure 14 to show the sequence by cycle of three switching phases switches ⁇ 1, ⁇ 2 and ⁇ . To simplify the understanding, the three phases ⁇ 1 ⁇ 2 and ⁇ are called by the name of the closed switches during each of the phases.
• phase ⁇ the integrator consisting of amplifier 115 with capacitance Cfb is reset by short-circuiting Cfb. Its charge Qcfb becomes null
• Vout (k) Wine (k) + a * Vout (k-1)
• the ratio between the values of the capacities Cout on the one hand and Cfb and Cin on the other hand amounts the value of the coefficient a.
• the weighting of the output of the digital filter can follow the law f (k) (or f (k + 1)) taking into account the theoretical application offset between the modulator and the digital filter. Another decreasing law can also be chosen for the digital filter.
• the variant embodiment described from FIGS. 13 and 14 has the advantage of not necessarily introducing a scale factor at the output of the integration circuit 101. Nevertheless, there is a risk of saturation of the integrator due to a gain greater than 1.
• An advantage of an exponential decay at the input of the integrator is related to consumption. Indeed, in a realization with switched capacities, the consumption related to the load of decreasing value capacities makes it possible to reduce the dynamic consumption. Nevertheless, this attenuation of the gain may cause an increase in the temporal noise. However, in certain imaging applications, for example, the linearity of the digital value produced at the output of the converter is greater than the temporal noise on this digital value.
• the eye will tend to smooth or average the temporal noise and will therefore be more sensitive to linearity errors (if we consider here a population of numerical values of output relative to several conversions of the same static input analog value, the noise is relative to the standard deviation of the population and the linearity error to the difference between the expected theoretical numerical value and the population mean).
• the proposed invention and in particular its variant explained from FIG. 10, nevertheless reduces the linearity error.
• FIG. 15a represents in the form of a chronogram whose time axis is expressed in number of cycles the evolution of the input weighting of the integrator according to the variant of FIG. 10.
• the total number of cycles OSR for producing a digital output value is 100 and the number N of cycles after which the input weight of the integrator is reset is 10.
• FIG. 15b represents in the form of a timing diagram with the same time axis, the weighting applied to the gain of the integrator according to the variant of FIG. 13. Every N cycles, in the example represented, the gain of 1 ' The integrator (initially equal to 1) is multiplied by (1 / q) N, i.e. (1/0, 8) 10 ⁇ 9.31, and is reset to its initial value at the next cycle. Thus, the property of a contribution of the input value of the integrator following the law f (k) is retained. In this combination, the risk of saturation is reduced and the robustness to noise is increased due to less attenuation of the input signal of the integrator.
• FIGS. 10 and 13 Another combination of the two variants of FIGS. 10 and 13 consists in simultaneously producing, at least for the same rank k, both an integrator input weighting and a gain in the integrator.
• variant FIG. 10 can be generalized to converters of order greater than 1 comprising several cascaded analog filters.
• the same is true for the variant presented with the aid of FIG. 13, which can be generalized to converters of order greater than 1.
• This generalization is presented in FIG. 16, where each integrator lal at Ia4 of FIG. replaced by an adder 109, an operator 111 and a multiplier 113. It is of course possible to replace only at least one of the integrators lal to Ia4 of FIG. 1a by an adder 109, an operator 111 and a multiplier 113.
• the factor a of each may be different in order to adjust the output variation ranges of the integrating analog filters.
• the digital filter is then advantageously adapted according to the different factors.
• the topology of the digital filter can be modified to approach that of the sigma-delta modulator.
• the digital filter in the case of a modulator with cascaded analog filters, it is advantageous to produce the digital filter by means of elementary filters of the same types and cascaded in the same way.
• filter of the same type we mean, for example, high pass, low pass, pass band, integrator filters which will be analog in the modulator and digital in the digital filter.
• different elementary filters can be implemented in an equivalent manner. It is for example possible to provide two variants of elementary filter. In the first variant, a unity gain integrator is preceded by a multiplier, in the image of the modulator of FIG. 10. In the second variant, the elementary filter comprises a non-unit gain integrator in the image of the modulator of FIG. 13. Integrator cascades according to the two variants are nevertheless completely equivalent and may both be implemented at the output of a modulator according to FIG. 10 or at the output of a modulator according to FIG. 13.
• the output value of the second integrator is equal to:
• the two ratios are identical, which shows the equivalence of the two variants of the digital filter. This equivalence has been shown for a cascade of two filters. It is understood that the equivalence between the two variants is obtained regardless of the number of cascaded elementary filters.

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