EP3014653B1 - Reduzierung von lötkontakttopologieunterschieden durch planarisierung - Google Patents

Reduzierung von lötkontakttopologieunterschieden durch planarisierung Download PDF

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Publication number
EP3014653B1
EP3014653B1 EP14733717.4A EP14733717A EP3014653B1 EP 3014653 B1 EP3014653 B1 EP 3014653B1 EP 14733717 A EP14733717 A EP 14733717A EP 3014653 B1 EP3014653 B1 EP 3014653B1
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EP
European Patent Office
Prior art keywords
solder
layer
solder pad
metal layer
metal
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EP14733717.4A
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English (en)
French (fr)
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EP3014653A2 (de
Inventor
Jipu Lei
Stefano Schiaffino
Alexander H. Nickel
Mooi Guan Ng
Salman Akram
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Lumileds Holding BV
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Lumileds Holding BV
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
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Definitions

  • This invention relates to solder-bonding a chip to a substrate and, in particular, to a technique for improving the reliability of solder connections between pads on the chip and pads on the substrate.
  • solder bumps on the pads.
  • the pads may have different heights due to a varying thickness of the chip or due to the pads having varying thicknesses.
  • the chip is then positioned over a larger substrate containing corresponding metal pads, and the solder bumps are reflowed to bond the opposing pads together to form electrical connections between the chip and the substrate.
  • Solder bumps may have heights between tens of micrometres (microns) to hundreds of micrometres (microns). These dimensions are typically many times greater than the differences in heights of the pads on the chip so, during reflow, there is a sufficient volume of solder on each pad to bridge across any gap to an opposing pad on the substrate. Additionally, the sizes of the solder bumps themselves vary somewhat, and the relatively large volume of solder is sufficient to bridge across any gap to an opposing pad on the substrate.
  • Figs. 1A-1C and Figs. 2A and 2B illustrate the problem with an insufficient size solder bump used with pads having differences in heights.
  • a chip 10 is shown that may be a semiconductor chip, a ceramic submount, or other chip that may benefit from small solder bumps.
  • the chip 10 has a small metal solder pad 12 and a small solder area 14 lower in height than the solder pad 12.
  • the chip 10 may have an array of such pads 12 or areas 14.
  • the area 14 represents any solder attachment area (which may also be another metal pad) that has a lower height than the pad 12.
  • Small solder bumps 16 and 18 are deposited over the pad 12 and area 14 and somewhat spread out over the surface. It is assumed the volumes of the solder bumps 16 and 18 are the same. If the pad 12 or area 14 were larger, the solder bumps 16 and 18 may resemble a sphere due to the surface tension of the solder.
  • solder bumps may be conventional such as tin, lead, silver, gold, nickel, other metals and alloys thereof.
  • the chip 10 is positioned over a substrate 20. Note how the solder bump 16 is pressed against the opposing metal pad 22 on the substrate 20, but the solder bump 18 is slightly separated from the opposing pad 24 on the substrate 20.
  • Fig. 1C the structure of Fig. 1B is heated to reflow the solder.
  • the solder bump 16 forms a good bond between the pads 16 and 22, but the solder bump 18 separates into two portions 18A and 18B and forms an unreliable connection between the pad 24 and the area 14. Therefore, more solder is needed and the solder pads/areas need to be larger or more separated.
  • the pad/area height difference limits the size and/or density of the solder pads/areas.
  • a chip 26 has a pad 28 and a lower height solder area 30, with a dielectric portion 32 between the pad 28 and area 30.
  • Recessed solder bumps 34 and 36, of the same volume solder, are formed on the pad 28 and area 30.
  • the chip 26 is positioned over the substrate 20. Note how the solder bump 34 is pressed against the opposing metal pad 22 on the substrate 20, but the solder bump 36 is slightly separated from the opposing pad 24 on the substrate 20.
  • solder bump 36 will not make a good connection to the opposing pad 24.
  • US 2002/052065 A1 discloses a method comprising: providing an electronic device with two pads at different distances above the surface of the electronic device; providing a dielectric layer between the pads; forming a patterned resist layer over portions of the dielectric layer; using the patterned resist layer, concurrently plating a first metal layer portion over the first pad and a second metal layer portion over the second pad; planarizing the first metal layer portion and the second metal layer portion, together with the patterned resist layer, resulting in the first metal layer portion and the second metal layer portion having surfaces in the same plane; and, after the planarizing of the first and second metal layer portions, depositing a first solder layer over the first metal layer portion and depositing a second solder layer over the second metal layer portion, such that a top surface of the first solder layer is in the same plane as a top surface of the second solder layer.
  • a chip is formed to have at least two pads having different heights.
  • a pad may include any area of the chip where a solder bump is to be deposited.
  • the pads will typically be a patterned metal layer.
  • a dielectric region is formed between the pads and has a height greater than the pads.
  • the pads are plated to form a relatively thick metal layer.
  • the metal layer portions over the pads are not planar due to the metal overlapping the dielectric region somewhat and due to non-uniformity in the plating process.
  • Other metal deposition techniques may also be used in examples not forming part of the claimed invention; however, plating may result in a finer resolution among other advantages.
  • CMP chemical-mechanical planarization
  • a uniform layer of solder is then formed over the planarized metal layer, such as by plating, screen printing, or other means.
  • the resulting solder layers over the metal layer portion are therefore in the same plane.
  • the plating was performed using a blanket seed layer and a patterned resist layer over the seed layer, the resist layer and seed layer below the resist layer are then etched away to electrically isolate the metal pads.
  • solder portions may then be bonded to corresponding pads of a substrate.
  • the connections with thus have a high reliability with only a very small amount of solder.
  • the pads may be made very small and/or very close together without the solder shorting the pads.
  • the present process greatly reduces the amount of solder required for reliable interconnections, saving considerable cost.
  • the process may be performed on individual chips after singulation or on a wafer scale before singulation.
  • Planarizing a semiconductor wafer surface for subsequent processing of the wafer is well known and described in US patent 6,746,317 .
  • the process of the present invention only planarizes the solder pads, which are at a height above the chip surface.
  • solder bumps themselves, such as described in US patents 5,901,437 and 6,660,944 .
  • planarization may dislodge the solder bumps. Further, such planarization may laterally spread the relatively soft solder bumps and create reliability problems.
  • the invention enables the use of less solder to ensure reliable connections are made between a chip and a substrate.
  • the invention is particularly useful where solder pads are desired to be small and/or closely spaced.
  • Fig. 3 illustrates a chip 40 that may be any electronic device, such as a flip chip light emitting diode (LED), an integrated circuit, a ceramic submount, an interposer, etc.
  • LED light emitting diode
  • a solder pad 42 is formed on the chip 40.
  • the pad 42 may be a metal layer contacting a semiconductor region or the pad 42 may itself be a semiconductor layer.
  • An area 44 is also shown, which may be another metal pad or semiconductor region where a metal connection is required.
  • Pad 42 and area 44 are an exemplary embodiment which includes two different starting heights of areas where a solder interconnection is to be made. Both the pad 42 and area 44 may be metal layers having different heights. The difference in heights may only be a few micrometres (microns).
  • the pads 42 and area 44 may be electrically connected to semiconductor regions or other circuitry in or on the chip 40.
  • Patterned dielectric layer 46 is formed between the pad 42 and area 44 as well as over other areas that are to be protected.
  • a metal seed layer 48 is deposited over the surface of the chip 40 such as by sputtering.
  • the seed layer 48 may be the same metal that will be plated over the seed layer, such as copper or other suitable material, or may be a different conductive material.
  • the seed layer 48 provides the conducting surface at the desired potential.
  • a patterned resist layer 50 is formed over the portions of the seed layer 48 that are not to be plated.
  • a potential is coupled to the seed layer 48, such as at an edge of the chip, and the chip is immersed in a plating solution.
  • a copper electrode (or other metal to be deposited) is also immersed in the plating solution and the copper atoms migrate to the seed layer 48 to form a relatively thick plating layer 52.
  • Layer 52 may be more than 10 micrometres (microns) thick. Electroless plating may also be used. The plating technique used may be conventional and need not be described in detail. A wide variety of metals may be deposited. The seed layer is no longer shown since it is assumed to be merged with the plating layer 52.
  • the plating layer 52 extends over the dielectric layer 46 somewhat since the seed layer 48 is exposed around the edges of the dielectric layer 46.
  • the plating layer 52 may be an irregular or a mushroom shape.
  • the plating layer 52 may have higher and lower points relative to the surface of chip 40. In the alternative, plating layer 52 may be relatively smooth, but will still have a lowest point relative to chip 40.
  • Fig. 6 illustrates a target planarization line 56 somewhat below the lowest point of the plating layer 52.
  • the planarization line 56 is above the dielectric layer 46. In an embodiment not forming part of the claimed invention, the planarization line 56 may be even with the dielectric layer 46.
  • a CMP process or other planarization process, is performed to planarize the plating layer 52 to the planarization line 56 ( Fig. 6 ). Note that the plating layer 52 still extends above the resist layer 50 so that the planarization only planarizes only one material. The top surfaces of all the plating layer portions are now in the same plane.
  • a relatively thin and uniform solder layer 58 is deposited over the planarized plating layer 52 so that the top surface of the solder layer 58 over each pad 12 and area 14 is substantially planar.
  • the solder layer 58 may be deposited by screen printing, plating, sputtering, or other suitable method.
  • the solder layer 58 may be any conventional metal or metal combination, such as gold, tin, silver, nickel, or other metals and alloys thereof.
  • the solder layer 58 may be made very thin due to the planar surface of the plating layer 52.
  • One or more interface layers may be deposited between the plating layer 52 and the solder layer 58 such as for improved wetting or bonding to the plating layer 52.
  • the resist layer 50 and exposed seed layer 48 are etched away to electrically isolate the solder layer 58 over each plating layer 52 portion.
  • the etch is a chemical etch.
  • Fig. 10 illustrates the resulting chip 40 positioned over a substrate 62, where the solder layer 58 either touches the corresponding metal pads 64 on the substrate 62 or is separated by an insubstantial distance so that the reflow process causes the solder layer 58 to form a reliable bond between the opposing pads.
  • the substrate 62 may be a printed circuit board, a submount, another chip, an interposer, or any other type of substrate.
  • the pressure of the bonding process pushes the solder layer 58 against the pads 64 while softening and fusing the solder layer 58 to the pads 64. Therefore, there will be a reliable connection between all the solder layer 58 portions and the pads 64.
  • Fig. 11 illustrates how the plated metal layer 65 may be formed, in an embodiment not forming part of the claimed invention, lower than the resist layer 66 on the chip 67, so both the metal layer 65 and the resist layer 66 are subsequently planarized during the same planarization process.
  • the target planarization line 68 is shown.
  • Fig. 12 is a flowchart identifying various steps that are used in one embodiment of the invention.
  • step 70 a chip is provided with solder pads that have different heights.
  • step 72 a relatively thick metal layer is deposited over the solder pads by plating.
  • step 74 the metal layer is planarized so that the top surface of the metal layer over each pad is in the same plane.
  • step 76 a substantially uniformly thin layer of solder is deposited over the planarized metal layer so the top surface of the solder over each pad is in the same plane.
  • step 78 the chip is positioned over a substrate having corresponding metal pads, and the solder is reflowed or ultrasonically bonded to the substrate pads.
  • the present invention may be performed on a wafer scale prior to the chips being singulated or performed after the chips are singulated.
  • the present invention is applicable to improving solder connections between any two opposing surfaces having solder pads and is not limited to chips.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Claims (10)

  1. Verfahren, Folgendes umfassend:
    Bereitstellen eines elektronischen Bauelements (40) mit einer ersten Oberfläche und einer zweiten Oberfläche gegenüber der ersten Oberfläche,
    Bereitstellen eines ersten Lötpads (42) in einem ersten Abstand oberhalb der ersten Oberfläche und eines zweiten Lötpads (44) in einem zweiten Abstand oberhalb der ersten Oberfläche, wobei sich der erste Abstand von dem zweiten Abstand unterscheidet,
    Bereitstellen einer dielektrischen Schicht (46) zwischen dem ersten Lötpad (42) und dem zweiten Lötpad (44),
    Deckschichtabscheiden einer Metallsaatschicht (48) über dem ersten Lötpad (42), dem zweiten Lötpad (44) und der dielektrischen Schicht (46),
    Bilden einer strukturierten Resistschicht (50) über Abschnitten der Saatschicht (48), die nicht plattiert werden sollen, so dass die Saatschicht über dem ersten Lötpad (42) und dem zweiten Lötpad (44) und um die Ränder der dielektrischen Schicht (46) herum freiliegt,
    Plattieren eines ersten Metallschichtabschnitts (52) über dem ersten Lötpad (42) oberhalb einer Höhe der dielektrischen Schicht (46) und der strukturierten Resistschicht (50) und
    Plattieren eines zweiten Metallschichtabschnitts (52) über dem zweiten Lötpad (44) oberhalb der Höhe der dielektrischen Schicht (46) und der strukturierten Resistschicht (50) gleichzeitig mit dem Plattieren des ersten Metallschichtabschnitts (52), so dass sich der erste Metallschichtabschnitt (52) über einen Abschnitt der dielektrischen Schicht (46) und einen Abschnitt der strukturierten Resistschicht (50) erstreckt und sich der zweite Metallschichtabschnitt (52) über einen Abschnitt der dielektrischen Schicht (46) und einen Abschnitt der strukturierten Resistschicht (50) erstreckt,
    Planarisieren des ersten Metallschichtabschnitts (52) und des zweiten Metallschichtabschnitts (52), so dass der Schritt des Planarisierens nur das Material planarisiert, das den ersten Metallschichtabschnitt (52) und den zweiten Metallschichtabschnitt (52) bildet, was dazu führt, dass der erste Metallschichtabschnitt (52) und der zweite Metallschichtabschnitt (52) eine dritte beziehungsweise vierte Oberfläche aufweisen, wobei die dritte Oberfläche und die vierte Oberfläche in der gleichen Ebene liegen und sich der planarisierte erste Metallschichtabschnitt (52) und der planarisierte zweite Metallschichtabschnitt (52) immer noch über Abschnitten der strukturierten Resistschicht (50) und der dielektrischen Schicht (46) erstrecken,
    Abscheiden einer ersten Lotschicht (58) über dem ersten Metallschichtabschnitt (52) und Abscheiden einer zweiten Lotschicht (58) über dem zweiten Metallschichtabschnitt (52) nach dem Planarisieren des ersten und des zweiten Metallschichtabschnitts (52), so dass eine obere Oberfläche der ersten Lotschicht (58) in der gleichen Ebene liegt wie eine obere Oberfläche der zweiten Lotschicht (58) und
    Wegätzen der strukturierten Resistschicht (50) und von Abschnitten der Metallsaatschicht (48), die nach dem Wegätzen der strukturierten Resistschicht (50) freiliegen, um die Lotschichten (58) über jedem plattierten Metallschichtabschnitt (52) elektrisch zu isolieren.
  2. Verfahren nach Anspruch 1, wobei der plattierte erste Metallschichtabschnitt (52) eine fünfte Oberfläche aufweist, die mit dem ersten Lötpad (42) verbunden ist, und eine sechste Oberfläche gegenüber der fünften Oberfläche,
    wobei der plattierte zweite Metallschichtabschnitt (52) eine siebente Oberfläche aufweist, die mit dem zweiten Lötpad (44) verbunden ist, und eine achte Oberfläche gegenüber der siebenten Oberfläche und
    wobei die dielektrische Schicht (46) näher bei der ersten Oberfläche liegt als ein beliebiger Punkt der sechsten und der achten Oberfläche.
  3. Verfahren nach Anspruch 1, ferner das Vereinzeln eines Wafers zu Chips umfassend, wobei das elektronische Bauelement ein Chip (40) nach der Vereinzelung aus dem Wafer ist.
  4. Verfahren nach Anspruch 3, ferner Folgendes umfassend:
    Positionieren des Chips (40) im Verhältnis zu einem Substrat (62), das ein drittes Lötpad (64) aufweist, das dem ersten Lötpad (44) entspricht und ein viertes Lötpad (64) aufweist, das dem zweiten Lötpad (42) entspricht,
    Bonden der ersten Lotschicht (58) an das dritte Lötpad (64) und
    Bonden der zweiten Lotschicht (58) an das vierte Lötpad (64).
  5. Verfahren nach Anspruch 4, wobei das Bonden der ersten Lotschicht (58) an das dritte Lötpad (64) und das Bonden der zweiten Lotschicht (58) an das vierte Lötpad (64) durch Lot-Reflow erfolgen.
  6. Verfahren nach Anspruch 4, wobei das Bonden der ersten Lotschicht (58) an das dritte Lötpad (64) und das Bonden der zweiten Lotschicht (58) an das vierte Lötpad (64) durch Ultraschallbonden erfolgen.
  7. Verfahren nach Anspruch 3, wobei der Chip (40) eine Flip-Chip-Leuchtdiode ist.
  8. Verfahren nach Anspruch 3, wobei der Chip (40) eine integrierte Schaltung ist.
  9. Verfahren nach Anspruch 1, wobei die Ebene parallel zur ersten Oberfläche liegt.
  10. Verfahren nach Anspruch 1, wobei die Ebene in einem Winkel relativ zur ersten Oberfläche liegt.
EP14733717.4A 2013-06-24 2014-06-05 Reduzierung von lötkontakttopologieunterschieden durch planarisierung Active EP3014653B1 (de)

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PCT/IB2014/061968 WO2014207590A2 (en) 2013-06-24 2014-06-05 Reducing solder pad topology differences by planarization

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JP2016529693A (ja) 2016-09-23
KR20160022917A (ko) 2016-03-02
KR102257933B1 (ko) 2021-05-31
TW201816905A (zh) 2018-05-01
CN105308732A (zh) 2016-02-03
WO2014207590A2 (en) 2014-12-31
US20160181216A1 (en) 2016-06-23
WO2014207590A3 (en) 2015-05-07
TWI622108B (zh) 2018-04-21
US9935069B2 (en) 2018-04-03
CN105308732B (zh) 2018-11-27
EP3014653A2 (de) 2016-05-04
TW201503271A (zh) 2015-01-16

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