EP2954543B1 - Substrate-less discrete coupled inductor structure - Google Patents

Substrate-less discrete coupled inductor structure Download PDF

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Publication number
EP2954543B1
EP2954543B1 EP14706170.9A EP14706170A EP2954543B1 EP 2954543 B1 EP2954543 B1 EP 2954543B1 EP 14706170 A EP14706170 A EP 14706170A EP 2954543 B1 EP2954543 B1 EP 2954543B1
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Prior art keywords
inductor
substrate
implementations
inductor winding
winding
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German (de)
English (en)
French (fr)
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EP2954543A1 (en
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James Thomas Doyle
Farsheed MAHMOUDI
Amirali Shayan ARANI
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Qualcomm Inc
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Qualcomm Inc
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Definitions

  • Various features relate to a substrate-less discrete coupled inductor structure.
  • a ladder coupled inductor structure 102 may comprise a core 104 with a plurality of inductor windings 106a-d.
  • a ladder structure 102 requires a custom core 104 and windings (e.g., coils). Relative to off-the-shelf inductors, the ladder structure 102 is relatively expensive. Additionally, when placing inductors within semiconductor devices, inductors taking up the smallest possible area are desired.
  • an inductor structure as set forth in claim 1 and a method for providing an inductor structure as set forth in claim 7.
  • Preferred embodiments are set forth in the dependent claims.
  • a substrate-less inductor structure that includes a first inductor winding, a second inductor winding and a filler.
  • the first inductor winding includes an electrically conductive material.
  • the second inductor winding includes an electrically conductive material.
  • the filler is laterally located between the first inductor winding and the second inductor winding.
  • the filler is configured to provide structural coupling of the first and second inductor windings.
  • the inductor structure is free of a substrate as a base portion for the inductor structure.
  • the first inductor winding is laterally co-planar to the second inductor winding.
  • the first inductor winding has a first spiral shape and the second inductor winding has a second spiral shape. In some implementations, the first inductor winding and the second inductor winding have an elongated circular shape. In some implementations, the filler is an epoxy.
  • FIGS. 2-3 illustrate an example of a coupled inductor structure.
  • the coupled inductor structure is designed / arranged in such a way as to occupy a small effective footprint / real estate with better and/or improved coupling than the ladder structure shown and described in FIG. 1 .
  • some implementations provide a coupled inductor structure that is designed / arranged to be thinner than the ladder structure shown in FIG. 1 .
  • such a coupled inductor structure is substrate-less discrete coupled inductor structure that is free of a substrate (e.g., substrate as a base portion has been removed) or, not in accordance with the claimed invention, has a very thin substrate.
  • FIG. 2 illustrates an angled view of a coupled inductor structure formed on a substrate (where the substrate is subsequently removed) and FIG. 3 illustrates top and side views of the coupled inductor structure on a substrate (where the substrate is subsequently removed).
  • removing the substrate provides a coupled inductor structure that is relatively thin compared to other coupled inductor structures.
  • the coupled inductor structure free of a substrate e.g., without a substrate as a base
  • the substrate-less coupled inductor structure has a thickness of 90 microns ( ⁇ m) or less.
  • FIG. 2 illustrates a coupled inductor structure 200 that includes a first inductor 204, a second inductor 206, and terminals 208-214.
  • the first inductor 204 e.g., first inductor winding
  • the second inductor 206 e.g., second inductor winding
  • the first inductor 204 and the second inductor 206 are coupled together through a filler (which is not visible) that provides structural coupling, stability, and/or rigidity for the coupled inductor structure 200.
  • the filler is an epoxy.
  • the filler is between the first inductor 204 and the second inductor 306 and holds the first and second inductors 204-206 together, allowing lateral energy coupling (e.g., energy transfer) between the two inductors 204-206.
  • FIG. 2 also illustrates that the coupled inductor structure is formed on a substrate 220.
  • the substrate 220 is shown as dotted lines to illustrate that the substrate 220 is removed after the inductors 204-206 are formed.
  • the substrate 220 is removed (e.g., etched, grinned) in order to provide a coupled inductor structure 200 that is as thin as possible.
  • FIG. 3 illustrates how a filler may provide structural coupling, stability and/or rigidity for the coupled inductor structure 200.
  • FIG. 3 illustrates top and side views of the coupled inductor structure on a substrate (which is subsequently removed or, not in accordance with the claimed invention, thinned).
  • the side view of the coupled inductor structure 200 is along the AA cross section of the top view of the coupled inductor structure 200.
  • the coupled inductor structure 200 includes a filler 202, a first inductor 204 and a second inductor 206.
  • the filler 202 provides structural coupling, stability and/or rigidity for the coupled inductor structure 200.
  • the filler 202 allows the first and second inductors 204-206 to be physically coupled together, allowing energy coupling between the first and second inductors 204-206. The energy coupling is further described below.
  • the coupled inductor structure 200 is formed on a substrate 220 (which is subsequently removed or, not in accordance with the claimed invention, thinned).
  • the substrate 220 may be a silicon substrate.
  • the first inductor 204 is defined by a first inductor winding (e.g., coils).
  • the second inductor 206 is defined by a second inductor winding (e.g., coils).
  • the first and second inductor windings may have electrically conductive material (e.g., metal, such as copper).
  • the first winding of the first inductor 204 has a shape of a first spiral.
  • the second winding of the second inductor 206 has a shape of a second spiral.
  • the inductor windings may have an elongated circular shape (e.g., race track shape).
  • the shape of the inductor windings may also be concentric, square, rectangular, oval, or other non-circular shapes.
  • the first spiral of the first inductor 204 and the second spiral of the second inductor 206 are positioned on the substrate 220 (the substrate 220 being subsequently removed) that there is lateral energy coupling between the first inductor 204 and the second inductor 206. That is, the first inductor 204 may be configured to induce a current in the second inductor 206.
  • lateral energy coupling refers to the transfer of energy between two inductors along the same plane (e.g., co-planar, along the same layer).
  • a lateral coupled inductor structure is an inductor structure where energy transfer between two inductors occurs mostly (e.g., majority), or substantially along the same plane.
  • a lateral coupled inductor structure may provide better coupling efficiency than other types of coupled inductor structures (e.g., vertical coupling inductor structure).
  • Some of the properties of an inductor and/or coupled inductor structure include effective inductance, Q factor and/or effectiveness of the coupling of the inductor structure.
  • the effectiveness of an inductor and/or inductor structure may be defined by its Q factor.
  • a Q factor is a quality factor/value that defines the efficiency of an inductor. The higher the Q factor, the closer the inductor approaches the behavior of an ideal inductor, which is a lossless inductor. Thus, generally speaking, a higher Q factor is more desirable than a lower Q factor.
  • the first inductor 204 is the primary inductor in the inductor structure and the second inductor 206 is the secondary inductor the inductor structure.
  • the first inductor 204 e.g., primary inductor
  • the second inductor 206 may induce a voltage / current in the second inductor 206 (e.g., secondary inductor).
  • the first inductor 204 may be the secondary inductor in the inductor structure and the second inductor 206 may be the primary inductor in the inductor structure.
  • the second inductor 206 may induce a voltage / current in the first inductor 204.
  • Each inductor 204-206 also includes a set of pins / terminals (e.g. an input terminal and an output terminal).
  • the first inductor 204 includes a first input terminal 208 (e.g., Vx1 ) and a first output terminal 2010 (e.g., Vout1 )
  • the second inductor 206 includes a second input terminal 214 (e.g., Vx2 ) and a second output terminal 212 (e.g., Vout2 ).
  • the terminal 208 may be an output terminal and the terminal 210 may be an input terminal.
  • the coupled inductor structure 200 may also include one or more ferromagnetic layers (not shown).
  • a first ferromagnetic layer may be located on top of the substrate 202 and a second ferromagnetic layer may be located on a bottom of the substrate 202.
  • the first and second ferromagnetic layers may be positioned above / below the filler between the inductors 204-206.
  • the first and second ferromagnetic layers may not be electrically coupled to the inductors 204-206.
  • the first and second ferromagnetic layers may be configured to reduce losses due to metal proximity (Faraday Cage).
  • the first and second ferromagnetic layers may also provide shielding of the first and second inductors 204-206, which helps increase the effective inductance, the Q factor and/or effectiveness of the coupling of the coupled inductor structure 200 in some implementations.
  • the effectiveness of an inductor may be defined by its Q factor.
  • a Q factor is a quality factor/value that defines the efficiency of an inductor. The higher the Q factor, the closer the inductor approaches the behavior of an ideal inductor, which is a lossless inductor. Thus, generally speaking, a higher Q factor is more desirable than a lower Q factor.
  • the use of the first and second ferromagnetic layers help increase the Q factor (e.g., increase effective inductance) of the coupled inductor structure 200 and provide magnetic shielding.
  • the magnetic shielding keeps (e.g., concentrates) the magnetic field generated by one or more of the inductors 204-206 within the coupled inductor structure, which increases the effective impedance (e.g., increase Q factor) of the inductor structure.
  • the first and second ferromagnetic layers may have high permeability ( ⁇ ) and/or high B saturation.
  • the permeability of a material refers to the degree of magnetization that the material obtains in response to an applied magnetic field.
  • the B saturation of a material refers to the state that the material reaches when an increase in magnetic field no longer increases the magnetization of the material.
  • An example of a ferromagnetic material could be silicon steel, Manganese-zinc ferrite (MnZn), and/or permalloy.
  • the first and second ferromagnetic layers are magnetic foils.
  • FIGS. 4A-4C illustrates a sequence for providing / manufacturing a substrate-less coupled inductor structure.
  • the sequence of FIGS. 4A-4C may be used to manufacture the coupled inductor structure 200 of FIGS. 2-3 .
  • the sequence of FIGS. 4A-4C may be applicable to other coupled inductor structures.
  • the sequence starts at stage 1 of FIG. 4A with a substrate 402.
  • the substrate 402 may be a silicon substrate in some implementations. Different implementations may use different substrates. In some implementations, the substrate 402 may be thinned.
  • a sacrificial layer 404 is provided (e.g., deposited) above the substrate 402.
  • the sacrificial layer 404 may be a photoresist layer in some implementations. Different implementations may use different materials for the photoresist layer.
  • patterns 405 are formed in the sacrificial layer 404.
  • the patterns 405 may be cavities and/or trenches in the sacrificial layer 404.
  • Different implementations may use different methods for creating / forming the patterns 405.
  • the patterns are etched / drilled in the sacrificial layer 404.
  • a laser may be used to etch and/or drill in the sacrificial layer 404.
  • lithography is used to etch the patterns 405 in the sacrificial layer 404. The etching may also be performed by a chemical process in some implementations.
  • a metal layer 406 is deposited above the substrate 402.
  • the metal layer 406 may fill some or all of the patterns 405 created in the sacrificial layer 404.
  • the metal layer 406 may also be deposited above the sacrificial layer 404.
  • Different implementations may use different materials for the metal layer 406.
  • the metal layer 406 may be copper in some implementations.
  • the sacrificial layer 404 and the metal layer 406 above the sacrificial layer 404 is removed, leaving only the remaining metal 408.
  • Different implementations may use different methods for removing (e.g., etching) the sacrificial layer 404 and the metal layer 406.
  • a chemical process may be used to "wash out” the remaining the sacrificial layer 404.
  • the metal layer above the sacrificial layer 404 is also removed in some implementations.
  • the remaining metal layer now becomes the components 408 of the inductor structure.
  • the components 408 may be windings of the first inductor and/or the second inductor.
  • the components 408 may also be the terminals of the first inductor and/or the second inductor in some implementations.
  • a filler 410 is provided between the components 408 (e.g., between the windings of the first and second inductors).
  • the filler 410 may be an epoxy in some implementations.
  • the filler 410 may be configured to provide structural coupling, stability, and/or rigidity for the coupled inductor structure in some implementations. That is in some implementations, the filler 410 may be configured to allow the coupled inductor structure to have structural integrity in the absence of a substrate as a base portion. For example, the filler 410 may allow a first inductor to be physically coupled to the second inductor.
  • the substrate 402 is removed (e.g., etched) from the coupled inductor structure.
  • the removal of the substrate 402 is represented by the dotted lines defining where the substrate 402 was previously located.
  • Different implementations may use different methods for removing the substrate.
  • a laser may be used to etch away the substrate 402.
  • only a portion of the substrate is removed.
  • the substrate is thinned, instead of being completely removed.
  • portions of the filler 410 is removed.
  • the removal of portions of the filler 410 is represented by the dotted lines defining where the portions was previously located.
  • Different implementations may use different methods for removing portions of the filler 410. For example, a laser may be used to remove portions of the filler 410. Portions of the filler 410 may be removed to further decrease the size and/or area of the coupled inductor structure.
  • Stage 9 illustrates an exemplary coupled inductor structure 400 after the substrate has been removed.
  • the substrate-less coupled inductor structure includes components 408 (which may include windings for first and second inductors) and a filler 410 that physically couples the components 408 together (e.g., physically couples windings of the first inductor to windings of the second inductor).
  • one or more ferromagnetic layers may be provided (e.g., deposited) on the coupled inductor structure 400.
  • the ferromagnetic layers may be provided above and/or below the coupled inductor structure 400.
  • Different implementations that are not in accordance with the claimed invention may provide the ferromagnetic layers during different stages of the manufacturing of the coupled inductor structure.
  • one or more ferromagnetic layers may be provided on a filler (e.g., after stage 6 of FIG. 4B ).
  • one or more ferromagnetic layers may be provided after the substrate is removed and/or thinned (e.g., after stage 7 of FIG. 4C ).
  • FIG. 5 illustrates a flow diagram of a method for providing / manufacturing a substrate-less coupled inductor structure.
  • the method of FIG. 5 is used to manufacture / provide the substrate-less coupled inductor structure 200 of FIGS. 2-3 and the substrate-less coupled inductor structure 400 of FIGS. 4A-4C .
  • the method provides (at 505) a substrate (e.g., substrate 402).
  • the substrate may be a silicon substrate in some implementations. Different implementations may use different substrates. In some implementations, the substrate may be thinned.
  • the method further provides (at 510) a sacrificial layer (e.g., sacrificial layer 404) above the substrate.
  • a sacrificial layer e.g., sacrificial layer 404
  • providing the sacrificial layer includes depositing the sacrificial layer on the substrate.
  • the sacrificial layer may be a photoresist layer in some implementations. Different implementations may use different materials for the photoresist layer.
  • the method selectively removes (at 515) portions of the sacrificial layer.
  • selectively removing portions of the sacrificial includes creating / forming patterns (e.g., patterns 405) in the sacrificial layer.
  • the patterns may be cavities and/or trenches in the sacrificial layer. Different implementations may use different methods for selectively removing portions of the sacrificial layer, creating / forming the patterns.
  • the patterns are etched / drilled in the sacrificial layer. For example, a laser may be used to etch and/or drill in the sacrificial layer.
  • lithography is used to etch the patterns in the sacrificial layer. The etching may also be performed by a chemical process in some implementations.
  • the method provides (at 520) a metal layer (e.g., metal layer 406) above the substrate.
  • providing the metal layer includes depositing a metal layer above the substrate.
  • the metal layer may fill some or all of the patterns created in the sacrificial layer when selected portions of the sacrificial layer were removed (at 515).
  • the metal layer may also be deposited above the sacrificial layer. Different implementations may use different materials for the metal layer.
  • the metal layer may be copper in some implementations.
  • the method removes (at 525) the sacrificial layer and the metal layer above the sacrificial layer.
  • Different implementations may use different methods for removing (e.g., etching) the sacrificial layer and the metal layer.
  • a chemical process may be used to "wash out” the remaining the sacrificial layer.
  • the metal layer above the sacrificial layer is also removed in some implementations.
  • the remaining metal layer now becomes the components (e.g., components 408) of the inductor structure.
  • the components e.g., components 408) may be windings of the first inductor and/or the second inductor.
  • the components may also be the terminals of the first inductor and/or the second inductor in some implementations.
  • the method provides (at 530) a filler (e.g., filler 410) between the metal layer that define the components of the coupled inductor structure (e.g., between the windings of the first and second inductors).
  • a filler e.g., filler 410 between the metal layer that define the components of the coupled inductor structure (e.g., between the windings of the first and second inductors).
  • providing the filler includes depositing a filler in between the metal layer that defines the components of the coupled inductor structure.
  • the filler may be an epoxy in some implementations.
  • the filler may be configured to provide structural coupling, stability, and/or rigidity for the coupled inductor structure in some implementations. That is, in some implementations, the filler may be configured to allow the coupled inductor structure to have structural integrity in the absence of a substrate as a base portion.
  • the filler may allow a first inductor (e.g., first inductor winding) to be physically coupled
  • the method removes (at 535) the substrate from the coupled inductor structure.
  • Different implementations may use different methods for removing the substrate.
  • a laser may be used to etch away the substrate.
  • some implementations may also remove portions of the filler. Portions of the filler may be removed to further decrease the size and/or area of the coupled inductor structure.
  • FIG. 6 illustrates a flow diagram of a method for providing / manufacturing a substrate-less coupled inductor structure.
  • the method of FIG. 6 is used to manufacture / provide the substrate-less coupled inductor structure 200 of FIGS. 2-3 and the substrate-less coupled inductor structure 400 of FIGS. 4A-4C .
  • the method provides (at 605) a substrate (e.g., substrate 402).
  • the substrate may be a silicon substrate in some implementations. Different implementations may use different substrates. In some implementations, the substrate may be thinned.
  • the method further provides (at 610) a first inductor winding and a second inductor winding on the substrate.
  • a first inductor winding and a second inductor winding may provide the first inductor winding and the second inductor winding on the substrate differently.
  • providing the first and second inductor windings includes providing (e.g., depositing) a sacrificial layer above the substrate.
  • the sacrificial layer may be a photoresist layer in some implementations. Different implementations may use different materials for the photoresist layer.
  • providing the first and second inductor windings also includes providing selectively removing portions of the sacrificial layer.
  • selectively removing portions of the sacrificial includes creating / forming patterns (e.g., patterns 405) in the sacrificial layer.
  • the patterns may be cavities and/or trenches in the sacrificial layer. Different implementations may use different methods for selectively removing portions of the sacrificial layer, creating / forming the patterns.
  • the patterns are etched / drilled in the sacrificial layer. For example, a laser may be used to etch and/or drill in the sacrificial layer.
  • lithography is used to etch the patterns in the sacrificial layer. The etching may also be performed by a chemical process in some implementations.
  • providing the first and second inductor windings includes providing a metal layer (e.g., metal layer 406) above the substrate.
  • providing the metal layer includes depositing a metal layer above the substrate. The metal layer may fill some or all of the patterns created in the sacrificial layer when selected portions of the sacrificial layer were removed. In some implementations, the metal layer may also be deposited above the sacrificial layer. Different implementations may use different materials for the metal layer. For example, the metal layer may be copper in some implementations.
  • providing the first and second inductor windings further includes providing removing the sacrificial layer and the metal layer above the sacrificial layer.
  • Different implementations may use different methods for removing (e.g., etching) the sacrificial layer and the metal layer. For example, a chemical process may be used to "wash out" the remaining the sacrificial layer. During the process of "washing out” the sacrificial layer, the metal layer above the sacrificial layer is also removed in some implementations. After the sacrificial layer is removed, the remaining metal layer now becomes the components (e.g., components 408) of the inductor structure.
  • the components may be windings of the first inductor and/or the second inductor.
  • the components may also be the terminals of the first inductor and/or the second inductor in some implementations.
  • the method provides (at 615) a filler between the first inductor winding and the second inductor winding.
  • providing (at 615) the filler includes depositing a filler (e.g., filler 410) between the metal layer that defines the components of the coupled inductor structure.
  • the filler may be an epoxy in some implementations.
  • the filler may be configured to provide structural coupling, stability, and/or rigidity for the coupled inductor structure in some implementations. That is, in some implementations, the filler may be configured to allow the coupled inductor structure to have structural integrity in the absence of a substrate as a base portion.
  • the filler may allow a first inductor (e.g., first inductor winding) to be physically coupled to the second inductor (e.g., second inductor winding).
  • the method removes (at 620) the substrate from the coupled inductor structure.
  • Different implementations may use different methods for removing the substrate.
  • a laser may be used to etch away the substrate.
  • some implementations may also remove portions of the filler. Portions of the filler may be removed to further decrease the size and/or area of the coupled inductor structure.
  • removing the substrate includes remove a portion of the substrate (e.g., thinning the substrate).
  • one or more of the coupled inductor structures may be coupled on a substrate within a package-on-package (PoP) structure.
  • FIG. 7 illustrates a side view of a package-on-package (PoP) structure 700 that includes coupled inductor structures.
  • the PoP structure includes a first package substrate 702, a first set of solder balls 704, a first die 706, a second package substrate 708, a second set of solder balls 710, a second set of dice 712, a first inductor structure 714, and a second inductor structure 716.
  • the first and second inductor structures 714-716 may be the inductor structure 200 and/or 400 of FIGS. 2-3 and FIGS. 4A-C .
  • the first die 706 may be a logic die.
  • the second set of dice 716 may be stacked memory dice in some implementations.
  • the first package of the PoP structure 700 may include the first package substrate 702, the first set of solder balls 704 and the first die 706.
  • the first package of the PoP structure 700 may also include the first and second inductor structures 714-716.
  • the first die 706 may be an Application Specific Integrated Circuit (ASIC) die in some implementations.
  • the first inductor structure 714 may be integrated on the top surface of the first package substrate 702. As shown in FIG. 7 , one or more solder balls may be removed to place the first inductor structure 714 on the top surface of the first package substrate 702.
  • An inductor structure may also be located on the bottom surface of a package substrate. As further shown in FIG. 7 , the second inductor structure 716 is located on the bottom surface of the first package substrate 702. One or more of the first set of solder balls 710 may be removed to allow the second inductor structure 716 to be placed on the bottom of the first package substrate 702.
  • FIG. 8 illustrates a side view and a bottom view of another package-on-package (PoP) structure 800 that includes coupled inductor structures.
  • the PoP structure includes a first package substrate 802, a first set of solder balls 804, a first die 806, a second package substrate 808, a second set of solder balls 810, a second set of dice 812, and an inductor structure 814.
  • the first inductor structures 814 may be the inductor structure 200 and/or 400 of FIGS. 2-3 and FIG. 4A-C .
  • the first die 706 may be a logic die.
  • the second set of dice 716 may be stacked memory dice in some implementations.
  • the inductor structure 814 is located on a bottom portion / surface of the first package substrate 802.
  • the inductor structure 814 is surrounded by the first set of solder balls 804.
  • FIG. 8 also illustrates that some of the solder balls from the first set of solder balls 804 have been removed in order to make room for the inductor structure 814.
  • the inductor structure 814 of FIG. 8 may conceptually represent one inductor structure or several inductor structures.
  • one or more of the coupled inductor structures may be coupled on a substrate within a semiconductor package.
  • a die/chip 900 may be mounted on a package substrate 902.
  • FIG. 9 also illustrates two coupled inductor structures on the surface of the package substrate 902.
  • FIG. 9 illustrates a first structure 904 and a second structure 906 on the package substrate 902.
  • the first and second structures 904-906 are coupled to the die 900 through a set of wiring (e.g., traces).
  • the first and second structures 904-906 may each be the inductor structure (e.g., inductor structure 200, 400) shown and described in FIGS. 2-3 and/or FIGS. 4A-4C .
  • one or more of the inductors from the inductor structure 904-906 may operate on different voltages.
  • one or more electrical voltage regulators (EVRs) 908-910 may be used to regulate the voltage / current that is provided (e.g., supplied) to one or more of the inductors in the inductor structures 904-906.
  • EVRs electrical voltage regulators
  • a first EVR 908 may be used to regulate and/or provide a voltage /current to the first structure 904.
  • the first EVR 908 may also regulate the phase of the voltage / current that is provided to one or more inductors of the first structure 904.
  • a second EVR 910 may be used to regulate and/or a voltage to the second structure 906.
  • the second EVR 910 may also regulate the phase of the voltage / current that is provided to one or more inductors of the first structure 906.
  • the first and second EVRs 908-910 are located on the die 900.
  • the EVRs 908-910 may be coupled to the die 900 but physically separate from the die 900.
  • the combined dimensions of the first and second EVRs 908-910 may be 2 mm x 2 mm or less.
  • different implementations may have EVRs 908-910 with different dimensions.
  • the spacing between the die 900 and one or both of the structures 904-906 is 2 mm or less.
  • the spacing may be defined as the edge to edge distance between two components (e.g., distance between the edge of a die and the edge of structure).
  • the spacing between the die 900 and the outer edge of the structure e.g., structure 904 is greater than 8 mm and lesser than 5 mm.
  • different implementations may have different spacing between the die 900 and one or more of the structure 904-906.
  • the substrate 902 may be part of an encapsulated package substrate (EPS) (which is further described below with reference to FIGS. 10-11 ). Consequently, the thickness of the inductor structures 902-904 is kept to less than or equal to the thickness of die/chip 900 (e.g., 0.2 mm or less) in some implementations.
  • EPS encapsulated package substrate
  • one or more of the coupled inductor structures may be coupled inside a substrate (e.g., package substrate) within a semiconductor package.
  • FIGS. 10-11 illustrate examples of a coupled inductors structure in a substrate in some implementations.
  • FIG. 10 illustrates a cross-sectional, schematic view of an IC package 1000 according to one aspect of the disclosure.
  • the IC package 1000 includes an IC die 1002 (e.g., memory circuit, processing circuit, applications processor, etc.) for an electronic device, such as, but not limited to, a mobile phone, laptop computer, tablet computer, personal computer, etc.
  • IC die 1002 e.g., memory circuit, processing circuit, applications processor, etc.
  • the IC package 1000 and in particular, the IC die 1002 may be supplied power (e.g., provided nominal supply voltages and currents) from a power management integrated circuit (PMIC) (not shown) through a power delivery network (PDN) (portions of the PDN external to the IC package 1000 are not shown) associated with the electronic device.
  • PMIC power management integrated circuit
  • PDN power delivery network
  • the IC die 1002 is electrically coupled to a multi-layer package substrate 1004 below it in a flip-chip style.
  • one or more soldering balls 1006 may electrically couple the die 1002 to metal traces located within a first metal layer 1022 of the package substrate 1004.
  • the IC die 1002 may be wire bonded to the package substrate 1004.
  • the package substrate 1004 may be, for example, a four metal layer laminate substrate.
  • the package substrate 1004 may have three or more metal layers, including five, six, seven, eight, nine, or ten metal layers.
  • the four layer package substrate 1004 shown includes the first metal layer 1022 (e.g., first outer metal layer), a second metal layer 1024 (e.g., first inner metal layer), a third metal layer 1026 (e.g., second inner metal layer), and a fourth metal layer 1028 (e.g., second outer metal layer.
  • Each of the metal layers 1022, 1024, 1026, 1028 are generally separated from one another by a plurality of insulating layers 1032, 1034, 1036 that may be composed of one or more dielectric materials, such as, but not limited to, epoxy and/or resin.
  • the first insulating layer 1034 in the middle of the package substrate 1004 may be thicker than the other layers and also provides structural rigidity to the package substrate 1004.
  • a plurality of metal vertical interconnect accesses (vias) 1008 electrically couple traces of the plurality of metal layers 1022, 1024, 1026, 1028 of the package substrate 1004 to each other where desired.
  • the package substrate 1004 includes a cavity 1035 (indicated by the dashed line box) that houses an embedded passive substrate (EPS) discrete circuit component (DCC) 1010, such as a capacitor, resistor, or inductor.
  • EPS embedded passive substrate
  • the EPS discrete circuit component is the coupled inductor structure described herein (e.g., coupled inductor structure of FIGS. 2-3 ).
  • the DCC 1010 is a conceptual representation of a DCC and does not necessarily represent exactly how the DCC (e.g., coupled inductor structure) is formed and coupled in the substrate. Rather, the DCC 1010 in FIGS. 10 and 11 is merely intended to show a possible location of a DCC in a substrate.
  • a first electrode (which is coupled to a first conductive layer) for the DCC may be coupled to the top left vias while a second electrode (which is coupled to a second conductive layer) for the DCC may be coupled to the top right vias in some implementations.
  • the cavity 1035 may occupy or be located within a portion of the first insulator layer 1034, and also one or more of the inner metal layers 1024, 1026.
  • the DCC 1010 may be, for example, a discrete capacitor (e.g., "decoupling capacitor").
  • the discrete capacitor 1010 helps reduce the impedance at a range of frequencies of the PDN by balancing inductive components of the impedance due to the IC package 1000 (e.g., inductance caused by traces, vias, metal lines, etc. associated with the package substrate 1004).
  • the package substrate 1004 may have a plurality of cavities each housing a separate EPS discrete circuit component.
  • the package substrate 1004 may comprise one or more via coupling components (e.g., via coupling component 1040) that are electrically coupled to electrodes of the DCC 1010.
  • the via coupling components serve as a means for increasing the available surface area to which a plurality of vias may couple to (e.g., a first end of each via may couple to the via coupling components).
  • the via coupling components are composed of a conductive material, such as a metal or metal alloy (e.g., copper, aluminum, and/or titanium nitride, etc.).
  • the via coupling components are made of one or more of the same metals that comprise the inner metal layers 1024, 1026.
  • a first via coupling component is electrically coupled to both a first electrode of the DCC 1010 and a first metal trace within the first inner metal layer 1024; a second via coupling component is electrically coupled to both the first electrode and a second metal trace within the second inner metal layer 1026; a third via coupling component is electrically coupled to both a second electrode of the DCC 1010 and a third metal trace within the first inner metal layer 1024; a fourth via coupling component is electrically coupled to both the second electrode and a fourth metal trace within the second inner metal layer 1026.
  • Each of the aforementioned metal traces may be electrically coupled to a power or ground plane associated with the package substrate 1004.
  • the first metal trace may be electrically coupled to the second metal trace by means of a via
  • the third metal trace may be electrically coupled to the fourth metal trace by means of another via.
  • the via coupling components may be electrically coupled to power or ground planes within the first and second inner metal layers 1024, 1026, wherein the first and second inner metal layers are closer to the first insulator layer 1034 than the outer metal layers 1022, 1028.
  • a first portion of the first via coupling component extends beyond a first edge of the first electrode of the DCC 1010.
  • a second portion of the first via coupling component is positioned within the first inner metal layer 1024.
  • a first portion of the second via coupling component may extend beyond a second edge of the first electrode, and a second portion of the second via coupling component may be positioned within the second inner metal layer 1026.
  • a first portion of the third via coupling component extends beyond a first edge of the second electrode of the DCC 1010.
  • a second portion of the third via coupling component is positioned within the first inner metal layer 1024.
  • a first portion of the fourth via coupling component may extend beyond a second edge of the second electrode, and a second portion of the fourth via coupling component may be positioned within the second inner metal layer 1026.
  • FIG. 11 illustrates a capacitor structure in another substrate in some implementations.
  • FIG. 11 is similar to FIG. 10 .
  • the substrate 1004 does not include one or more via coupling components (e.g., via coupling component 1040 of FIG. 10 ).
  • FIG. 12 illustrates various electronic devices that may be integrated with any of the aforementioned integrated circuit, die or package.
  • a mobile telephone 1202, a laptop computer 1204, and a fixed location terminal 1206 may include an integrated circuit (IC) 1200 as described herein.
  • the IC 1200 may be, for example, any of the integrated circuits, dice or packages described herein.
  • the devices 1202, 1204, 1206 illustrated in FIG. 12 are merely exemplary.
  • IC 1200 may also feature the IC 1200 including, but not limited to, mobile devices, hand-held personal communication systems (PCS) units, portable data units such as personal digital assistants, GPS enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers or any other device that stores or retrieves data or computer instructions, or any combination thereof.
  • PCS personal communication systems
  • FIGS. 2 , 3 , 4A-4C , 5 , 6 , 7 , 8 , 9 , 10 , 11 and/or 12 may be rearranged and/or combined into a single component, step, feature or function or embodied in several components, steps, or functions. Additional elements, components, steps, and/or functions may also be added without departing from the invention.
  • FIGs One or more of the components, steps, features and/or functions illustrated in the FIGs may be rearranged and/or combined into a single component, step, feature or function or embodied in several components, steps, or functions. Additional elements, components, steps, and/or functions may also be added without departing from novel features disclosed herein.
  • the apparatus, devices, and/or components illustrated in the FIGs may be configured to perform one or more of the methods, features, or steps described in the FIGs.
  • the novel algorithms described herein may also be efficiently implemented in software and/or embedded in hardware.
  • the word "exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term “aspects” does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation.
  • the term “coupled” is used herein to refer to the direct or indirect coupling between two objects. For example, if object A physically touches object B, and object B touches object C, then objects A and C may still be considered coupled to one another-even if they do not directly physically touch each other.
  • die package is used to refer to an integrated circuit wafer that has been encapsulated or packaged or encapsulated.
  • the embodiments may be described as a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged.
  • a process is terminated when its operations are completed.
  • a process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.
  • a process corresponds to a function
  • its termination corresponds to a return of the function to the calling function or the main function.

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CN104969312B (zh) 2018-05-15
KR20150115867A (ko) 2015-10-14
TW201443940A (zh) 2014-11-16
TW201640535A (zh) 2016-11-16
CN104969312A (zh) 2015-10-07
JP2016513364A (ja) 2016-05-12
EP2954543A1 (en) 2015-12-16
WO2014123790A1 (en) 2014-08-14
US10115661B2 (en) 2018-10-30
TWI600037B (zh) 2017-09-21
US20140225700A1 (en) 2014-08-14
TWI611437B (zh) 2018-01-11

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