EP2940520B1 - Dispositif d'affichage d'inversion z et son procédé de fabrication - Google Patents

Dispositif d'affichage d'inversion z et son procédé de fabrication Download PDF

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Publication number
EP2940520B1
EP2940520B1 EP15165848.1A EP15165848A EP2940520B1 EP 2940520 B1 EP2940520 B1 EP 2940520B1 EP 15165848 A EP15165848 A EP 15165848A EP 2940520 B1 EP2940520 B1 EP 2940520B1
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Prior art keywords
drain electrode
electrode
display device
gate line
inversion type
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German (de)
English (en)
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EP2940520A1 (fr
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Donggeun Lim
KiTaeg Shin
ChelHee Jo
Jiwon Kang
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LG Display Co Ltd
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LG Display Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present invention is a technology related to a display device and a method of manufacturing the display device.
  • the present invention is a technology related to a display device in which pixels are formed in a Z-inversion type, and a method of manufacturing the dispay device.
  • LCD Liquid Crystal Display
  • PDP Plasma Display Panel
  • OLED Organic Light Emitting Diode Display Device
  • a Liquid Crystal Display (LCD) device includes a display panel and a driving unit.
  • the display panel includes an array substrate including a thin film transistor, which is a switching device for controlling on/off of each pixel area, an upper substrate including color filters and/or black matrixes, and a liquid crystal layer formed between the array substrate and the upper substrate.
  • the driving unit controls the thin film transistor.
  • alignment of the liquid crystal layer is controlled according to an electric field applied between a common voltage (Vcom) electrode and a pixel (PXL) electrode provided at a pixel area, so as to adjust the transmittance of light and thereby form an image.
  • Vcom common voltage
  • PXL pixel
  • the LCD device drives a liquid crystal panel in an inversion type in order to prevent degradation of a liquid crystal and improve display quality.
  • a frame inversion type i.e., a frame inversion system
  • a line inversion type i.e., a line inversion system
  • a column inversion type i.e., a line inversion system
  • a dot inversion type i.e., a dot inversion system
  • the frame inversion type, the line inversion type and the column inversion type may reduce power consumption compared to the dot inversion type, but have disadvantages in display quality degradation such as a crosstalk phenomenon or an up-down luminance difference.
  • the dot inversion type may reduce the above-mentioned display quality degradation, and thus may provide an image with quality superior to that of the frame inversion type, the line inversion type and the column inversion type.
  • the dot inversion type has disadvantages in that power consumption is too large compared to the line inversion type or the column inversion type.
  • a type proposed to enhance the above-mentioned problems is a Z-inversion type (i.e., a Z-inversion system).
  • the Z-inversion type is a method in which a Thin Film Transistor (TFT) and a pixel electrode (P) are alternately disposed on left and right of data lines, and a data voltage is provided to the data lines in a column inversion type. That is, the Z-inversion type is an enhanced structure of the column inversion type in which a circuit driving method of the Z-inversion type uses the column inversion, but a screen display is implemented in the same manner as the dot inversion type (i.e., the dot inversion system) by forming TFTs of a liquid crystal panel in an opposite direction with respect to each line.
  • TFT Thin Film Transistor
  • P pixel electrode
  • the Z-inversion type has an effect similar to that of the dot inversion type with regard to display quality, and uses the column inversion type with regard to data.
  • the Z-inversion type is a method capable of providing superior image quality and reducing power consumption.
  • FIGs. 1A and 1B illustrate a thin film transistor positioned in a pixel of a Z-inversion type display device.
  • a channel of a TFT disposed in some pixels is formed in a left direction
  • a channel of a TFT disposed in other pixels is formed in a right direction.
  • a channel of a TFT disposed on the upper side is formed in a left direction
  • a channel 30b of a TFT disposed on the lower side is formed in a right direction.
  • a drain electrode (i.e., an electrode electrically connected to a pixel electrode) of the TFT should be disposed to the left of a source electrode such that the channel is formed in the left direction.
  • the drain electrode of the TFT should be disposed on the right of the source electrode such that the channel is formed in the right direction.
  • a direction in which the drain electrode of the TFT is disposed with respect to the source electrode is different in each pixel. Specifically, the direction in which the drain electrode is disposed with respect to the source electrode in an odd-numbered pixel and the direction in which the drain electrode is disposed with respect to the source electrode in an even-numbered pixel are different.
  • FIG. 1A illustrates a drain electrode position in a normal case.
  • an area where a drain electrode 20a and a gate electrode 10a of the upper TFT of which the channel is formed in the left direction are overlapped is substantially the same as an area where a drain electrode 20b and a gate electrode 10b of the lower TFT of which the channel is formed in the right direction are overlapped.
  • Cgs An area where a drain electrode and a gate electrode of a TFT overlap forms a capacitor having a capacitance, and the capacitance is referred to as Cgs. At this time, the capacitance Cgs is determined according to an overlapped area. In the normal case shown in FIG. 1A , the capacitances Cgs of the above-mentioned two TFTs are the same.
  • FIG. 1B illustrates a drain electrode position in a case in which a gate electrode layer and source/drain electrode layers are horizontally misaligned by 2.5 um.
  • the gate electrode layer and the source/drain electrode layers are formed on different layers using different masks.
  • a reference position of a mask for forming the gate electrode layer and a mask for forming the source/drain electrode layers may be minutely misaligned, for example, the reference position may be horizontally misaligned by 2.5 um.
  • the drain electrode may be formed as shown in FIG. 1B .
  • an area where a drain electrode 20c and a gate electrode 10c of the upper TFT of which the channel is formed in the left direction are overlapped is smaller than an area where a drain electrode 20d and a gate electrode 10d of the lower TFT of which the channel is formed in the right direction are overlapped.
  • the capacitance Cgs lowers a voltage charged in a pixel, due to a coupling phenomenon which is generated during a gate off, a level of the lowering of the charged voltage is differently determined according to the capacitance Cgs. Therefore, when the capacitances Cgs are different in each pixel, the level of the lowering of the charged voltage in each pixel by the capacitances Cgs becomes different, and thus a charged voltage in each pixel becomes different.
  • the gate electrode layer and the source/drain electrode layers may be misaligned for reasons such as a mask misalignment, and, at this time, there are problems in which the capacitances Cgs of each pixel become different.
  • KR20130016922 discloses a Z-inversion type display device which solves this problem by a drain electrode having a central part overlapping the gate electrode and two drain extensions non-overlapping the gate electrode.
  • the preamble of claim 1 is based on this disclosure.
  • US2004104388 discloses a display device, wherein the drain electrode completely overlaps the gate line in order to avoid gate-drain capacitance variations.
  • an aspect of the present invention is to provide a Z-inversion type display device in which a capacitance of Cgs does not change even though a forming position of a source electrode or a drain electrode changes, and a method of manufacturing the Z-inversion type display device.
  • a Z-inversion type display device comprises: a gate line and a data line that intersect with each other to define a pixel area on a substrate; a transistor that includes a gate electrode, a source electrode and a drain electrode, wherein the drain completely overlaps the gate line in plan view; and a pixel electrode that is formed in the pixel area, and is electrically connected to the drain electrode of the transistor.
  • the drain electrode of the transistor has a 'T' shape comprising a horizontal leg and a vertical leg, wherein the horizontal leg of the 'T' shape drain electrode is arranged next to the source electrode and extends in parallel with the source electrode, and wherein the vertical leg of the 'T' shape drain electrode protrudes from the horizontal leg away from the source electrode.
  • the pixel electrode is electrically connected to the drain electrode of the transistor through a contact hole.
  • a method of manufacturing a Z-inversion type display device comprises: forming a gate line and a gate electrode on a substrate; sequentially forming a gate insulating layer and source/drain metal films on the gate electrode, forming a source electrode, a drain electrode and a data line, and forming the drain electrode completely overlaps the gate line in plan view, wherein the drain electrode has a 'T ' shape comprising a horizontal leg and a vertical leg, wherein the horizontal leg of the 'T' shape drain electrode is arranged next to the source electrode, and wherein the vertical leg of the 'T' shape drain electrode protrudes from the horizontal leg away from the source electrode; forming a first protecting layer on the drain electrode, and forming a contact hole on the first protecting layer; and forming a pixel electrode on the first protecting layer through which the contact hole is formed, and forming a second protecting layer on the pixel electrode.
  • first, second, A, B, (a), (b) or the like may be used herein when describing components of the present invention. These terms are merely used to distinguish one structural element from other structural elements, and a property, an order, a sequence and the like of a corresponding structural element are not limited by the term. It should be noted that if it is described in the specification that one component is “connected,” “coupled” or “joined” to another component, a third component may be “connected,” “coupled,” and “joined” between the first and second components, although the first component may be directly connected, coupled or joined to the second component. Likewise, when it is described that a certain element is formed “on” or “under” another element, it should be understood that the certain element may be formed either directly or indirectly via a still another element on or under another element.
  • FIG. 2 is a system configuration diagram of a display device according to an embodiment.
  • a display device 100 may include a panel 110, a data driving unit 120 and a gate driving unit 130.
  • the display device 100 may further include a timing controlling unit 140 according to a configuration of an embodiment. In the following, an embodiment in which the display device 100 includes the timing controlling unit 140 is described.
  • the timing controlling unit 140 may output a Data Control Signal (DCS) for controlling the data driving unit 120 and a Gate Control Signal (GCS) for controlling the gate driving unit 130, based on an external timing signal such as horizontal/vertical synchronization signals (Vsync, Hsync), image data (RGB) and a clock signal (CLK) which are input from a host system (not shown).
  • DCS Data Control Signal
  • GCS Gate Control Signal
  • Vsync, Hsync horizontal/vertical synchronization signals
  • RGB image data
  • CLK clock signal
  • the timing controlling unit 140 may convert the image data (e.g. RGB) input from the host system (not shown) into a data signal form used in the data driving unit 120, and may provide the converted image data (R'G'B') to the data driving unit 120.
  • the timing controlling unit 140 may provide the image data (R'G'B') converted correspondingly to a resolution or a pixel structure of the panel 110.
  • the image data (RGB) and the converted image data (R'G'B') may be referred to as an image signal, image digital data, or data.
  • the data driving unit 120 converts the converted image data (R'G'B') into a data voltage (i.e., an analog pixel signal or a data signal) which is a voltage corresponding to a gray value, and provides the data voltage to a data line, in response to the DCS and the converted image data (R'G'B') input from the timing controlling unit 140.
  • a data voltage i.e., an analog pixel signal or a data signal
  • the gate driving unit 130 sequentially provides a gate signal (i.e., a scan signal, a gate pulse, a scan pulse or a gate on signal) to a gate line, in response to the GCS input from the timing controlling unit 140.
  • a gate signal i.e., a scan signal, a gate pulse, a scan pulse or a gate on signal
  • the panel 110 includes a plurality of pixels P defined by an intersection of a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm.
  • a transistor e.g., a field effect transistor, e.g., a Thin Film Transistor (TFT) connected to the gate line GL and the data line DL and disposed between the gate line GL and the data line DL may be formed.
  • the gate driving unit 130 provides a gate signal to the gate line GL and turns on the TFT to enable the data line DL to be connected to the pixel.
  • a data voltage output from the data driving unit 120 is applied to the pixel connected to the data line DL and an image is displayed.
  • Each pixel may have a different structure according to an image display method.
  • a pixel may have a structure in which a liquid crystal is interposed between both electrodes.
  • the pixel when the panel 110 displays an image according to an organic light emitting method, the pixel may include at least one organic light emitting element including an anode which is a first electrode, a cathode which is a second electrode, and a light emitting layer.
  • the light emitting layer in each organic light emitting element may include at least one light emitting layer among red, green, blue and white light emitting layers, or a white light emitting layer.
  • the panel 110 displays an image according to the liquid crystal display method.
  • the panel 110 may display an image by another method (e.g., the organic light emitting method), and the present invention is not limited such an image display method.
  • the panel 110 includes an array substrate, an upper substrate and a liquid crystal material layer.
  • the array substrate includes a thin film transistor which is a switching element for controlling turning on and turning off of each pixel.
  • the upper substrate includes a color filter and/or a black matrix.
  • the liquid crystal material layer is interposed between the array substrate and the upper substrate.
  • an arrangement state of a liquid crystal layer is controlled according to an electric field applied between a pixel (P) electrode and a common voltage (Vcom) electrode in a pixel area, transmittance of light is controlled by the control of the arrangement state of a liquid crystal, and an image is displayed.
  • an Active Area (AA) which includes at least one pixel displayiing an image and a Non-active Area (NA) are defined.
  • the pixel P is defined by the intersection of the plurality of gate lines GL and the plurality of data lines DL.
  • the TFT is disposed at each intersection points, and each TFT is connected to a transparent pixel electrode formed in each pixel P in one to one correspondence.
  • a plurality of layers such as a gate metal layer, a semiconductor layer, source/drain metal layers, a pixel electrode layer, and a common electrode layer may be formed in order to form the TFT, a line and the like, a dielectric layer, a protecting layer, or the like for insulating each layer or for protecting each layer may be formed.
  • Twisted Nematic (TN) scheme in which a liquid crystal is injected between an array substrate having a pixel electrode formed therein and an upper substrate having a common voltage electrode formed therein, separated from each other, and liquid crystal molecules in a nematic phase are driven in a direction perpendicular to the substrates.
  • a liquid crystal display device of the twisted nematic scheme as described above is disadvantageous in that it has a narrow viewing angle of about 90 degrees.
  • the IPS scheme liquid crystal display device which drives liquid crystal molecules in a direction parallel to the substrate to improve a viewing angle to not less than 170 degrees.
  • the IPS scheme liquid crystal display device includes a type in which basically a pixel electrode and a common electrode are simultaneously formed on a lower substrate or an array substrate, and both electrodes are formed in the same layer, and a Fringe Field Switching (FFS) type in which both electrodes are spaced apart in a horizontal direction by at least one insulating layer, and one electrode has a finger shape.
  • FFS Fringe Field Switching
  • connection pad for connection to a driving unit disposed at an inner or outer portion of the substrate, a signal application pad for applying a reference voltage or reference signals, and various pads for measurement may be formed on a part of the Non-Active area (NA) outside of the Active Area (AA) in the array substrate.
  • the liquid crystal display device drives a liquid crystal panel in an inversion type.
  • a frame inversion type i.e., a frame inversion system
  • a line inversion type i.e., a line inversion system
  • a column inversion type i.e., a line inversion system
  • a dot inversion type i.e., a dot inversion system
  • the frame inversion type, the line inversion type and the column inversion type may reduce power consumption compared to the dot inversion type, but have disadvantages of display quality degradation such as a crosstalk phenomenon or an up-down luminance difference.
  • the dot inversion type may reduce the above-mentioned display quality degradation, and thus may provide an image with quality superior to that of the frame inversion type, the line inversion type and the column inversion type.
  • the dot inversion type has disadvantages in that power consumption is too large compared to that of the line inversion type or the column inversion type.
  • a type proposed to enhance the above-mentioned problems is a Z-inversion type (i.e., a Z-inversion system).
  • the Z-inversion type may be applied to the panel 110 of FIG. 2 .
  • a pixel structure of the Z-inversion type display device is different from other inversion types (e.g., the frame inversion type, the colum inversion type, and the like).
  • FIG. 3 is a pixel structure diagram for a Z-inversion type array substrate which may be applied to the panel of FIG. 2 .
  • FIG. 3 shows an enlarged view of a portion corresponding to some data lines DL1 to DL5 and some gate lines GL1 to GL5 in the panel 110 of FIG. 2 . It may be understood that such a pixel structure is repeated in the remaining portions.
  • the pixels are defined by the intersections of the plurality of gate lines GL1 to GL5 and the plurality of data lines DL1 to DL5.
  • each pixel is connected to the data lines in left and right directions alternately.
  • the TFTs disposed in each pixel are connected to the data lines, source electrodes of the TFTs are connected to the data lines in the left and right directions alternately.
  • a data voltage of a positive polarity (+) is provided to odd-numbered data lines DL1, DL3 and DL5, and a data voltage of a negative polarity (-) is provided to even-numbered data lines DL2 and DL4. Since the TFTs of the pixels are connected to the data lines in the left and right directions alternately, when a data voltage of a specific polarity is provided to one data line, the data voltage is alternately provided to a left pixel of the data line and a right pixel of the data line.
  • the data voltage is provided according to the column inversion type (a type in which data voltages of different polarities are provided to each data line), but an inversion type of the pixel is equal to the dot inversion type (an inversion type in which pixels having the same polarity are not adjacent in horizontal and vertical directions.
  • the dot inversion type an inversion type in which pixels having the same polarity are not adjacent in horizontal and vertical directions.
  • FIG. 4 is a plan view of the array substrate for illustrating a portion of FIG. 3 .
  • FIG. 4 is view for an area 310 of FIG. 3 . It may be understood that the same structure is repeated in the remaining portions.
  • a first gate line 410a is disposed in a direction on a substrate, and a first data line 420a is disposed in a direction perpendicular to the first gate line 410a.
  • a first pixel electrode 444a and a first TFT 430a are disposed on the right side of the first data line 420a, and a first pixel is formed.
  • a second gate line 410b is disposed in parallel with the first gate line 410a
  • a second data line 420b is disposed in parallel with the first data line 420a.
  • a second pixel electrode 444b and a second TFT 430b are disposed on the left side of the second data line 420b, and a second pixel is formed.
  • the first TFT 430a and the second TFT 430b are symmetric in the horizontal direction, and formed in different directions.
  • the first TFT 430a includes a first source electrode 422a, a first drain electrode 432a, and a first gate electrode 412a.
  • the first source electrode 422a is a portion of the first data line 420a which is disposed on the left side thereof and has an 'I' shape.
  • the first drain electrode 432a has a 'T' shape in which a side of the first drain electrode 432a is parallel with the first source electrode 422a and another side of the first drain electrode 432a protrudes.
  • the 'T' shape first drain electrode 432a has a horizontal leg and a vertical leg.
  • the horizontal leg of the 'T' shape drain electrode is arranged adjacent to the first source electrode 422a and extends in parallel with the first source electrode 422a.
  • the vertical leg of the 'T' shape first drain electrode protrudes from the horizontal leg away from the first source electrode 422a.
  • the first TFT 430a is formed in the lower-left side of the first pixel.
  • the second TFT 430b includes a second source electrode 422b, a second drain electrode 432b, and a second gate electrode 412b.
  • the second source electrode 422b is a portion of the second data line 420b which is disposed on the right side thereof and has an ⁇ I' shape.
  • the second drain electrode 432b has a 'T' shape in which a side of the second drain electrode 432b is parallel with the second source electrode 422b and another side of the second drain electrode 432b protrudes.
  • the ⁇ T' shape second drain electrode 432b has a horizontal leg and a vertical leg.
  • the horizontal leg of the 'T' shape second drain electrode is arranged adjacent to the second source electrode 422b and extends in parallel with the second source electrode 422b.
  • the vertical leg of the ⁇ T' shape second drain electrode protrudes from the horizontal leg away from the second source electrode 422b.
  • the second TFT 430b is formed in the lower-right side of the second pixel.
  • the directions of the TFTs in the pixels adjacent in vertical directions are different.
  • a deviation of Cgs may be generated due to a misalignment of the gate electrode layer and source/drain electrode layers.
  • the drain electrode completely overlaps the gate line in order to resolve the Cgs deviation.
  • the first drain electrode 432a of the first TFT 430a completely overlaps the first gate line 410a.
  • the plan view of FIG. 4 shows an overlap shape in which the first drain electrode 432a of the first TFT 430a is wholly included in the first gate line 410a.
  • first drain electrode 432a may overlap (e.g., laterally overlap) the first gate line 410a with a margin.
  • the overlap with the margin means that the first drain electrode 432a is disposed within a margin distance C from an edge of the first gate line 410a.
  • a reference numeral 433a indicates a first drain electrode misaligned by a predetermined distance and formed in another position due to a problem of a process.
  • a first drain electrode' 433a since a misalignment distance is shorter than the margin distance C, the first drain electrode' 433a completely overlaps the first gate line 410a.
  • the second drain electrode 432b completely overlaps the second gate line 410b.
  • the plan view of FIG. 4 shows an overlap shape in which the second drain electrode 432b of the second TFT 430b is wholly included in the second gate line 410b.
  • the second drain electrode 432b may overlap the second gate line 410b with a margin in a method similar to that of the first drain electrode 432a.
  • even source electrode may completely overlap the gate line.
  • the first source electrode 422a of the first TFT 430a is a portion of the first data line 420a and has an 'I' shape.
  • an area of the source electrode may be defined a portion where the data line and the gate line overlap in a data line direction.
  • a portion corresponding to a first source electrode area 423a where the first data line 420a overlap the first gate line 410a corresponds to the first source electrode 422a.
  • the first source electrode 422a since the first source electrode 422a is the portion of the first data line 420a and has the ⁇ I' shape, the first source electrode 422a always overlaps the first gate line 410a in the data line direction. In contrast, the first source electrode 422a may or may not overlap the first gate line 410a in a gate line direction according to a position of the source electrode 422a. In the array substrate shown in FIG. 4 , the first source electrode 422a is positioned so as to completely overlap the first gate line 410a. As described above, an overlap relation may be identified in the plan view, and referring to FIG. 4 , an area of the first source electrode 422a is included in an area of the first gate line 410a.
  • the second source electrode 422b also completely overlap the second gate line 410b in the same manner as the first source electrode 422a.
  • the capacitance (Cgd) formed between the drain electrode and the gate line is uniformly maintained in each pixel. Since the capacitance (Cgd) between the drain electrode and the gate line lowers a charged voltage which is charged in a pixel, like the capacitance Cgs, the capacitance Cgd should be uniform in every pixels. In the array substrate shown in FIG. 4 , since the Cgd is uniformly maintained in each pixel, a flickering problem or a vertical line problem generated due to a nonuniformity between pixels is resolved.
  • a first channel 451a between the first source electrode 422a and the first drain electrode 432a is positioned in order to completely overlap the first gate line 410a.
  • the first channel 451a may overlap the first gate line 410a automatically because the first source electrode 422a and the first drain electrode 432a completely overlap the first gate line 410a.
  • the first channel 451a may be positioned to completely overlap the first gate line 410a autonomously according to a position adjustment by a design.
  • a channel characteristic may be changed according to an area where the channel overlaps the gate line, and as shown in FIG. 4 , when the channel completely overlaps the gate line in each pixel, the channel characteristics of all pixels are the same.
  • the first pixel electrode 444a is electrically connected to the first TFT 430a.
  • the first pixel electrode 444a is electrically connected to the first drain electrode 432a of the first TFT 430a.
  • the first pixel electrode 444a is electrically connected to the vertical leg of the first drain electrode 432a via a contact hole 442a.
  • the contact hole 442a completely overlaps the first gate line 410a.
  • the width of the first gate line 410a may not be uniform.
  • the first gate line 410a may includes portions of different widths.
  • a width of a portion of the first gate line which includes the first contact hole 442a is a width in a direction parallel to the extension of the first data line 420a.
  • a width of a portion of the first gate line which includes the horizontal leg of the 'T' shape first drain electrode is a width in a direction parallel to the extension of the first data line 420a.
  • the width of the portion of the first gate line 410a which accomodates the first contact hole 442a may be different from the width of the portion of the first gate line 410a which accomodates the horizonal leg of the 'T' shape first drain electrode 432a.
  • the width of the portion of the first gate line 410a which accomodates the first contact hole 442a may be smaller than the width of the portion of the first gate line 410a which accomodates the horizonal leg of the first drain electrode 432a.
  • the first gate line 410a may include a first edge and a second edge in parallel to the first data line 420a.
  • the first edge of the first gate line is adjacent to an edge of the horizontal leg of the 'T' shape first drain electrode which faces away the first data line 420a.
  • the second edge of the first gate line is adjacent to the second data line 420b. In other words, the first edge of the first gate line is closer to the first data line 420a and the second edge of the first gate line is closer to the second data line 420b.
  • the second gate line 410b which is parallel to the first gate lines 410a may also include an first edge and second edge in parallel to the second data line 420b.
  • the first edge of the second gate line is adjacent to the first data line 420a.
  • the second edge of the second gate line is adjacent to an edge of the horizontal leg of the 'T' shape second drain electrode which faces away the second data line 420b.
  • the first edge of the second gate line is closer to the first data line 420a and the second edge of the second gate line is closer to the second data line 420b.
  • the first edge of the first gate line (i.e., adjacent to the horizontal leg of the first drain electrode) is closer to the first data line 420a than the second edge of the second gate line (i.e., adjacent to the horizontal leg of the second drain electrode) to the first data line 420a.
  • the first drain electrode 432a is closer to the first data line 420a than the second drain electrode 432b, as shown in FIG. 4 .
  • the second gate line 410b may have the same configuration and similarly accommodate a second contact hole 442b as the first gate line 410a.
  • the first TFT 410a and second TFT 410b form a transistor pair.
  • the first TFT 410a which has a ⁇ T' shape first drain electrode 432a is rotated 90° in a counterclockwise direction and the second TFT 410b which has a 'T' shape second drain electrode 432b is rotated 90° in a clockwise direction.
  • FIG. 5 is a cross-sectional view taken along a line B-B' of FIG. 4 .
  • the first gate line 410a is formed using a metal layer or a metal pattern on a substrate 510 such as an organic substrate, and a gate insulating layer (i.e., a Gate Insulator (GI)) 520 is formed on the first gate line 410a.
  • a gate insulating layer i.e., a Gate Insulator (GI)
  • a semiconductor layer 530 forming the channel of the TFT is formed on the GI 520, and a metal layer or a metal pattern forming the first source electrode 422a and the first drain electrode 432a is laminated on the semiconductor layer 530.
  • a first protecting layer 532 is formed on the first source electrode 422a and the first drain electrode 432a.
  • the first protecting layer 532 may be an inorganic protecting layer formed of inorganic insulating material such as nitride silicon (SiNx) or oxide silicon (SiO2), and may be an organic protecting layer formed of material such as photo-acryl, acrylate and polyamide.
  • the first protecting layer 532 may be a double structure including the inorganic protecting layer and the organic protecting layer.
  • a first contact hole 442a is formed in the first protecting layer 532.
  • a first pixel electrode 444a is electrically connected to the first drain electrode 432a thorugh the first contact hole 442a.
  • a second protecting layer 540 is formed on the first pixel electrode 444a.
  • the second protecting layer 540 may be an inorganic protecting layer formed of inorganic insulating material such as nitride silicon SiNx or oxide silicon SiO2.
  • FIG. 5 shows the first drain electrode 432a formed at a position according to a design value, together with the first drain electrode' 433a which is somewhat moved from the design value and is formed.
  • FIG. 5 shows Cgs 550 formed by the first drain electrode 432a and the first gate line 410a, together with Cgs' 551 formed by the first drain electrode' 433a and the first gate line 410a, for a comparison.
  • an area where the drain electrode 432a disposed to the design value overlaps the first gate line 410a is the same as an area where the drain electrode' 433a moved and is disposed from the design value overlaps the first gate line 410a. This is because the first drain electrode 432a completely overlaps the first gate line 410a. More specifically, in a cross-sectional view of FIG. 5 , this is because both of an area of the first drain electrode 432a and an area of the first drain electrode' 433a are in an area of the first gate line 410a. Therefore, a capacitance Cgs 550 formed by the first drain electrode 432a which is disposed at the design value becomes identical to Cgs' 551 formed by the first drain electrode' 433a.
  • the first source electrode 422a and the semiconductor layer 530 also completely overlap the first gate line 410a.
  • FIGS. 6A to 6D are cross-sectional views taken along a line B-B' for illustrating a manufacturing process for the array substrate of FIG. 4 .
  • the first gate line 410a is formed using a metal layer or a metal pattern on the substrate 510 such as an organic substrate.
  • the gate insulating layer 520 i.e., the Gate Insulator (GI)
  • the GI 520 may be an inorganic insulating material, for example, may be one selected from oxide silicon, nitride silicon or mutliple layers thereof.
  • the metal layer forming the first gate line 410a may have single layer or multiple layers by depositing one or more material selected from copper (Cu), copper alloy, aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo) and molybdenum alloy (MoTi).
  • the semiconductor layer 530 is formed on the GI 520.
  • the semiconductor layer 530 may form a source area and a drain area by doping a P type impurity or an N type impurity, and may define a channel area interposed between the source area and the drain area, simultaneously.
  • a group 3 element such as boron (B), aluminum (Al), gallium (Ga) and indium (In) may be used as the doped impurity.
  • a group 5 element such as phosphorus (P), arsenic (As) and antimony
  • (Sb) may be used as the doped impurity.
  • a hole is used as a carrier in the P type transistor, and an electron is used as a carrier in the N type transistor.
  • source/drain metal films are formed on the semiconductor layer 530, and the first source electrode 422a and the first drain electrode 432a are patterned using a mask process.
  • the first source electrode 422a and the first drain electrode 432a may be formed of a metal material having a low resistance characteristic, such as copper (Cu), copper alloy, aluminum (Al) and aluminum alloy (AlNd).
  • the mask for patterning an electrode may be somewhat moved.
  • the first drain electrode' 433a may be formed, which is somewhat moved from a design value, rather than the first drain electrode 432a corresponding to a position of the design value. Therefore, Cgs' 551 may be formed rather than Cgs 550.
  • the first drain electrode 432a in order to maintain the capacitance Cgs' 551 equally to the capacitance Cgs 550, is formed such that the first drain electrode 432a completely overlaps the first gate line 410a.
  • the first drain electrode 432a in a plan view, is formed such that the area of the first drain electrode 432a is formed within the margin distance from the edge of the area of the first gate line 410a.
  • the margin distance is determined according to an error range of the mask process.
  • the first protecting layer 532 is formed on the first source electrode 422a and the first drain electrode 432a.
  • the first contact hole 442a is formed on the first protecting layer 532
  • the first pixel electrode 444a which is connected to the first drain electrode 432a is formed on the first protecting layer 532
  • the second protecting layer 540 is formed on the first pixel electrode 444a.
  • the first protecting layer 532 or the second protecting layer 540 may be an inorganic protecting layer formed of inorganic insulating material such as nitride silicon (SiNx) or oxide silicon (SiO2), and may be an organic protecting layer formed of material such as photo-acryl, acrylate and polyamide.
  • the first protecting layer 532 or the second protecting layer 540 may be a double structure including the inorganic protecting layer and the organic protecting layer.
  • FIGs. 7A and 7B are views illustrating an opening area of a display device according to an embodiment.
  • FIG. 7A is a plan view of a compared array substrate.
  • FIG. 7B is a plan view of an array substrate according to an embodiment.
  • a source electrode 722a has an 'L' shape, and thus a portion of the source electrode 722a protrudes toward a gate line. Therefore, in the compared array substrate, a contact hole 734a for connecting a pixel electrode 740a is formed at an upper position compared to a data line direction edge of a gate electrode 712a. As described above, when a position of the contact hole 734a moves upward, there is a problem in which an opening area becomes narrower according to the movement of the contact hole 734a.
  • a source electrode 722b has an ⁇ I' shape. Since the source electrode 722b has the ⁇ I' shape, an area occupied by the source electrode 722b in a gate line direction is reduced, and thus an area where other components of a TFT are formed becomes comparatively larger. Therefore, a drain electrode 732b does not move upward, and is formed in parallel with the gate line. Thus, in the array substrate in an embodiment, a contact hole 734b is formed at a lower position compared to a data line direction edge of a gate electrode 712b. As described above, when a position of the contact hole 734b is moved downward, an opening area becomes larger according to the movement of the contact hole 734b. Specifically, in a high resolution panel, an area of each pixel is reduced, and when a source electrode is formed in an ⁇ I' shape like the embodiment in such a panel, an opening ratio may be more increased.
  • FIG. 8 is a pixel structure diagram of another array substrate which may be applied to the panel of FIG. 2 .
  • TFTs are alternately connected to the left side of a data line and the right side of the data line, like a Z-inversion type.
  • the array substrate shown in FIG. 8 is different from the array substrate shown in FIG. 3 , in which the TFTs are alternately connected to the upper side of a gate line and the lower side of the gate line.
  • a deviation of Cgs or Cgd in a vertical direction may be generated due to a misalignment of a mask, like the existing Z-inversion pixel structure.
  • the concept of an embodiment is positioning a drain electrode or a source electrode such that the drain electrode or the source electrode completely overlaps a gate line. As described above, when the drain electrode or the source electrode completely overlaps the gate line, although a mask is misaligned in a vertical direction (i.e., a data line direction), a deviation of Cgs or Cgd is not generated.
  • Cgs when the capacitance Cgs is substantially the same in each pixel, in a display device, there is an effect in which nonuniformity between pixels is removed, and problems such as flickering or a vertical line defect are improved.
  • Cgs may be changed in each pixel according to an error of a process.
  • FIGs. 9A and 9B are views illustrating a flow of a normal Cgs compensation process.
  • FIG. 9A is a Cgs compensation process of a display device having an existing column inversion pixel structure.
  • FIG. 9B is a Cgs compensation process of a display device having an existing Z-inversion pixel structure.
  • an array substrate of a column inversion pixel structure is formed (S1010).
  • Cgs has been compensated through a common voltage (Vcom) compensation.
  • Vcom common voltage
  • the Cgs of all pixels is consistently changed. Thus, in this case, a Cgs deviation between pixels is not generated in one display device.
  • Cgs when Cgs is out of the normal range, since a pixel charged voltage is increased or decreased in all pixels, Cgs should be compensated by controlling a level of the common voltage Vcom, and thus compensating the common voltage Vcom (S1012) is included in a process of the display device having the existing column inversion pixel structure.
  • an array substrate of a Z-inversion pixel structure is formed (S1020).
  • first compensation pattern is formed (S1022).
  • the capacitance Cgs should be increased by adding a compensation pattern to a pixel of which the capacitance Cgs is comparatively small.
  • the capacitance Cgs of all pixels becomes uniform through the forming of the compensation pattern (S1022).
  • the capacitance Cgs is compensated by controlling a level of the common voltage Vcom (S1024).
  • the process of compensating Cgs is necessary in a process. More specifically, in the case of the display device in which a pixel is formed in the Z-inversion method, the two kinds of steps of the forming of the compensation pattern (S1022) and the compensating of the Vcom (S1024) are necessary. In contrast, since the display device according to an embodiment does not have to compensate Cgs, such two kinds of steps may be skipped.
  • the display device does not have to compensate Cgs, and thus the display device according to an embodiment can resolve the above-mentioned problems.

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Claims (13)

  1. Dispositif d'affichage du type à inversion de Z comprenant :
    une grille (410a) et une ligne de données (420a) qui se croisent mutuellement pour définir une zone de pixel sur un substrat (510) ;
    un transistor (430a) qui comprend une électrode de grille (412a), une électrode de source (422a) et une électrode de drain (432a) ; et
    une électrode de pixel (444a) qui est formée dans la zone de pixel, et qui est connectée électriquement à l'électrode de drain du transistor par l'intermédiaire d'un trou de contact (442a) ; caractérisé en ce que l'électrode de drain recouvre complètement la ligne de grille en vue plane,
    dans lequel l'électrode de drain du transistor a la forme d'un `T' comprenant une branche horizontale et une branche verticale, dans lequel la branche horizontale de l'électrode de drain en forme de `T' est agencée à côté de l'électrode de source et s'étend parallèlement à l'électrode de source, et dans lequel la branche verticale de l'électrode de drain en forme de `T' fait saillie de la branche horizontale à l'opposé de l'électrode de source.
  2. Dispositif d'affichage du type à inversion de Z selon la revendication 1, dans lequel
    le trou de contact recouvre complètement la ligne de grille en vue plane.
  3. Dispositif d'affichage du type à inversion de Z selon l'une quelconque des revendications 1 ou 2, dans lequel l'électrode de drain du transistor est positionnée dans les limites d'une distance de marge d'un bord de la ligne de grille, en vue plane.
  4. Dispositif d'affichage du type à inversion de Z selon l'une quelconque des revendications 1 à 3, dans lequel un canal (451 a) entre l'électrode de source et l'électrode de drain du transistor recouvre complètement la ligne de grille.
  5. Dispositif d'affichage du type à inversion de Z selon l'une quelconque des revendications 1 à 4, dans lequel l'électrode de source du transistor, qui est une partie de la ligne de données ou qui est formée par une expansion de la partie, a la forme d'un 'I'.
  6. Dispositif d'affichage du type à inversion de Z selon l'une quelconque des revendications 1 à 5, dans lequel l'électrode de pixel est connectée électriquement à la branche verticale de l'électrode de drain en forme de `T' par l'intermédiaire du trou de contact.
  7. Dispositif d'affichage du type à inversion de Z selon l'une quelconque des revendications 1 à 6, dans lequel une largeur d'une première partie de la ligne de grille comprenant le trou de contact est différente d'une largeur d'une deuxième partie de la ligne de grille comprenant la branche horizontale de l'électrode de drain en forme de 'T'.
  8. Dispositif d'affichage du type à inversion de Z selon l'une quelconque des revendications 1 à 7, comprenant en outre :
    un transistor supplémentaire (430b) comprenant une électrode de drain (432b) ayant la forme d'un 'T' comprenant une branche horizontale et une branche verticale ;
    une ligne de données supplémentaire (420b) à côté de la ligne de données ;
    dans lequel le transistor et le transistor supplémentaire sont agencés dans une région entre la ligne de données et la ligne de données supplémentaire ;
    dans lequel la branche horizontale de l'électrode de drain en forme de 'T' du transistor supplémentaire est couplée à la ligne de données supplémentaire.
  9. Dispositif d'affichage du type à inversion de Z selon la revendication 8, dans lequel le transistor et le transistor supplémentaire forment une paire de transistors ;
    le dispositif d'affichage du type à inversion de Z comprenant en outre au moins une paire de transistors supplémentaire de la même structure que la paire de transistors agencée dans la région entre la ligne de données et la ligne de données supplémentaire.
  10. Dispositif d'affichage du type à inversion de Z selon l'une quelconque des revendications 8 ou 9,
    dans lequel la ligne de grille comprend un bord parallèle à la ligne de données et adjacent à la branche horizontale de l'électrode de drain en forme de 'T' du transistor ;
    le dispositif d'affichage du type à inversion de Z comprenant en outre une ligne de grille supplémentaire (410b) parallèle à la ligne de grille, la ligne de grille supplémentaire comprenant un bord parallèle à la ligne de données supplémentaire et adjacent à la branche horizontale de l'électrode de drain en forme de 'T' du transistor supplémentaire ;
    dans lequel le bord de la ligne de grille est plus proche de la ligne de données que le bord de la ligne de grille supplémentaire l'est de la ligne de données.
  11. Procédé de fabrication du dispositif d'affichage du type à inversion de Z selon la revendication 1, le procédé comprenant :
    la formation de la ligne de grille et de l'électrode de grille sur le substrat ;
    de manière séquentielle, la formation d'une couche isolante de grille (520) et de films métalliques source/drain sur l'électrode de grille, la formation de l'électrode de source, de l'électrode de drain et de la ligne de données par un processus de masquage ;
    la formation d'une première couche de protection (532) sur l'électrode de drain, et la formation du trou de contact à travers la première couche de protection ; et
    la formation de l'électrode de pixel sur la première couche de protection à travers laquelle le trou de contact est formé, et la formation d'une deuxième couche de protection (540) sur l'électrode de pixel.
  12. Procédé selon la revendication 11, dans lequel l'électrode de drain est formée de sorte que l'électrode de drain soit positionnée dans les limites d'une distance de marge d'un bord de la ligne de grille en vue plane en relation avec la distance de marge déterminée conformément à une plage d'erreur du processus de masquage.
  13. Procédé selon l'une quelconque des revendications 11 ou 12, dans lequel l'électrode de source comprend une partie de la ligne de données, et l'électrode de source a la forme d'un 'I'.
EP15165848.1A 2014-04-30 2015-04-30 Dispositif d'affichage d'inversion z et son procédé de fabrication Active EP2940520B1 (fr)

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US9780126B2 (en) 2017-10-03
US9588386B2 (en) 2017-03-07
CN105022198B (zh) 2018-11-23
US20170133405A1 (en) 2017-05-11
CN105022198A (zh) 2015-11-04
EP2940520A1 (fr) 2015-11-04
US20150316825A1 (en) 2015-11-05

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