EP2722993A1 - Codage avec codes polaires poinçonnés pour mémoires non volatiles - Google Patents

Codage avec codes polaires poinçonnés pour mémoires non volatiles Download PDF

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Publication number
EP2722993A1
EP2722993A1 EP13187875.3A EP13187875A EP2722993A1 EP 2722993 A1 EP2722993 A1 EP 2722993A1 EP 13187875 A EP13187875 A EP 13187875A EP 2722993 A1 EP2722993 A1 EP 2722993A1
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EP
European Patent Office
Prior art keywords
bits
locations
punctured
puncturing
word
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP13187875.3A
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German (de)
English (en)
Other versions
EP2722993B1 (fr
Inventor
Dong-Min Shin
Kyeongcheol Yang
Seung-Chan Lim
Kijun Lee
Junjin Kong
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Samsung Electronics Co Ltd
Academy Industry Foundation of POSTECH
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Samsung Electronics Co Ltd
Academy Industry Foundation of POSTECH
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Publication of EP2722993A1 publication Critical patent/EP2722993A1/fr
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1191—Codes on graphs other than LDPC codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0009—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding

Definitions

  • Example embodiments of inventive concepts described herein relate to semiconductor devices, for example, controllers to control nonvolatile memory devices and operating methods of controllers.
  • a semiconductor memory device is a memory device which is fabricated using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), and the like. Semiconductor memory devices are classified into volatile memory devices and nonvolatile memory devices.
  • the volatile memory devices may lose stored contents at power-off.
  • the volatile memory devices include a static RAM (SRAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), and the like.
  • the nonvolatile memory devices may retain stored contents even at power-off.
  • the nonvolatile memory devices include a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a flash memory device, a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), and the like.
  • Errors may be generated at data writing and reading operations.
  • a variety of error correction codes may be applied to a memory controller to detect and correct errors.
  • the error correction codes may include an RS (Reed-Solomon) code, a BCH (Bose-Chaudhuri-Hocquenghem) code, an LDPC (Low Density Parity Check) code, and so on.
  • At least one example embodiment of inventive concepts is directed to an operating method of a controller, which is configured to control a nonvolatile memory device.
  • the operating method includes: selecting bits of a polar encoded code word to be punctured; detecting locations of incapable bits, lost by the puncturing, of an input word of the polar code encoding, based on locations of the bits to be punctured and a structure of a generation matrix associated with the polar code encoding; refreezing the input word such that frozen bits and incapable bits of the input word overlap; generating input word bits by replacing information word bits with frozen bits based on the refreezing result; generating the code word bits by performing generation matrix calculation about the input word bits; generating output bits by puncturing the code word bits based on locations of the bits to be punctured; and transmitting the output bits to the nonvolatile memory device.
  • At least one other example embodiment of inventive concepts is directed to a method of operating a controller for a nonvolatile memory device, the method including: selecting bits of a polar encoded code word to be punctured; determining an error probability associated with bits of an input word based on the selected bits of the polar encoded code word; identifying bits of the input word to be replaced with static bit values based on the determined error probability; generating a modified input word by replacing the identified bits of the input word with the static bit values; generating the polar encoded code word based on the modified input word; puncturing the polar encoded code word to generate an output code word; and transmitting the output code word to the nonvolatile memory device.
  • locations of the frozen bits when the bits to be punctured are selected are different from locations of the frozen bits when the bits to be punctured are not selected.
  • locations of the incapable bits vary when locations of the bits to be punctured vary.
  • the selecting bits to be punctured includes: calculating polarization exponents of the generation matrix calculation unit while varying locations of the bits to be punctured; and selecting locations of the bits of the polar encoded code word having a higher polarization exponent.
  • the selecting bits to be punctuated includes: dividing the generation matrix into a plurality of portions; calculating a polarization exponent of at least one portion of the generation matrix while varying a location of at least one bit to be punctured; and selecting a location of the at least one bit to be punctured having a higher polarization exponent at the at least one portion of the generation matrix.
  • the generation matrix is divided into at least two stages in a direction from an input to an output, each of the at least two stages is divided into a plurality of square matrixes, and the at least one portion of the generation matrix corresponds to at least one square matrix of a stage adjacent to the output.
  • locations of the remaining portions of the generation matrix corresponding to a location of the at least one bit to be punctured are selected as locations of the bits to be punctured.
  • the bits to be punctured are periodically distributed at the code word bits, and the incapable bits are localized in terms of blocks at the input word bits.
  • the refreezing the input word includes: selecting the incapable bits as the frozen bits; and if remaining frozen bits exist after selecting of the incapable bits, calculating density evolution of the code word bits and selecting locations of the remaining frozen bits to have a higher reliability according to the calculated density evolution.
  • At least one other example embodiment of inventive concepts is directed to a controller including: a puncturing bit register configured to store information associated with bits of a polar encoded code word to be punctured; a location providing unit configured to provide locations of the bits to be punctured and frozen bits based on the information associated with the bits to be punctured stored at the puncturing bit register; a frozen bit inserting unit configured to receive information word bits and to generate input word bits by inserting the frozen bits into the information word bits based on the locations of the frozen bits from the location providing unit; a generation matrix calculating unit configured to generate code word bits by calculating a generation matrix with the input word bits; and a puncturing unit configured to generate output bits by puncturing the code word bits based on the locations of the bits to be punctured provided from the location providing unit.
  • At least one other example embodiment of inventive concepts is directed to a controller including: a puncturing bit register configured to store information regarding bits of a polar encoded code word to be punctured; a location providing circuit configured to identify bits of an input word to be replaced with static bit values based on an error probability associated with bits of the input word, the error probability being based on the stored information; a frozen bit inserting circuit configured to generate a modified input word by replacing the identified bits of the input word with the static bit values; a generation matrix calculation circuit configured to generate the polar encoded code word based on the modified input word; a puncturing circuit configured to puncture the polar encoded code word to generate an output code word; and transmitting the output code word to a nonvolatile memory device.
  • the output bits may be transmitted to a nonvolatile memory controlled by the controller.
  • the location providing unit may be further configured to calculate the locations of the bits to be punctured and the frozen bits based on the information of the bits to be punctured and a structure of the generation matrix and/or of the generation matrix calculation unit.
  • the location providing unit is further configured to store a location table and to detect locations of the bits to be punctured and the frozen bits based on the information of the bits to be punctured and the location table.
  • the controller may further include: a decoding unit configured to receive data from a nonvolatile memory controlled by the controller and to perform successive cancelation decoding, message passing decoding, or list decoding on the received data.
  • a decoding unit configured to receive data from a nonvolatile memory controlled by the controller and to perform successive cancelation decoding, message passing decoding, or list decoding on the received data.
  • the controller forms a memory card or a solid state drive with a nonvolatile memory.
  • FIG. 1 is a block diagram schematically illustrating a memory system according to an example embodiment of inventive concepts.
  • FIG. 2 is a block diagram schematically illustrating a nonvolatile memory device according to an example embodiment of inventive concepts.
  • FIG. 3 is a circuit diagram schematically illustrating a memory cell array according to an example embodiment of inventive concepts.
  • FIG. 4 is a circuit diagram schematically illustrating a memory cell array according to another example embodiment of inventive concepts.
  • FIG. 5 is a block diagram schematically illustrating a controller according to an example embodiment of inventive concepts.
  • FIG. 6 is a block diagram schematically illustrating a polar code encoder/decoder according to an example embodiment of inventive concepts.
  • FIG. 7 is a block diagram schematically illustrating a polar code encoding unit according to an example embodiment of inventive concepts.
  • FIGS. 8A and 8B show examples of a generation matrix calculation unit.
  • FIG. 9 shows still another example of a generation matrix calculation unit.
  • FIG. 10 shows an example in which punctuation is applied to a generation matrix calculation unit of FIG. 9 .
  • FIG. 11 is a block diagram schematically illustrating a polar code encoding unit according to another example embodiment of inventive concepts.
  • FIG. 12 is a flow chart schematically illustrating an operation of a polar code encoding unit.
  • FIG. 13 shows a refrozen result of a generation matrix calculation unit of FIG. 10 .
  • FIG. 14 is a flow chart schematically illustrating a punctuation bit selecting operation of FIG. 12 according to an example embodiment of inventive concepts.
  • FIG. 15 is a flow chart schematically illustrating a punctuation bit selecting operation of FIG. 12 according to another example embodiment of inventive concepts.
  • FIG. 16 shows an example of division of a generation matrix calculation unit.
  • FIG. 17 shows a first example of selection of punctuation bits.
  • FIG. 18 shows a second example of selection of punctuation bits.
  • FIG. 19 is a flow chart schematically illustrating a refrozen performing method according to an example embodiment of inventive concepts.
  • FIG. 20 is a block diagram schematically illustrating a polar code encoding unit according to an example embodiment of inventive concepts.
  • FIG. 21 is a flow chart schematically illustrating an operation of a polar code encoding unit in FIG. 20 .
  • FIG. 22 is a block diagram illustrating an application of a memory system in FIG. 1 .
  • FIG. 23 is a diagram illustrating a memory card according to an example embodiment of inventive concepts.
  • FIG. 24 is a diagram illustrating a solid state drive according to an example embodiment of inventive concepts.
  • FIG. 25 is a block diagram schematically illustrating a computing system according to an example embodiment of inventive concepts.
  • first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.
  • spatially relative terms such as “beneath”, “below”, “lower”, “under”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below.
  • the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • a layer when referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
  • FIG. 1 is a block diagram schematically illustrating a memory system according to an example embodiment of inventive concepts.
  • a memory system 1000 may include a nonvolatile memory device 1100 and a controller 1200.
  • the nonvolatile memory device 1100 may be configured to perform write, read, and erase operations according to a control of the controller 1200.
  • the controller 1200 may be connected to a host and the nonvolatile memory device 1100.
  • the controller 1200 may access the nonvolatile memory device 1100 in response to a request from the host.
  • the controller 1200 may be configured to control write, read, and erase operations of the nonvolatile memory device 1100.
  • the controller 1200 may be configured to provide an interface between the nonvolatile memory device 1100 and the host.
  • the controller 1200 may be configured to drive firmware for controlling the nonvolatile memory device 1100.
  • the controller 1200 may receive data from the host.
  • the controller 1200 may encode the input data to generate coded data DATA_C.
  • the controller 1200 may be configured to provide a control signal CTRL and an address ADDR to the nonvolatile memory device 1100.
  • the controller 1200 may be configured to exchange the coded data DATA_C with the nonvolatile memory device 1100.
  • the controller 1200 may receive the coded data DATA_C from the nonvolatile memory device 1100 to decode the coded data DATA_C.
  • the controller 1200 may transfer the decoded data to the host.
  • FIG. 2 is a block diagram schematically illustrating a nonvolatile memory device according to an example embodiment of inventive concepts.
  • a nonvolatile memory device 1100 may include a memory cell array 1110, an address decoder 1120, a read/write circuit 1130, and control logic 1140.
  • the memory cell array 1110 may be connected to the address decoder 1120 via word lines WL and to the read/write circuit 130 via bit lines BL.
  • the memory cell array 1110 may include a plurality of memory cells. Memory cells arranged in a row direction may be connected with word lines, and memory cells arranged in a column direction may be connected with bit lines. For example, memory cells arranged in a column direction may form a plurality of cell groups (e.g., strings). The plurality of cell groups may be connected to bit lines, respectively. In example embodiments, each of memory cells may store one or more bits of data.
  • the address decoder 1120 may be connected to the memory cell array 1110 through the word lines WL.
  • the address decoder 1120 may operate responsive to a control of the control logic 1140.
  • the address decoder 1120 may receive an address ADDR from an external device.
  • the address decoder 1120 may be configured to decode a row address of the input address ADDR.
  • the address decoder 1120 may select the word lines WL using the decoded row address.
  • the address decoder 1120 may be configured to decode a column address of the input address ADDR.
  • the decoded column address DCA may be transferred to the read/write circuit 1130.
  • the address decoder 1120 may include components such as a row decoder, a column decoder, an address buffer, and so on.
  • the read/write circuit 1130 may be connected to the memory cell array 1110 through the bit lines BL, and may exchange coded data DATA_C with the external device.
  • the read/write circuit 1130 may operate responsive to a control of the control logic 1140.
  • the read/write circuit 1130 may select the bit lines BL in response to the decoded column address DCA.
  • the read/write circuit 1130 may receive the coded data DATA_C from the external device to write it at the memory cell array 1110.
  • the read/write circuit 1130 may read coded data DATA_C from the memory cell array 1110 to transfer it to the external device.
  • the read/write circuit 1130 may read data from a first storage region of the memory cell array 1110 to write it at a second storage region of the memory cell array 1110.
  • the read/write circuit 1130 may be configured to perform a copy-back operation.
  • the read/write circuit 1130 may include constituent elements such as a page buffer (or, a page register), a column selecting circuit, a data buffer, and so on. In other example embodiment, the read/write circuit 1130 may include constituent elements such as a sense amplifier, a write driver, a column selecting circuit, a data buffer, and the like.
  • the control logic 1140 may be connected to the address decoder 1120 and the read/write circuit 1130.
  • the control logic 1140 may be configured to control an overall operation of the nonvolatile memory device 1100.
  • FIG. 3 is a circuit diagram schematically illustrating a memory cell array according to an example embodiment of inventive concepts.
  • memory cells MC1 to MCm provided along a row direction may be connected with word lines WL1 to WLm.
  • Memory cells in the same row may be connected with the same word line WL.
  • Memory cells MC1 to MCm provided along a column direction may correspond to bit lines BL1 to BLn, respectively. Memory cells MC1 to MCm in the same column may correspond to the same bit line BL.
  • String selection transistors SST may be connected between the bit lines BL1 to BLn and the memory cells MC1 to MCm.
  • the string selection transistors SST may be connected with a string selection line SSL.
  • Ground selection transistors GST may be connected between the memory cells MC1 to MCm and a common source line CSL.
  • the ground selection transistors GST may be connected with a ground selection line GSL.
  • a memory cell array 1110a may be a planar NAND flash memory array.
  • FIG. 4 is a circuit diagram schematically illustrating a memory cell array according to another example embodiment of inventive concepts.
  • cell strings CS11, CS12, CS21, and CS22 may be provided between bit lines BL1 and BL2 and a common source line CSL.
  • the cell strings CS11 and CS21 may be connected between the first bit line BL1 and the common source line CSL.
  • the cell strings CS12 and CS22 may be connected between the second bit line BL2 and the common source line CSL.
  • Memory cells at the same height may be connected in common with a word line (or, a dummy word line).
  • a voltage when a voltage is applied to a word line (or, a dummy word line) at a specific word line, it may be applied to all cell strings CS11, CS12, CS21, and CS22.
  • Cell strings at different rows may be connected to different string selection lines SSL1 and SSL2, respectively.
  • the cell strings CS11, CS12, CS21, and CS22 may be selected or unselected by a row unit by selecting or unselecting the first and second string selection lines SSL1 and SSL2.
  • cell strings cell strings CS11 and CS12 or CS21 and CS22 connected with an unselected string selection line SSL1 or SSL2 may be electrically isolated from the bit lines BL1 and BL2.
  • Cell strings cell strings CS21 and CS22 or CS11 and CS12 connected with a selected string selection line SSL2 or SSL1 may be electrically connected with the bit lines BL1 and BL2.
  • the cell strings CS11, CS12, CS21, and CS22 may be connected with the bit lines BL1 and BL2 by a column unit.
  • the cell strings CS11 and CS21 may be connected with the first bit line BL1, and the cell strings CS12 and CS22 may be connected with the second bit line BL2.
  • the cell strings CS11, CS12, CS21, and CS22 may be selected or unselected by a column unit by selecting or unselecting the bit lines BL1 and BL2.
  • a memory cell array 1110b may be a vertical NAND flash memory array.
  • a nonvolatile memory device 1100 may include a NAND flash memory device. However, inventive concepts are not limited thereto.
  • the nonvolatile memory device 1100 may include a variety of nonvolatile memory devices necessitating error correction.
  • the nonvolatile memory device 1100 may include a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), and so on.
  • PRAM phase-change RAM
  • MRAM magnetic RAM
  • RRAM resistive RAM
  • FRAM ferroelectric RAM
  • FIG. 5 is a block diagram schematically illustrating a controller according to an example embodiment of inventive concepts.
  • a controller 1200 may include a system bus 1210, a processor 1220, a RAM 1230, a host interface 1240, a memory interface 1250, and a polar code encoder/decoder 1260.
  • the system bus 1210 may provide a channel among the components 1220 to 1260 of the controller 1200.
  • the processor 1220 may control an overall operation of the controller 1200.
  • the RAM 1230 may be used as at least one of a working memory, a cache memory, and a buffer memory.
  • the host interface 1240 may communicate with an external device (e.g., the host) via at least one of various communications standards such as USB (Universal Serial Bus), MMC (multimedia card), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer small interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), and a Firewire.
  • various communications standards such as USB (Universal Serial Bus), MMC (multimedia card), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer small interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), and a Firewire.
  • the memory interface 1250 may interface with a nonvolatile memory device 1100 (refer to FIG. 1 ).
  • the memory interface 1250 may include a NAND interface or a NOR interface.
  • the polar code encoder/decoder 1260 may perform polar code encoding on data received from an external host and polar code decoding on data received from the nonvolatile memory device 1100.
  • FIG. 6 is a block diagram schematically illustrating a polar code encoder/decoder according to an example embodiment of inventive concepts.
  • a polar code encoder/decoder 1260 may include a polar code encoding unit 1261 and a successive canceling unit 1267.
  • the polar code encoding unit 1261 may receive k information word bits I(k) (k being a positive integer).
  • the information word bits I(k) may be received from a host.
  • the polar code encoding unit 1261 may perform polar code encoding on the information word bits I(k) to generate n code word bits C(n) (n being an integer larger than k).
  • the code word bits C(n) may be programmed at a nonvolatile memory device 1100.
  • Data programmed at the nonvolatile memory device 1100 may be read as n read bits Y(n).
  • the successive canceling unit 1267 may perform successive cancelation decoding on the read bits Y(n) to generate k information word bits O(k).
  • the nonvolatile memory device 1100 may be understood to be a channel where code word bits C(n) encoded by the polar code encoding unit 1261 are transferred.
  • the polar code encoder/decoder 1260 may include the successive canceling unit 1267.
  • inventive concepts are not limited thereto.
  • the successive canceling unit 1267 may be replaced with a function block which performs decoding using one of various decoding algorithms such as message passing decoding, list decoding, and so on.
  • FIG. 7 is a block diagram schematically illustrating a polar code encoding unit according to an example embodiment of inventive concepts.
  • a polar code encoding unit 1261 may include a frozen bit inserting unit 1262 and a generation matrix calculation unit 1263.
  • the frozen bit inserting unit 1262 may receive information word bits I(k).
  • the frozen bit inserting unit 1262 may insert frozen bits into the information word bits I(k).
  • the frozen bits may be static bits fixed to a logical value such "1" or "0". That is, the frozen bits may be bits having a fixed logic value (e.g., "0" or "1").
  • the frozen bit inserting unit 1262 may insert frozen bits into a head or tail of the information word bits I(k) or into a given, desired or predetermined location between the head and the tail of the information word bits I(k). Locations where frozen bits are inserted may be locations decided such that an error prevention function of the polar code encoder/decoder 1260 is optimized.
  • the frozen bit inserting unit 1262 may generate input word bits U(n) by inserting frozen bits into the information word bits I(k).
  • the generation matrix calculation unit 1263 may receive the input word bits U(n) from the frozen bit inserting unit 1262.
  • the generation matrix calculation unit 1263 may generate code word bits C(n) by performing generation matrix calculation on the input word bits U(n) based on a given, desired or predetermined generation matrix.
  • FIGS. 8A and 8B show examples of a generation matrix calculation unit 1263.
  • a generation matrix calculation unit 1263_1 based a 2-by-2 generation matrix.
  • a first code word bit C(1) may be a sum of first and second input word bits U(1) and U(2).
  • a second code word bit C(2) may be a second input word bit U(2).
  • a first code word bit C(1) may be a sum of first and second input word bits U(1) and U(2).
  • a second code word bit C(2) may be a sum of second and third input word bits U(2) and U(3).
  • a third code word bit C(3) may be a third input word bit U(3).
  • a generation matrix may be generated by a combination of unit matrixes having a given, desired or predetermined size as illustrated in FIGS. 8A and 8B .
  • the generation matrix may be generated based a Kronecker product of unit matrixes.
  • the length of code word bits C(n) or input word bits U(n) supported by a generation matrix calculation unit 1263 may be limited to combinations of unit matrixes.
  • Puncturing may be applied to support code word bits C(n) or input word bits U(n) having a length.
  • the puncturing may be a method of puncturing some bits of the code word bits C(n). Punctured bits may not be transferred to a channel, and bits not punctured may be transferred to the channel. That is, if puncturing is used, lengths of code word bits C(n) or input word bits U(n) may be adjusted within a range at which the reliability on error correction is secured.
  • FIG. 9 shows still another example of a generation matrix calculation unit.
  • a generation matrix calculation unit based on an 8-by-8 generation matrix.
  • the 8-by-8 generation matrix may be generated by a Kronecker product of 2-by-2 unit matrix.
  • a generation matrix calculation unit 1263_3 may receive first to eighth input word bits U(1) to U(8) to output first to eighth code word bits C(1) to C(8).
  • the third to sixth input word bits U(3) to U(6) may be frozen bits. Since a bit error rate (BER) of the third to sixth input word bits U(3) to U(6) may be higher than that of the first, second, seventh, and eighth input word bits U(1), U(2), U(7), and U(8), the third to sixth input word bits U(3) to U(6) may be selected as frozen bits.
  • BER bit error rate
  • FIG. 10 shows an example in which puncturing is applied to a generation matrix calculation unit of FIG. 9 .
  • first, third, fourth, and eighth code word bits C(1), C(3), C(4), and C(8) may be punctured. If locations of puncturing bits PUNC are decided, locations of incapable bits INC may be decided.
  • the incapable bits INC may be input word bits which have a relatively high probability of having errors after transmission due to puncturing. For example, the incapable bits INC may be input word bits which are not transferred through a channel due to puncturing.
  • the incapable bits INC may be decided by the following calculation.
  • a punctuation variable IO(n) indicating whether each bit of the code word C(n) is a puncturing bit PUNC.
  • the puncturing variable IO(n) may be "0".
  • the puncturing variable IO(n) may be "1 ".
  • a location variable L(n) indicating a location of an input word bit U(n).
  • the location variable L(i) corresponding to an i-th input word bit U(i) may have a value expressed by the binary numeral.
  • a value of the location variable L(i) may be expressed by binary bits.
  • Respective bits of the location variable L(i) may be defined by b0, b1, b2, ..., bn from a most significant bit (MSB) to a least significant bit (LSB).
  • a sign “ ⁇ ” may indicate an AND operation
  • a sign “ ⁇ ” may indicate an OR operation
  • Calculation of the formula 1 may be performed based on a value of a specific location variable L(j). If a value of the puncturing variable In(1) is "0" after the equation 1 is calculated, an input word bit U(j) of a location corresponding to the location variable L(j) may be an incapable bit INC. If a value of the puncturing variable In(1) is "1", an input word bit U(j) of a location corresponding to the location variable L(j) may not be an incapable bit INC.
  • one incapable bit INC may be generated when one puncturing bit PUNC is set.
  • third to sixth input word bits U(3) to U(6) may be frozen bits.
  • First to third and fifth input word bits U(1) to U(3) and U(5) may be incapable bits.
  • first and second input word bits U(1) and U(2) are information word bits I(n) not being frozen bits FR, they may not be transferred to a nonvolatile memory device 1100. That is, if puncturing is applied to a polar code encoder/decoder 1260, loss of information word bits I(n) may be generated. In this case, it is impossible to normally decode information word bits I(n) at polar code decoding. This may mean that the reliability of a memory system 1000 (refer to FIG. 1 ) is lowered.
  • polar code encoding may be controlled such that incapable bits INC and frozen bits FR overlap. If incapable bits INC and frozen bits FR overlap, such a problem that information word bits I(n) are lost without transmission to a channel may be solved.
  • polar code encoder/decoder which supports code word bits C(n) or input word bits I(n) having any length.
  • FIG. 11 is a block diagram schematically illustrating a polar code encoding unit according to another example embodiment of inventive concepts.
  • a polar code encoding unit 1261a may include a frozen bit inserting unit 1262a, a generation matrix calculation unit 1263a, a puncturing unit 1264a, a puncturing bit register 1265a, and a location calculation unit 1266a.
  • the frozen bit inserting unit 1262a may be configured to insert frozen bits FR into information word bits I(k). In example embodiments, when puncturing bits PUNC are not selected, the frozen bit inserting unit 1262a may insert frozen bits FR at reference locations of the information word bits I(k). The reference locations may be stored at the frozen bit inserting unit 1262a. The reference bits may be provided to the location calculation unit 1266a.
  • the frozen bit inserting unit 1262a may receive information about locations of frozen bits FR from the location calculation unit 1266a. Locations of the frozen bits FR received from the location calculation unit 1266a may include locations of incapable bits INC. That is, for example, locations of the incapable bits INC may overlap with locations of the frozen bits FR. If the incapable bits INC and the frozen bits FR overlap, loss of information word bits I(k) due to puncturing may be suppressed and/or prevented.
  • the frozen bit inserting unit 1262a may output input word bits U(n) by inserting frozen bits FR into the information word bits I(k).
  • the generation matrix calculation unit 1263a may receive the input word bits U(n) from the frozen bit inserting unit 1262a. The generation matrix calculation unit 1263a may calculate a generation matrix on the input word bits U(n). The generation matrix calculation unit 1263a may output code word bits C(n) by calculating the generation matrix.
  • the puncturing unit 1264a may receive the code word bits C(n) from the generation matrix calculation unit 1263a.
  • the puncturing unit 1264a may receive information about locations of puncturing bits PUNC from the location calculation unit 1266a.
  • the puncturing unit 1264a may puncture the code word bits C(n) based on the input information.
  • the puncturing unit 1264a may puncture the code word bits C(n) to output m output bits P(m) (m being a positive integer less than n).
  • the puncturing bit register 1265a may be configured to store information about puncturing bits PUNC.
  • the puncturing bit register 1265a may be accessed from an external device of a controller 1200 (refer to FIG. 5 ).
  • the puncturing bit register 1265a may be a one-time programmable (OTP) register.
  • OTP one-time programmable
  • the puncturing bit register 1265a may store information about the number of puncturing bits PUNC.
  • the location calculation unit 1266a may receive information (e.g., the number of puncturing bits PUNC) about puncturing bits PUNC from the puncturing bit register 1265a.
  • the location calculation unit 1266a may calculate locations of frozen bits FR based on the input information.
  • the location calculation unit 1266a may receive information about the number and locations of puncturing bits PUNC from the puncturing bit register 1265a.
  • the location calculation unit 1266a may calculate locations of incapable bits INC based on information about locations of puncturing bits PUNC and a structure of a generation matrix calculation unit 1263a.
  • the location calculation unit 1266a may adjust locations of frozen bits FR such that the frozen bits overlap with the incapable bits INC.
  • An operation of adjusting locations of the frozen bits FR may be referred to refrozen.
  • Information associated with a structure of the generation matrix calculation unit 1263a may be stored (e.g., previously stored) at the location calculation unit 1266a.
  • Information associated with a structure of the generation matrix calculation unit 1263a may include an algorithm for calculating locations of incapable bits INC from locations of puncturing bits PUNC based on a structure of the generation matrix calculation unit 1263a as described with reference to the equation 1.
  • the location calculation unit 1266a may receive information about the number of puncturing bits PUNC from the puncturing bit register 1265a.
  • the location calculation unit 1266a may calculate locations of puncturing bits PUNC based on information about the number of puncturing bits PUNC and information associated with a structure of the generation matrix calculation unit 1263a. For example, the location calculation unit 1266a may calculate locations of puncturing bits PUNC such that a bit error rate BER of a polar code encoder/decoder 1260 (refer to FIG. 5 ) is reduced and/or minimized. Afterwards, the location calculation unit 1266a may perform refrozen.
  • FIG. 12 is a flow chart schematically illustrating an operation of a polar code encoding unit 1261a.
  • puncturing bits PUNC may be selected.
  • the puncturing bits PUNC may be selected by storing information of the puncturing bits PUNC at a puncturing bit register 1265a or reading information of the puncturing bits PUNC from puncturing bit register 1265a.
  • the number of the puncturing bits PUNC or the number and locations of the puncturing bits PUNC may be selected.
  • selecting of the puncturing bits PUNC may further include an operation of calculating locations of the puncturing bits PUNC.
  • locations of incapable bits INC may be detected based on locations of the puncturing bits PUNC and information associated with a generation matrix calculation unit 1263a.
  • the operation S120 may be performed by the location calculation unit 1266a.
  • refreezing may be performed such that frozen bits FR overlap with incapable bits INC.
  • the refreezing may be performed by the location calculation unit 1266a.
  • a frozen bit inserting unit 1262a may generate input word bits U(n) by inserting the frozen bits FR to information word bits I(k) based on a refrozen result.
  • a generation matrix calculation unit 1263a may generate code word bits by performing generation matrix calculation on the input word bits U(n).
  • a puncturing unit 1264a may generate output bits P(m) by puncturing the code word bits C(n) based on locations of the puncturing bits PUNC.
  • the output bits P(m) may be transmitted to a nonvolatile memory device 1100 (refer to FIG. 1 ).
  • the nonvolatile memory device 1100 may program the input output bits P(m).
  • FIG. 13 shows a refrozen result of a generation matrix calculation unit 1263_3 of FIG. 10 .
  • frozen bits FR may be moved to overlap with incapable bits INC. If the frozen bits FR overlap with the incapable bits INC, then loss of information word bits I(k) may be suppressed and/or prevented, and a polar code encoder/decoder 1260 may be provided which maintains the reliability and supports a code word C(n) having a variable length.
  • FIG. 14 is a flow chart schematically illustrating a puncturing bit selecting operation of FIG. 12 according to an example embodiment of inventive concepts.
  • FIG. 14 there may be illustrated a manner of calculating locations of puncturing bits PUNC when information about the number of puncturing bits is stored at a puncturing bit register 1264a.
  • the operation of FIG. 14 may be executed by a location calculation unit 1266a.
  • polarization exponents of a generation matrix calculation unit 1263a may be calculated while varying locations of puncturing bits PUNC.
  • locations of the puncturing bits PUNC having a higher polarization exponent e.g., the highest polarization exponent
  • locations of the puncturing bits PUNC having a higher polarization exponent are selected, then a polarization exponent of a generation matrix calculation unit 1263a may be optimized. If the polarization exponent of the generation matrix calculation unit 1263a is optimized, then a bit error rate BER of a polar code encoder/decoder 1260 (refer to FIG. 5 ) may be reduced and/or minimized.
  • FIG. 15 is a flow chart schematically illustrating a puncturing bit selecting operation of FIG. 12 according to another example embodiment of inventive concepts.
  • a generation matrix calculation unit 1263a may be divided into a plurality of portions.
  • polarization exponents of at least one portion of the generation matrix calculation unit 1263a may be calculated while varying a location of at least one punctuation bit.
  • a time taken to search all locations of puncturing bits PUNC may be long.
  • the generation matrix calculation unit 1263a may be divided into a plurality of portions, and polarization exponents on one of the plurality of portions may be calculated.
  • At least one puncturing bit in the at least one portion of the generation matrix calculation unit 1263a may be selected.
  • a bit having the same location as the at least one puncturing bit selected may be selected as a puncturing bit.
  • locations of puncturing bits PUNC having a reduced bit error rate BER may be searched by searching one portion of the generation matrix calculation unit 1263a, not the whole of the generation matrix calculation unit 1263a.
  • Variables N1 and N2 may be defined to divide the generation matrix calculation unit 1263a.
  • the variables N1 and N2 may be defined by the following equation 2.
  • N ⁇ 1 2 k
  • N ⁇ 2 2 m - k
  • a code length of a code word C(n) may be 2 ⁇ m, and "k” may be a positive integer less than "m”.
  • the variables N1 and N2 may be expressed by the base 2 exponentiation. However, inventive concepts are not limited thereto.
  • the variables N1 and N2 may be expressed by a composite number.
  • the variables N1 and N2 may be expressed by the following equation 3.
  • N ⁇ 1 p ⁇ 1 n ⁇ 1
  • N ⁇ 2 p ⁇ 2 n ⁇ 2
  • a generation matrix of the generation matrix calculation unit 1263a may be expressed by the following equation 4, based on the equation 3.
  • G I N ⁇ 1 ⁇ G N ⁇ 2 ⁇ D I N ⁇ 2 ⁇ G N ⁇ 1
  • an operator ( ⁇ ) may indicate a Kronecker product
  • a matrix (Ia) may indicate an Identity matrix having a size of aXa
  • a matrix (D) may indicate a permutation matrix having the same length as a code word C(n).
  • the generation matrix calculation unit 1263a may be divided into a portion corresponding to the variable N1 and portions corresponding to the variable N2 by a variable (k).
  • the portions corresponding to the variables N1 and N2 may correspond to respective stages.
  • FIG. 16 there may be illustrated a generation matrix calculation unit 1263 divided when the variable (k) is 2.
  • FIG. 16 shows an example of division of a generation matrix calculation unit.
  • a generation matrix calculation unit 1263a may be divided into a plurality of stages (e.g., two stages). Each stage may be divided into a plurality of portions by a square matrix unit.
  • a first stage may include a plurality of blocks S1_1 to S1_N1. Each block in the first stage may receive N2 input word bits.
  • a second stage may include a plurality of blocks S2_1 to S2_N1. Each block in the second stage may receive N1 input word bits.
  • polarization exponents according to a location of a puncturing bit may be calculated at one of the blocks S2_1 to S2_N2 in the second state.
  • a location, corresponding to the highest polarization exponent, from among locations of a puncturing bit may be selected as a location of a puncturing bit.
  • code word bits at the selected location may be selected as puncturing bits PUNC.
  • a first example of selection of puncturing bits may be illustrated in FIG. 17 .
  • a first code word bit may be selected as a puncturing bit. That is, in the second stage, locations of puncturing bits PUNC may be periodic.
  • incapable bits INC may be shown in terms of block (or, to be blockwise) at a first stage. For example, input word bits of a first block S1_1 of a plurality of blocks S1_1 to S1_N1 in the first stage may be incapable bits INC.
  • FIG. 18 A second example of selection of puncturing bits may be illustrated in FIG. 18 .
  • second code word bits of blocks S2_1 to S2_N2 in a second stage may be selected as puncturing bits.
  • input word bits of a third block S1_3 in a first stage may be further selected as incapable bits INC.
  • FIG. 19 is a flow chart schematically illustrating a refreezing method according to an example embodiment of inventive concepts.
  • the refreezing method in FIG. 19 may correspond to operation S130 in FIG. 12 .
  • incapable bits may be selected as frozen bits.
  • whether remaining frozen bits exist may be determined. For example, when the number of incapable bits is less than the number of frozen bits, remaining frozen bits may exist. If the number of incapable bits is equal or more than the number of frozen bits, then frozen bits may not exist. If frozen bits do not exist, then refreezing may be ended. If remaining frozen bits exist, then the method proceeds to operation S430.
  • density evolution on code word bits C(n) may be calculated. For example, density evolution on output bits P(m), not punctured, from among the code word bits C(n) may be calculated. The density evolution may be calculated based on a log likelihood ratio (LLR) of the code word bits C(n).
  • LLR log likelihood ratio
  • the LLR of the code word bits C(n) may be L1(n).
  • Probability density functions of the log likelihood ratios L1(n) may be P1(L1(n)). If density evolution is calculated, log likelihood ratios L2(n) of input word bits U(n) and probability density functions P2(L2(n)) of the log likelihood ratios L2(n) may be acquired using the probability density functions P1(L1(n)) of the code word bits C(n).
  • remaining frozen bits may be selected to have the higher (e.g., highest) reliability.
  • a bit error rate Pe of an input word bit may be defined by the following equation 5.
  • P e j , u j , ⁇ u ⁇ ⁇ - ⁇ 1 ⁇ P ⁇ 2 L ⁇ 2 j d L ⁇ 2 j
  • log likelihood ratios of punctured code word bits may vary. If log likelihood ratios of punctured code word bits vary, then the whole probability density functions P1(L1(n)) of the code word bits C(n) may vary. If density evolution may be calculated based on the varied probability density functions P1(L1(n)), then a reliability order of the input word bits may vary. Thus, input word bits selected as frozen bits may also vary.
  • frozen bits FR may exist at reference locations. If the code word bits C(n) are punctured, then locations of the frozen bits FR may vary. For example, locations of the frozen bits may be varied to include incapable bits INC and changed according to a reliability order of input word bits U(n).
  • FIG. 20 is a block diagram schematically illustrating a polar code encoding unit according to an example embodiment of inventive concepts.
  • a polar code encoding unit 1261b may include a frozen bit inserting unit 1262b, a generation matrix calculation unit 1263b, a puncturing unit 1264b, a puncturing bit register 1265b, and a location table 1266b.
  • the frozen bit inserting unit 1262b, the generation matrix calculation unit 1263b, the puncturing unit 1264b, and the puncturing bit register 1265b may operate substantially the same as the frozen bit inserting unit 1262a, the generation matrix calculation unit 1263a, the puncturing unit 1264a, and the puncturing bit register 1265a described with reference to FIG. 11 . Accordingly, a description of these components is omitted.
  • the location table 1266b may store information associated with puncturing bits PUNC, incapable bits INC, and frozen bits FR. For example, when the number and locations of puncturing bits PUNC are stored at the puncturing bit register 1265b, the location table 1266b may store locations of the frozen bits FR according to locations of puncturing bits PUNC. When the number of the puncturing bits PUNC is stored at the puncturing bit register 1265b, the location table 1266b may store locations of puncturing bits PUNC according to puncturing bits PUNC and locations of the frozen bits FR according to the locations of the puncturing bits PUNC.
  • Locations of the frozen bits FR stored in the location table 1266b may include locations of incapable bits INC. As the number or locations of the puncturing bits PUNC vary, the location table 1266b may provide locations of different frozen bits FR.
  • Information stored in the location table 1266b may be previously stored when a controller 1200 (refer to FIG. 5 ) is fabricated.
  • FIG. 21 is a flow chart schematically illustrating an operation of a polar code encoding unit in FIG. 20 .
  • the number of puncturing bits PUNC may be received.
  • the number of puncturing bits PUNC may be received by storing information about the number of puncturing bits PUNC at a puncturing bit register 1265b or reading information about the number of puncturing bits PUNC from the puncturing bit register 1265b.
  • locations of puncturing bits PUNC and frozen bits FR and including incapable bits INC may be detected using a location table 1266b.
  • An operation of detecting locations of the puncturing bits PUNC and the frozen bits FR may correspond to operations S120 and S130 in FIG. 12 .
  • Calculation on locations of puncturing bits PUNC, calculation on locations of incapable bits INC, and refrozen of frozen bits FR may be skipped by referring to the location table 1266b.
  • input word bits U(n) may be generated by inserting frozen bits FR to information word bits I(k) based on locations of frozen bits.
  • a generation matrix on the input word bits U(n) may be calculated to generate code word bits C(n).
  • output bits P(m) may be generated by puncturing code word bits C(n) based on the locations of the puncturing bits PUNC.
  • the output bits P(m) may be sent to a nonvolatile memory device 1100 (refer to FIG. 1 ).
  • Operations S530 to S560 may correspond to operations S140 to S170 in FIG. 12 , respectively.
  • FIG. 22 is a block diagram illustrating an application of a memory system in FIG. 1 .
  • a memory system 2000 may include a nonvolatile memory 2100 and a controller 2200.
  • the nonvolatile memory 2100 may include a plurality of nonvolatile memory chips, which form a plurality of groups. Nonvolatile memory chips in each group may be configured to communicate with the controller 2200 via one common channel.
  • the plurality of nonvolatile memory chips may communicate with the controller 2200 via a plurality of channels CH1 to CHk.
  • FIG.22 there is described such as case that one channel is connected with a plurality of nonvolatile memory chips.
  • the memory system 2000 can be modified such that one channel is connected with one nonvolatile memory chip.
  • FIG. 23 is a diagram illustrating a memory card according to an example embodiment of inventive concepts.
  • a memory card 3000 may include a nonvolatile memory 3100, a controller 3200, and a connector 3300.
  • the connector 4300 may connect the memory card 3000 electrically with a host.
  • the memory card 3000 may be formed of memory cards such as a PC (PCMCIA) card, a CF card, an SM (or, SMC) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), a security card (SD, miniSD, microSD, SDHC), a universal flash storage (UFS) device, and so on.
  • PC PC
  • CF Compact Disc
  • SM or, SMC
  • MMCmicro multimedia card
  • SD miniSD
  • microSD microSD
  • SDHC universal flash storage
  • UFS universal flash storage
  • FIG. 24 is a diagram illustrating a solid state drive according to an example embodiment of inventive concepts.
  • a solid state drive 4000 may include a plurality of nonvolatile memories 4100, a controller 4200, and a connector 4300.
  • the connector 4300 may connect the solid state driver 4000 electrically with a host.
  • FIG. 25 is a block diagram schematically illustrating a computing system according to an example embodiment of inventive concepts.
  • a computing system 5000 may include a bus 5100, a processor 5200, a memory system 5300, a modem 5400, and a user interface 5500.
  • the bus 5100 may provide a channel among components of the computing system 5000.
  • the processor 5200 may control an overall operation of the computing system 5000 and perform a logical operation.
  • the memory system 5300 may include a memory system 1000 or 2000 according to an example embodiment of inventive concepts.
  • the memory system 5300 can be used as a working memory or storage of the computing system 5000.
  • the working memory may be a storage space which the processor 5200 uses to control the computing system 5000.
  • the storage may be a storage space which the computing system 5000 uses to retain data for the long term.
  • the computing system 5000 may further include separate storage.
  • the computing system 5000 may further include a separate working memory.
  • the modem 5400 may perform wire or wireless communications with an external device.
  • the user interface 5500 may include user input interfaces such as a camera, a keyboard, a mouse, a microphone, a touch pad, a touch panel, a button, a sensor, and so on and user output interfaces such as a display, a speaker, a ramp, a motor, and so on.
  • user input interfaces such as a camera, a keyboard, a mouse, a microphone, a touch pad, a touch panel, a button, a sensor, and so on
  • user output interfaces such as a display, a speaker, a ramp, a motor, and so on.
  • the computing system 5000 may be mobile multimedia devices such as a smart phone, a smart pad, and so on or multimedia devices such as a smart television, a smart monitor, a computer, a notebook computer, and so on.
  • a code word encoded may be punctured, and an input word may be refrozen. If the input word is refrozen, lowering of the reliability due to puncturing may be suppressed and/or prevented. Thus, it is possible to support code words having various lengths using a polar code encoder/decoder over maintaining the reliability.

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