EP2696350A2 - Nichtflüchtiges speicherelement, elektronisches steuersystem und verfahren zum betreiben des nichtflüchtigen speicherelements - Google Patents

Nichtflüchtiges speicherelement, elektronisches steuersystem und verfahren zum betreiben des nichtflüchtigen speicherelements Download PDF

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Publication number
EP2696350A2
EP2696350A2 EP12764518.2A EP12764518A EP2696350A2 EP 2696350 A2 EP2696350 A2 EP 2696350A2 EP 12764518 A EP12764518 A EP 12764518A EP 2696350 A2 EP2696350 A2 EP 2696350A2
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EP
European Patent Office
Prior art keywords
page
nand cell
data
pages
cell array
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Withdrawn
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EP12764518.2A
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English (en)
French (fr)
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EP2696350A4 (de
Inventor
Myoung Kyu Seo
Yong Soo Kim
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Industrial Bank of Korea
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ATO SOLUTION CO Ltd
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Publication of EP2696350A2 publication Critical patent/EP2696350A2/de
Publication of EP2696350A4 publication Critical patent/EP2696350A4/de
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0688—Non-volatile semiconductor memory arrays
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series

Definitions

  • the present invention relates to a semiconductor device and a method of controlling the same, and more particularly, to a non-volatile memory device, an electronic control system using the same, and a method of operating the non-volatile memory device and the electronic control system.
  • a non-volatile memory device such as a flash memory not only has excellent data retention characteristics, and but also has low power consumption and high impact-resistant characteristics in comparison to a hard disk.
  • a flash memory having a NOR structure allows high-speed random access and thus is used to store codes
  • a flash memory having a NAND structure has a high level of integration and allows a page operation, and thus is generally used to store data.
  • the above-described flash memory is required to sequentially exchange data with a host according to a product or an interface.
  • NOR flash memory may read and prepare to output data of a page while data of another page is output.
  • NOR flash memory having a low capacity may not completely read and prepare to output data of a page while data of another page is output.
  • a start address for starting to read data is located near a last part of a page, continuous reading of pages may not be easily acheived.
  • the present invention is aimed to solve various problems including the above-described problem, and provides a non-volatile memory device capable of continuously reading data, an electronic control system using the non-volatile memory device, and a method of operating the non-volatile memory device.
  • the scope of the present invention is not limited thereto.
  • a non-volatile memory device including a first NAND cell array including a first group of pages, and a second NAND cell array including a second group of pages.
  • a plurality of X-decoders are at least one-to-one connected to the first and second NAND cell arrays.
  • a control logic controls the plurality of X-decoders to simultaneously sense data of a first page corresponding to a start address from among the first group of pages, and data of a second page subsequent to the first page from among the second group of pages.
  • control logic controls the plurality of X-decoders to sense data of a third page subsequent to the second page while the data of the second page is output to an external apparatus.
  • the first group of pages may include the third page, and the third page may be disposed in a row next to the first page.
  • the non-volatile memory device may further include a third NAND cell array including a third group of pages, and the third group of pages may include the third page.
  • the non-volatile memory device may further include a plurality of page buffers at least one-to-one connected to the first and second NAND cell arrays so as to sense and latch data of the first and second NAND cell arrays.
  • the non-volatile memory device may further include an input address detection unit for detecting the start address.
  • control logic may continuously output data of the first and second NAND cell arrays from the start address via a serial peripheral interface (SPI) to an external apparatus with no latency between pages.
  • SPI serial peripheral interface
  • a non-volatile memory device including a plurality of NAND cell arrays each including a plurality of pages.
  • a plurality of X-decoders are at least one-to-one connected to the plurality of NAND cell arrays.
  • a plurality of page buffers are at least one-to-one connected to the plurality of NAND cell arrays so as to sense and latch data of the plurality of NAND cell arrays.
  • a control logic controls the plurality of X-decoders to simultaneously sense data of a first page of a first NAND cell array corresponding to a start address from among the plurality of NAND cell arrays, and data of a second page of a second NAND cell array subsequent to the first page, in order to sequentially output the data of the plurality of NAND cell arrays from the start address.
  • a non-volatile memory device including a plurality of NAND cell arrays each including a plurality of pages.
  • a plurality of X-decoders are at least one-to-one connected to the plurality of NAND cell arrays.
  • a plurality of page buffers are at least one-to-one connected to the plurality of NAND cell arrays so as to sense and latch data of the plurality of NAND cell arrays.
  • a control logic controls a data read operation so as to sequentially output data of the plurality of NAND cell arrays from a start address via a serial peripheral interface (SPI) to an external apparatus with no latency between pages.
  • SPI serial peripheral interface
  • an electronic control system including a host; and a memory chip for exchanging data with the host via a serial peripheral interface (SPI).
  • the memory chip includes at least one of the above-described non-volatile memory devices.
  • a method of operating a non-volatile memory device includes detecting a start address of a first NAND cell array including a first group of pages, and a second NAND cell array including a second group of pages; and simultaneously sensing data of a first page corresponding to the start address from among the first group of pages, and data of a second page subsequent to the first page from among the second group of pages.
  • the method may further include sensing data of a third page subsequent to the second page while the data of the second page is output to an external apparatus.
  • the simultaneous sensing may include sensing and latching the data of the first and second pages respectively on first and second page buffers corresponding to the first and second pages.
  • a chip structure and an operating method capable of increasing data capacity by using NAND cell arrays and of allowing high-speed data output may be provided. For example, when data is output from NAND cell arrays, all data from a start address may be sequentially and continuously output with no latency between pages.
  • a non-volatile memory device may refer to a memory device capable of retaining data even when power is cut off.
  • the non-volatile memory device may include a flash memory, an electrically erasable programmable read-only memory (EEPROM), a phase-change random access memory (PRAM), a magnetic random access memory (MRAM), or a resistive random access memory (RRAM).
  • the flash memory may also be referred to as a floating gate memory, a charge trapping memory, or a silicon-oxide-nitride-oxide-silicon (SONOS) memory, and the above names do not limit the scope of the embodiments.
  • SONOS silicon-oxide-nitride-oxide-silicon
  • a NAND cell array may refer to an array of memory cells having a NAND structure.
  • FIG. 1 is a block diagram of a non-volatile memory device 100 according to an embodiment of the present invention.
  • FIG. 2 is a circuit diagram of an example of a portion of a NAND cell array in the non-volatile memory device 100 of FIG. 1 .
  • NAND cell arrays 110a and 110b may be separate from each other and may be aligned in parallel.
  • the NAND cell array 110a may include a group of pages LP
  • the NAND cell array 110b may include another group of pages RP.
  • the group of the pages LP and the other group of the pages RP may be separate from each other and may be aligned in parallel.
  • the NAND cell arrays 110a and 110b may have the same structure and may be aligned in a line in a row direction.
  • the group of the pages LP may form left half pages
  • the other group of the pages RP may form right half pages.
  • each of the NAND cell arrays 110a and 110b may include a plurality of memory cells MC aligned in a matrix.
  • the memory cells MC aligned in the same column may be connected to each other in series, and the memory cell MC disposed at one end of each column may be connected to a bit line and the other end of each column may be connected to a common source line CSL.
  • the bit-lines BL may extend in a column direction and may be connected to sources and drains of the memory cells MC, and word-lines WL may extend in a row direction and may be coupled to control gates of the memory cells MC.
  • a connection between a first word-line WL0 and the bit-lines BL may be controlled by a string selection line SSL.
  • the string selection line SSL may be connected to gates of string selection transistors.
  • a connection between the memory cells MC and the common source line CSL may be controlled by a ground selection line GSL.
  • the ground selection line GSL may be connected to gates of ground selection transistors.
  • the memory cells MC aligned in each row may form a page (see LP and RP of FIG. 1 ).
  • a first page LP-0 of the NAND cell array 110a and a first page RP-0 of the NAND cell array 110b may include the memory cells MC connected to the first word-line WLO.
  • an nth page LP-n of the NAND cell array 110a and an nth page RP-n of the NAND cell array 110b may include the memory cells MC connected to an nth word-line WLn.
  • the non-volatile memory device 100 may provide a cell structure capable of increasing data capacity by using the NAND cell arrays 110a and 110b and of achieving high-speed output as described below even when one serial output terminal is used.
  • each of the NAND cell arrays 110a and 110b may include a structure in which a plurality of blocks each having the circuit structure of FIG. 2 are connected.
  • the number of bit-lines BL and the number of word-lines WL in one block may be appropriately selected according to a block size, and do not limit the scope of the current embodiment.
  • each of the NAND cell arrays 110a and 110b may operate by separating the bit-lines BL into even bit-lines and odd bit-lines.
  • the NAND cell array 110a may be connected to an X-decoder 115a, and the NAND cell array 110b may be connected to an X-decoder 115b.
  • the X-decoders 115a and 115b may be separate from each other and may be aligned in parallel.
  • the X-decoder 115a may be connected to the pages LP and may control the word-lines WL in the NAND cell array 110a
  • the X-decoder 115b may be connected to the pages RP and may control the word-lines WL in the NAND cell array 110b. If the NAND cell arrays 110a and 110b have the same memory capacity, the X-decoders 115a and 115b may have the same structure.
  • the X-decoder 115a may include a decoding unit for decoding address information of the memory cells MC in the NAND cell array 110a, and an X-multiplexer/driver for driving the pages LP according to the address information.
  • the X-decoder 115b may include a decoding unit for decoding address information of the memory cells MC in the NAND cell array 110b, and an X-multiplexer/driver for driving the pages RP according to the address information.
  • the two groups of the pages LP and RP may be sequentially or simultaneously driven by individually using the two X-decoders 115a and 115b.
  • the NAND cell arrays 110a and 110b may be one-to-one connected to page buffers 120a and 120b.
  • the bit-lines BL of the NAND cell array 110a may be connected to the page buffer 120a
  • the bit-lines BL of the NAND cell array 110b may be connected to the page buffer 120b. Since the page buffers 120a and 120b are separate from each other as described above, operations of the NAND cell arrays 110a and 110b may be independently performed.
  • Each of the page buffers 120a and 120b may include a sense amplifier for sensing and latching data.
  • the sense amplifier may include a sense unit and a latch unit. If the NAND cell arrays 110a and 110b have the same memory capacity, the page buffers 120a and 120b may have the same structure. If the NAND cell arrays 110a and 110b operate by separating even columns from odd columns, the capacity of each of the page buffers 120a and 120b may correspond to 1/2 of the capacity of each of the NAND cell arrays 110a and 110b.
  • the page buffers 120a and 120b may be connected to an input/output (I/O) buffer & latch unit 150 via a multiplexer latch unit 140.
  • the I/O buffer & latch unit 150 may be connected to an I/O interface 160.
  • the I/O buffer & latch unit 150 may be used as a data buffer during data input and output between the I/O interface 160 and an external apparatus.
  • the I/O interface 160 may include a serial peripheral interface (SPI) or a parallel interface.
  • SPI serial peripheral interface
  • the multiplexer latch unit 140 may adjust data output from the page buffers 120a and 120b to the I/O buffer & latch unit 150, or data input from the I/O buffer & latch unit 150 to the page buffers 120a and 120b.
  • a control logic 130 may control the X-decoders 115a and 115b in order to control read and write operations of the NAND cell arrays 110a and 110b, and may control the multiplexer latch unit 140 in order to control data input and output of the page buffers 120a and 120b.
  • the control logic 130 may form a read control circuit when data of the NAND cell arrays 110a and 110b are sequentially and continuously output as described below.
  • the control logic 130 is illustrated to mainly control a multiplexer.
  • the control logic 130 is not limited thereto and may control all core and peripheral circuits of the non-volatile memory device 100.
  • An input address detection unit 135 may be connected to the control logic 130 so as to provide start address information in a read operation.
  • the input address detection unit 135 may perform an operation of detecting and latching input address information.
  • the input address detection unit 135 may detect and latch the start address information.
  • the NAND cell arrays 110a and 110b, the pages LP, the X-decoders 115a and 115b, and the page buffers 120a and 120b may be separately referred by using ordinal numbers (e.g., first and second).
  • a NAND cell array corresponding to a start address in a read operation may be referred to as a first NAND cell array
  • another NAND cell array may be referred to as a second NAND cell array.
  • the first NAND cell array may include a first group of pages
  • the second NAND cell array may include a second group of pages.
  • the first NAND cell array may be connected to a first X-decoder and a first page buffer
  • the second NAND cell array may be connected to a second X-decoder and a second page buffer.
  • FIG. 3 is a block diagram of a non-volatile memory device 100a according to another embodiment of the present invention.
  • the non-volatile memory device 100a according to the current embodiment is partially modified from the non-volatile memory device 100 of FIG. 1 , and thus repeated descriptions in the two embodiments are not provided here.
  • the non-volatile memory device 100a may include NAND cell arrays 110a, 110b, 110c, and 110d.
  • the NAND cell arrays 110a, 110b, 110c, and 110d may be formed in the same structure and may have the same capacity.
  • the illustrated number and alignment of the NAND cell arrays 110a, 110b, 110c, and 110d are exemplarily provided.
  • one of the NAND cell arrays 110a, 110b, 110c, and 110d may be omitted, or a plurality of NAND cell arrays (not shown) may be added.
  • the NAND cell arrays 110a, 110b, 110c, and 110d are aligned in a line, they may be aligned in two or more lines.
  • X-decoders 115a, 115b, 115c, and 115d may be one-to-one connected to the NAND cell arrays 110a, 110b, 110c, and 110d in a row direction, and page buffers 120a, 120b, 120c, and 120d may be one-to-one connected to the NAND cell arrays 110a, 110b, 110c, and 110d in a column direction.
  • the X-decoder 115a and the page buffer 120a may be connected to the NAND cell array 110a
  • the X-decoder 115b and the page buffer 120b may be connected to the NAND cell array 110b
  • the X-decoder 115c and the page buffer 120c may be connected to the NAND cell array 110c
  • the X-decoder 115d and the page buffer 120d may be connected to the NAND cell array 110d.
  • the page buffers 120a, 120b, 120c, and 120d may be connected so as to exchange data with the multiplexer latch unit 140.
  • the control logic 130 may be connected to the X-decoders 115a, 115b, 115c, and 115d, and the multiplexer latch unit 140 so as to control operation of the non-volatile memory device 100a.
  • the NAND cell arrays 110a, 110b, 110c, and 110d, the X-decoders 115a, 115b, 115c, and 115d, and the page buffers 120a, 120b, 120c, and 120d may be separately referred by using ordinal numbers (e.g., first through fourth).
  • a NAND cell array corresponding to a start address in a read operation may be referred to as a first NAND cell array
  • subsequent NAND cell arrays may be referred to as a second NAND cell array, a third NAND cell array, and a fourth NAND cell array.
  • the first NAND cell array may be connected to a first X-decoder and a first page buffer
  • the second NAND cell array may be connected to a second X-decoder and a second page buffer
  • the third NAND cell array may be connected to a third X-decoder and a third page buffer
  • the fourth NAND cell array may be connected to a fourth X-decoder and a fourth page buffer.
  • FIG. 4 is a block diagram of an electronic control system 200 according to an embodiment of the present invention.
  • a host 210 and a memory chip 220 may be connected to each other so as to exchange data via an interface 240.
  • the interface 240 may include an SPI.
  • the host 210 may operate as a master device, and the memory chip 220 may operate as a slave device.
  • data may be transmitted between the memory chip 220 and the host 210 via one pin.
  • the memory chip 220 may include at least one of the above-described non-volatile memory devices 100 and 100a.
  • the host 210 may include a controller for controlling the memory chip 220, for example, a central processing unit (CPU).
  • the electronic control system 200 may further include an I/O apparatus (not shown) for transmitting and receiving data to and from an external apparatus.
  • the host 210 may receive an input of data via the I/O apparatus so as to store the data in the memory chip 220, or may output the data stored in the memory chip 220 via the I/O apparatus.
  • the above-described electronic control system 200 may include a computer, a cellular phone, a mobile device, a personal digital assistant (PDA), a navigation device, or a home appliance.
  • PDA personal digital assistant
  • FIGS. 5 through 8 A continuous read operation of a non-volatile memory device according to an embodiment of the present invention will now be described with reference to FIGS. 5 through 8 .
  • a start address in NAND cell arrays is detected (S10). Then, data of a first page corresponding to the start address in a first NAND cell array and data of a second page subsequent to the first page in a second NAND cell array are simultaneously sensed (S20). For example, data may be sensed and latched on a first page buffer by driving a first X-decoder connected to the first NAND cell array and, at the same time, data may be sensed and latched on a second page buffer by driving a second X-decoder connected to the second NAND cell array.
  • the data of the first page and/or the data of the second page may be output to an external apparatus and, while the data is output, data of a third page subsequent to the second page may be sensed (S30).
  • data may be sensed and latched on a third page buffer by driving a third X-decoder connected to the third page.
  • the third page may be included in the first NAND cell array or a third NAND cell array. If the third page is included in the first NAND cell array, the third X-decoder may be the same as the first X-decoder.
  • data of a fourth page subsequent to the third page may be output to the external apparatus (S40).
  • data may be sensed and latched on a fourth page buffer by driving a fourth X-decoder connected to the fourth page.
  • the fourth page may be included in the first or second NAND cell array. Operation S40 may be repeated to sequentially and continuously output all data to the external apparatus.
  • FIGS. 6 and 7 are block diagrams for describing a method of operating a non-volatile memory device based on the location of a start address SA, according to an embodiment of the present invention.
  • FIG. 8 is a timing diagram of a method of operating a non-volatile memory device according to embodiments of the present invention.
  • data of a first page LP-0 corresponding to the start address SA and data of a second page RP-0 subsequent to the first page LP-0 may be simultaneously sensed (1).
  • the first page LP-0 may be included in the NAND cell array 110a
  • the second page RP-0 may be included in the NAND cell array 110b.
  • the data of the first and second pages LP-0 and RP-0 may be respectively sensed and latched on the page buffers 120a and 120b.
  • data of a third page LP-1 may be sensed and latched on the page buffer 120a (2).
  • the third page LP-1 may be included in the NAND cell array 110a, and may be disposed in a row directly under the first page LP-0.
  • data of a subsequent fourth page RP-1 may be sensed (3).
  • the fourth page RP-1 may be included in the NAND cell array 110b, and the data of the fourth page RP-1 may be latched on the page buffer 120b.
  • data of a subsequent fifth page LP-2 may be sensed (4).
  • the fifth page LP-2 may be included in the NAND cell array 110a, and the data of the fifth page LP-2 may be latched on the page buffer 120a.
  • the data of the first through fourth pages LP-0, RP-0, LP-1, and RP-1 from the start address SA may be sequentially and continuously output.
  • data from the start address SA may be continuously output with no latency between pages.
  • all data from the start address SA may be continuously output with no latency.
  • data of a first page RP-0 corresponding to the start address SA and data of a second page LP-1 subsequent to the first page RP-0 may be simultaneously sensed (1).
  • the first page RP-0 may be included in the NAND cell array 110b
  • the second page LP-1 may be included in the NAND cell array 110a.
  • the data of the first and second pages RP-0 and LP-1 may be respectively sensed and latched on the page buffers 120b and 120a.
  • the data of the first and second pages RP-0 and LP-1 may be simultaneously sensed.
  • the reason why the data of the first and second pages RP-0 and LP-1 are simultaneously sensed is because the start address SA of the first page RP-0 is located near the last column in a first row. As such, the data of the subsequent second page LP-1 may not be easily sensed within a short time for outputting the data of the first page RP-0 from the start address SA.
  • a predetermined latency is provided after the data of the first page RP-0 is output, and thus a time for reading the data of the second page LP-1 is ensured.
  • the data of the first through fourth pages RP-0, LP-1, RP-1, and LP-2 from the start address SA may be sequentially and continuously output.
  • data from the start address SA may be continuously output with no latency between pages.
  • all data from the start address SA may be continuously output with no latency.
  • data may be read at a high speed and thus a read performance of a non-volatile memory device may be improved.
  • the above high-speed continuous read performance may satisfy the standard of a product using an SPI, as illustrated in FIG. 8 .
  • a chip selection signal is input to a chip selection terminal CS#
  • an instruction and an address may be sequentially input to a serial input terminal SI according to a clock signal of a serial clock terminal SCK.
  • data D1, D2, etc. may be sequentially output to a serial output terminal SO with no latency.
  • FIGS. 9 through 12 are block diagrams for describing a method of operating a non-volatile memory device based on the location of a start address, according to another embodiment of the present invention.
  • the method according to the current embodiment is partially modified from the method of FIGS. 6 and 7 , and thus repeated descriptions in the two embodiments are not provided here.
  • start address SA corresponds to the NAND cell array 110a
  • data of first and second pages of the NAND cell arrays 110a and 110b may be simultaneously sensed and latched (1).
  • data of a subsequent third page of the NAND cell array 110c may be sensed and latched (2).
  • data of a subsequent fourth page of the NAND cell array 110d may be sensed and latched (3).
  • data of a subsequent fifth page of the NAND cell array 110a may be sensed and latched (4).
  • start address SA corresponds to the NAND cell array 110b
  • data of first and second pages of the NAND cell arrays 110b and 110c may be simultaneously sensed and latched (1).
  • data of a subsequent third page of the NAND cell array 110d may be sensed and latched (2).
  • data of a subsequent fourth page of the NAND cell array 110a may be sensed and latched (3),
  • data of a subsequent fifth page of the NAND cell array 110b may be sensed and latched (4).
  • start address SA corresponds to the NAND cell array 110c
  • data of first and second pages of the NAND cell arrays 110c and 110d may be simultaneously sensed and latched (1).
  • data of a subsequent third page of the NAND cell array 110a may be sensed and latched (2).
  • data of a subsequent fourth page of the NAND cell array 110b may be sensed and latched (3).
  • data of a subsequent fifth page of the NAND cell array 110c may be sensed and latched (4).
  • start address SA corresponds to the NAND cell array 110d
  • data of first and second pages of the NAND cell arrays 110d and 110a may be simultaneously sensed and latched (1).
  • data of a subsequent third page of the NAND cell array 110b may be sensed and latched (2).
  • data of a subsequent fourth page of the NAND cell array 110c may be sensed and latched (3).
  • data of a subsequent fifth page of the NAND cell array 110d may be sensed and latched (4).
  • data of first through fourth pages from the start address SA may be sequentially and continuously output with no latency between pages.
  • all data from the start address SA of the first page may be sequentially and continuously output with no latency between pages.
  • the above operation performance may satisfy the standard of a product required to continuously read data at a high speed with no latency between pages. For example, if data is output by using one serial output terminal (see SO of FIG. 8 ), the performance of a product may be improved.
EP12764518.2A 2011-04-01 2012-03-22 Nichtflüchtiges speicherelement, elektronisches steuersystem und verfahren zum betreiben des nichtflüchtigen speicherelements Withdrawn EP2696350A4 (de)

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KR1020110030143A KR101293223B1 (ko) 2011-04-01 2011-04-01 비휘발성 메모리 소자, 전자제어 시스템, 및 비휘발성 메모리 소자의 동작방법
PCT/KR2012/002047 WO2012134096A2 (ko) 2011-04-01 2012-03-22 비휘발성 메모리 소자, 전자제어 시스템, 및 비휘발성 메모리 소자의 동작방법

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JP6453492B1 (ja) 2018-01-09 2019-01-16 ウィンボンド エレクトロニクス コーポレーション 半導体記憶装置

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WO2012134096A2 (ko) 2012-10-04
CN103608867B (zh) 2016-03-30
US20140223080A1 (en) 2014-08-07
KR20120111579A (ko) 2012-10-10
US9262099B2 (en) 2016-02-16
WO2012134096A9 (ko) 2013-10-17
KR101293223B1 (ko) 2013-08-05
EP2696350A4 (de) 2015-02-25
WO2012134096A3 (ko) 2012-12-13

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