EP2482315B1 - Halbleiterbauelement - Google Patents

Halbleiterbauelement Download PDF

Info

Publication number
EP2482315B1
EP2482315B1 EP11833583.5A EP11833583A EP2482315B1 EP 2482315 B1 EP2482315 B1 EP 2482315B1 EP 11833583 A EP11833583 A EP 11833583A EP 2482315 B1 EP2482315 B1 EP 2482315B1
Authority
EP
European Patent Office
Prior art keywords
channel layer
identified
region
potential
diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
EP11833583.5A
Other languages
English (en)
French (fr)
Other versions
EP2482315A4 (de
EP2482315A1 (de
Inventor
Makoto Kitabatake
Masao Uchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Intellectual Property Management Co Ltd
Original Assignee
Panasonic Intellectual Property Management Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Intellectual Property Management Co Ltd filed Critical Panasonic Intellectual Property Management Co Ltd
Publication of EP2482315A1 publication Critical patent/EP2482315A1/de
Publication of EP2482315A4 publication Critical patent/EP2482315A4/de
Application granted granted Critical
Publication of EP2482315B1 publication Critical patent/EP2482315B1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827Vertical transistors
    • H01L29/7828Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692Surface layout
    • H01L29/0696Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391Gated diode structures

Definitions

  • the present invention relates to a semiconductor element and more particularly relates to a wide-bandgap semiconductor element (as a power semiconductor device), which can be used in applications that require a high breakdown voltage and a large amount of current.
  • a Si semiconductor element is generally used in order to control a high breakdown voltage and a huge amount of current in a voltage transformer, for example. More particularly, as a Si transistor functioning as a switch for a voltage transformer, an insulated gate bipolar transistor (IGBT), which can control a high breakdown voltage and a huge amount of current and which has a low ON-state resistance, is used.
  • IGBT insulated gate bipolar transistor
  • a Si-IGBT with a vertical structure is virtually always used to control as high a breakdown voltage as 600 V or more and as large an amount of current as 10 A or more.
  • the upper surface of the element including a gate that functions as a switch to turn the ON and OFF states of current has the same structure as a gate-channel portion of a metal-insulator-semiconductor field effect transistor (MISFET) with an insulated gate.
  • MISFET metal-insulator-semiconductor field effect transistor
  • a structure similar to a DIMISFET double implanted MISFET is fabricated in such a vertical Si-IGBT structure.
  • FIG. 7(a) is a cross-sectional view illustrating the structure of a Si semiconductor element (which may be a Si-IGBT or a MISFET) 1100.
  • the semiconductor element 1100 is made of a silicon (Si) semiconductor. If the semiconductor element is implemented as an IGBT, the element has a structure in which an n - -drift layer 120 is stacked on a p-type Si substrate 110. On the other hand, if the semiconductor element is implemented as a MISFET, the n - -drift layer 120 is stacked on an n + -Si substrate. As can be seen from the plan view shown in FIG.
  • a p-body region 130 has been defined in an upper portion of the n - -drift layer 120. And on a plan view as viewed from right over the principal surface of the substrate, a p-body contact region 132 and an n + -source region 140 are defined in an upper portion of an internal part of the p-body region 130.
  • a source electrode 145 has been formed on the p-body contact region 132 and the n + -source region 140.
  • On the surface of the p-body region 130 there is a channel region 151, on which a gate insulating film 160 and a gate electrode 165 have been stacked in this order.
  • On a plan view as viewed from right over the principal surface of the substrate there is an n-type region, which does not include the p-body region 130, on the surface of the drift layer 120.
  • a portion of the drift layer 120 that is interposed between two p-body regions 130 will be referred to herein as a "JFET region" 121.
  • a drain electrode 170 has been formed on the back surface of the Si substrate 110.
  • the source electrode 145 and the drain electrode 170 function as an emitter electrode and a collector electrode, respectively.
  • a “switching operation” refers to the ability to switch the ON and OFF states of current with the voltage applied between the source electrode 145 and the gate electrode 165 when a DC voltage is applied so that the drain electrode 170 has a positive potential and the source electrode 145 has a negative potential.
  • a voltage that is equal to or higher than a threshold voltage is applied between the source electrode 145 and the gate electrode 165 so that the gate electrode 165 has a positive potential, the channel region 151 gets depleted and becomes an inversion region. In that case, electrons are ready to move from the source region 140 toward the JFET region 121 via the channel region 151. That is to say, current flows.
  • This structure is sometimes modified in order to make a huge amount of current flow by adding a channel layer 150 as shown in FIG. 7(c) .
  • a channel layer 150 as shown in FIG. 7(c) .
  • the switching operation is performed when a positive DC voltage is applied to the drain electrode 170 and a negative DC voltage is applied to the source electrode 145. If DC voltages of opposite polarities are applied (i.e., negative and positive voltages are applied to the drain electrode 170 and the source electrode 145, respectively), then the MISFET performs a diode operation. This is because a body diode 180 is formed by the pn junction between the p-body region 130 and the n - -drift layer 120 of the MISFET 1100. That is to say, the source electrode 145 makes ohmic contact with the p-body region 130 via the p-body contact region 132.
  • the forward current produced by the pn junction of the body diode 180 flows between the source electrode 145 and the drain electrode 170. That is to say, if positive and negative voltages are respectively applied to the drain electrode 170 and the source electrode 145, the vertical MISFET 1100 operates as a switch to be controlled with the potential of the gate electrode 165. On the other hand, if negative and positive voltages are respectively applied to the drain electrode 170 and the source electrode 145, then the vertical MISFET 1100 functions as a diode. And when a forward current of a diode flows, a voltage that is equal to or higher than the built-in voltage (of approximately 1 V) of the Si semiconductor is generated.
  • inverter which outputs AC current based on a DC voltage
  • inductance component i.e., an inductive load
  • the voltage applied may be opposite to what is applied during the switching operation and the forward current of the body diode may sometimes flow.
  • a pseudo-Schottky diode which performs a diode operation using the vertical MISFET structure shown in FIG. 7(c) , has been invented (see Patent Document No. 1).
  • the operation of that element may be the same as the diode operation in a situation where negative and positive voltages are respectively applied to the drain electrode 170 and the source electrode 145.
  • the element is designed so that current flows mostly through the channel layer 150, not the body diode 180.
  • That element can be designed so that the current that flows through the channel layer 150 in the reverse direction to the current that flows during the transistor operation can start to flow even if the voltage is equal to or smaller than the built-in voltage (of about 1 V) of the Si semiconductor when negative and positive voltages are respectively applied to the drain electrode 170 and the source electrode 145 and that current never passes through the body diode.
  • the design of the channel layer is linked to the design of the MOS interface and needs to be carried out based on a complicated principle and know-how that has been obtained from a huge amount of actually measured data.
  • a channel layer with a thickness of 0.1 ⁇ m or more, n-type conductivity, and a concentration of 2 ⁇ 10 17 cm -3 or less has been used.
  • Patent Document No. 2 an MOS diode that uses Si is disclosed in Patent Document No. 2 and an MOS transistor that uses SiC is disclosed in Patent Document No. 3.
  • US 2008/121993 A1 relates to a power switching semiconductor device including rectifying junction-shunts.
  • US 5 929 690 A relates to a three-terminal power MOSFET switch for use as a synchronous rectifier or voltage clamp.
  • WO 2008/149922 A1 relates to a semiconductor device having an epitaxial layer, a trench and impurities region, wherein the region between the trench and the impurities region serves as a channel.
  • a power converter such as an inverter is formed using, as a switching element, a Si semiconductor element (power device) that may be a MISFET or an IGBT for use in applications that require a high breakdown voltage and a large amount of current and if that converter provides output for an L load such as the winding of a motor
  • a diode needs to be added in parallel with the switching element. This is because the switching circuit needs to make current flow even when the applied voltage has an opposite polarity to what is applied during its switching operation.
  • a Schottky diode ordinarily has a low breakdown voltage
  • a pn junction diode should be used as the diode with a breakdown voltage of 600 V or more.
  • the pseudo-Schottky diode may be used instead of the conventional pn junction diode. Then, no minority carriers will be injected and the recovery problem described above can be overcome. However, if the amount of current is as large as 10 A or more, for example, current will flow through a parasitic body diode even in the pseudo-Schottky diode. In that case, minority carriers are injected from the pn junction of the body diode into the n - -drift layer. The recovery time will increase due to the presence of those minority carriers with a long life, and a large amount of recovery current will be generated, which will in turn cause a significant increase in loss. That is a problem. On top of that, the pseudo-Schottky diode is also too expensive to be used extensively on an industrial basis.
  • the MISFET and the pseudo-Schottky diode could be integrated together.
  • a micro element operating as a MISFET and a micro element operating as a pseudo-Schottky diode can be simply arranged in parallel with each other. That is why it is difficult to reduce the size of such a structure, which is also a problem.
  • the overall area of such a structure which is the sum of the area of the MISFET functioning as a switching element and that of the pseudo-Schottky diode functioning as a diode, cannot be reduced so much.
  • Patent Document No. 3 A MISFET and a pseudo-Schottky diode implemented as silicon carbide semiconductor elements have already been reported (see Patent Document No. 3, for example).
  • Patent Document No. 3 when the structure of the element is designed, a tradeoff is inevitable between the MISFET operation and the pseudo-Schottky diode operation. That is to say, as already described with respect to the Si semiconductor, Patent Document No. 3 also states that it is impossible for a single structure to carry out the MISFET operation and the pseudo-Schottky diode operation while maintaining performance that is high enough to apply it on an industrial basis.
  • Patent Document No. 3 As for the pseudo-Schottky diode that performs a diode operation using the vertical MISFET structure described above, a Si element and a SiC element have already been disclosed in Patent Documents Nos. 2 and No. 3, respectively. As disclosed in Paragraph [0097] of Patent Document No. 3, for example, these diodes can be certainly designed to have a forward current electrical characteristic (i.e., a source-drain voltage Vf0 at which current starts to flow in the positive direction during the diode operation). That is to say, the diode current can be made to flow at a source-drain voltage Vf0 that is smaller than the built-in potential of a pn diode.
  • a forward current electrical characteristic i.e., a source-drain voltage Vf0 at which current starts to flow in the positive direction during the diode operation. That is to say, the diode current can be made to flow at a source-drain voltage Vf0 that is smaller than the built-in potential of
  • the pseudo-Schottky diode that performs a diode operation using such a vertical MISFET structure can also function as a MISFET as originally intended by designing a combined threshold voltage regulating/SIR channel layer and by applying a voltage between the source and gate.
  • the channel layer should have its concentration controlled within the range of 1 ⁇ 10 15 to 5 ⁇ 10 17 cm -3 and have its thickness controlled within the range of 0.05 ⁇ m to 1 ⁇ m (see Paragraphs [0101] of Patent Document No. 3).
  • Patent Document No. 3 does say that "a tradeoff should be made between the MISFET control function and the reverse conduction SIR function".
  • a film that has a thickness of 0.05 ⁇ m or more and that is doped with an n-type dopant with a concentration of 5 x 10 17 cm -3 or less is used as the channel layer.
  • the element is formed by extending either the structure of the Si semiconductor MISFET or that of the pseudo-Schottky diode.
  • a semiconductor element according to the present invention is defined in claim 1.
  • supposing the dopant concentration of the body region is identified by Nb
  • the dopant concentration of the channel layer is identified by Nc
  • the built-in potential of the pn junction is identified by Pbi
  • elementary charge is q, (1+( ⁇ s/Ci) ⁇ (Di/Ds)) > 2/(Pbi-(0.5q/ ⁇ s) ⁇ (Nb ⁇ Db (Db+2Dc)-Nc ⁇ Dc2))>2 is satisfied.
  • the wide bandgap semiconductor is made of silicon carbide, and supposing the dopant concentrations of the body region and the channel layer are identified by Nb and Nc, respectively, Vf0 ⁇ 0.5 volts, Ds ⁇ (2/3) ⁇ Di, Nb>1 ⁇ 10 18 cm -3 , and Nc>1 ⁇ 10 18 cm -3 are satisfied.
  • supposing the dopant concentration of the body region is identified by Nb
  • the dopant concentration of the channel layer is identified by Nc
  • the built-in potential of the PN junction is identified by Pbi
  • elementary charge is q, (1 + ( ⁇ s/ ⁇ i) ⁇ (Di/Ds)) > 2/(Pbi-(0.5q/Cs) ⁇ (Nb ⁇ Db(Db+2Dc)-Nc ⁇ Dc 2 )) >4 is satisfied.
  • Ds is greater than 14 nm.
  • At least one of Nb and Nc is equal to or smaller than 1.4 ⁇ 10 19 cm -3 .
  • Ds is smaller than 50 nm.
  • the present invention provides a vertical MISFET that operates with good stability with almost no diode current allowed to flow through a body diode, which is defined by a pn junction.
  • the semiconductor element of this embodiment is a silicon carbide semiconductor element (power semiconductor device) and includes a metal-insulator-semiconductor field effect transistor (MISFET) 1000, which is typically a MOSFET.
  • MISFET metal-insulator-semiconductor field effect transistor
  • the silicon carbide semiconductor portion of the MISFET 1000 includes: a body region 130 of a first conductivity type; a source region 140 of a second conductivity type, which contacts with at least a portion of the body region 130; a drift region 120 of the second conductivity type, which is isolated from the source region 140 via that portion of the body region 130; and a channel layer 150 of the second conductivity type, which contacts with the surface of that portion of the body region 130 that is located between the source region 140 and the drift region 120.
  • the MISFET 1000 further includes an insulating film 160 that contacts with the surface of the channel layer 150, a gate electrode 165 that faces the channel layer 150 with the insulating film 160 interposed between them; and a source electrode 145 that contacts with the source region 140.
  • the silicon carbide semiconductor portion including the drift region 120 and other regions and layers is supported by a silicon carbide semiconductor substrate 110 of the second conductivity type, and a drain electrode 170 is arranged on the back surface of the substrate 110.
  • the drain electrode 170 is electrically connected to the drift region 120.
  • the potential of the drain electrode 170 with respect to the potential of the source electrode 145 is identified by Vds.
  • the potential of the gate electrode 165 with respect to the potential of the source electrode 145 is identified by Vgs.
  • the gate threshold voltage of the MISFET 1000 is identified by Vth.
  • the direction of current flowing from the drain electrode 170 toward the source electrode 145 is defined to be a "forward direction”.
  • the direction of current flowing from the source electrode 145 toward the drain electrode 170 is defined to be a "reverse direction".
  • the MISFET 1000 makes the drain electrode 170 and the source electrode 145 electrically conductive with each other via the channel layer 150.
  • the MISFET 1000 functions as a diode that makes no current flow in the "forward direction” but makes current flow in the "reverse direction” from the source electrode 145 toward the drain electrode 170 via the channel layer 150 when Vds ⁇ -Vf0 volts.
  • the diode makes current flow in the "reverse direction”
  • "forward current” flows through the diode itself.
  • a diode that makes current flow from the source electrode 145 toward the drain electrode 170 via the channel layer 150 when the transistor is in OFF state will be referred to herein as a "channel diode".
  • a pseudo-Schottky diode if the amount of current is small, then no current will flow through the pn junction body diode in the "channel diode" of the present invention, either. However, even if the amount of current is large, no current flows through the pn junction body diode, either, in the channel diode of the present invention, which is a unique feature of the diode of the present invention that is absent from the conventional Si pseudo-Schottky diode.
  • a depletion layer with a thickness Dc which has been depleted entirely in the thickness direction, is formed in at least a part of the channel layer 150, on a plan view as viewed perpendicularly to the principal surface of the channel layer 150, due to the presence of a pn junction between that portion of the body region 130 and the channel layer 150.
  • another depletion layer that has a thickness Db as measured from a junction surface of the pn junction is formed in that portion of the body region 130.
  • the semiconductor element of this embodiment satisfies Ds ⁇ Di ⁇ ⁇ s/( ⁇ i(2/Vf0-1)).
  • the "turn-on voltage" of the diode is defined to be the magnitude of a potential at which current starts to flow from the source electrode 145 toward the drain electrode 170 while the potential of the drain electrode 170 with respect to that of the source electrode 145 is being decreased from zero volts.
  • a forward voltage of Vf0 or more is applied to the diode, forward current flows through the diode. According to the definition described above, this forward current is current that flows in the "reverse direction" for the semiconductor element.
  • a depletion layer with the thickness Dc which has been depleted entirely in the thickness direction of the channel layer 150, is formed due to the pn junction between the body region 130 and the channel layer 150.
  • another depletion layer that has the thickness Db as measured from the junction surface of the pn junction is formed in the body region 130.
  • the semiconductor element of this embodiment includes the silicon carbide semiconductor substrate 110 of the second conductivity type and the drift region 120 of silicon carbide of the second conductivity type that has been formed on the surface of the substrate 110.
  • the drift region 120 of the second conductivity type is the rest of the silicon carbide layer that has been formed on the substrate 110 other than its portion including the body region 130 of the first conductivity type. Such a portion will be referred to herein as a "second conductivity type portion".
  • the silicon carbide layer including the "drift region 120" and the "body region 130" will be sometimes referred to herein as a "drift layer" for convenience sake.
  • the silicon carbide semiconductor substrate 110 is an n + -substrate (n + -SiC substrate) and the drift region 120 is an n - -region. That is to say, according to this embodiment, the second conductivity type is n type and the first conductivity type is p type. However, these n and p types may naturally be changed with each other. It should be noted that the superscript "+” or "-” added to the conductivity type "n” represents the relative concentration of the dopant introduced. That is to say, “n + “ means that the concentration of an n-type dopant added is higher than "n", while “n - " means that the concentration of an n-type dopant added is lower than "n”.
  • a p-body region 130 of the first conductivity type In the drift layer, defined is a p-body region 130 of the first conductivity type. And in the p-body region 130, defined is a source region 140 of the second conductivity type. The source region 140 is an n + type.
  • the p-body region 130 will be referred to herein as sometimes a "p-body layer” and sometimes a "p-base region”.
  • a p + -type contact region 132 is further defined in the p-body region 130.
  • a source electrode 145 is arranged on the source region 140. Specifically, the source electrode 145 covers the surface of both the n + -source region 140 and the p + -contact region 132 and is electrically in contact with both of the n + -source region 140 and the p + -contact region 132.
  • the p + -contact region 132 is also electrically in contact with the p-body region 130. If the p-body region 130 has a sufficiently high dopant concentration, then the p + -contact region 132 may be omitted and the source electrode 145 may directly contact with the p-body region 130.
  • a dopant of the second conductivity type (which is n type in this example) may be introduced by ion implantation, for example, in order to lower the resistance in the JFET region 121, and the that part may have a higher dopant concentration than the rest of the drift region 120.
  • an n-type channel layer 150 has been formed so as to be at least partially in contact with the p-body region 130 and the n + -source region 140.
  • the channel layer 150 has been grown epitaxially, for example, on the drift layer in which the p-body region 130 and the n + -source region 140 have been defined.
  • the channel layer 150 may be a region that has been defined by implanting an n-type dopant into an upper portion of the p-body region 130 as shown in FIG. 7(c) .
  • a gate insulating film 160 has been deposited on the channel layer 150.
  • a gate electrode 165 has been formed on the gate insulating film 160.
  • a drain electrode 170 has been formed on the back surface of the substrate 110.
  • the present inventors carefully analyzed the operations of the FET and the pseudo-Schottky diode in the structure surrounding the channel of the MISFET, thereby discovering the following principle of operation. And based on that discovery, the present inventors invented a novel semiconductor element that can operate as both a MISFET and a diode alike. Specifically, the present inventors derived a general formula (which is Equation (7) to be described later) representing the minimum voltage Vf0 between the drain electrode and the source electrode at which forward current starts to flow through the diode.
  • the present inventors further derived a general formula (which is Equation (8) to be described later) representing the relation between the voltage Vth applied to the gate electrode that turns the transistor ON and Vf0, which is an important factor that determines the MISFET operation.
  • a general formula which is Equation (8) to be described later
  • the present inventors discovered a structure that can perform both the MISFET operation and the diode operation without making a tradeoff between them.
  • a depletion layer with a thickness Dc which has been depleted entirely in the thickness direction, is formed in at least a part of the channel layer 150 due to the presence of a pn junction between the body region 130 and the channel layer 150 (see FIG. 2 ).
  • the depletion layer surrounding the channel layer 150 of the MISFET needs to satisfy the following Inequality (2) : Ds ⁇ Emax 2 > Pbi where Emax is the maximum electric field at or under which no leakage current flows through the pn junction without producing avalanche current in the semiconductor and Pbi is the built-in potential of the pn junction of the semiconductor element
  • the channel layer had a thickness of less than 70 nm and a dopant concentration of greater than approximately 2 ⁇ 10 17 cm -3 , it would be difficult to establish the state where no current flows through the channel layer when the potential Vgs of the gate electrode 165 with respect to that of the source electrode 145 is 0 volts.
  • the semiconductor element could operate with good stability.
  • the dopant concentration Nc of the channel layer is supposed to be uniform in the thickness direction and the dopant concentration Nb of the body region is supposed to be much higher than the dopant concentration Nc of the channel layer. That is why it can be said that the depletion layer would be thin at the body region's end and the thickness Ds of the depletion layer would be approximately equal to the thickness Dc of the channel layer.
  • a SiC-based semiconductor element with such a thin channel layer can also operate with no problem. It can also be seen that even if the dopant concentration of the channel layer is higher than approximately 2 ⁇ 10 17 cm -3 , which they believe may not be exceeded in a Si-based semiconductor element, a SiC-based semiconductor element with a channel layer having such a high dopant concentration can also operate with no problem.
  • Ds Dc+Db. That is why supposing Dc and Db are substantially equal to each other, even if Nc is twice as high as the value described above, the SiC semiconductor element can also operate with good stability. That is to say, it can be seen from Inequality (5') that even if Nc, Nb ⁇ 1.4 ⁇ 10 19 cm -3 , stabilized function can also be achieved. In other words, if at least one of Nc and Nb is less than 1.4 ⁇ 10 19 cm -3 , then the SiC-based element can function as a semiconductor element with good stability.
  • the potential in the depletion layer at the pn junction is supposed to have dropped all the way down to the level of the built-in potential at the pn junction of the semiconductor (which corresponds to the bandgap). Since the semiconductor element of the present invention is not a Normally ON type, when no voltage is applied between the source electrode and the gate electrode, the potential that has dropped at the pn junction between the channel layer and the body region according to the present invention is less than the built-in potential at the pn junction of the SiC semiconductor (which corresponds to the bandgap).
  • the potential drop is preferably 2 V or more in order to prevent current from flowing through the body diode even when a large amount of current is made to flow through the channel diode.
  • the lower limit of Ds becomes two-thirds of 20 nm. That is why the following Inequality is satisfied: Ds SiC > 14 nm
  • Vth Vfo ⁇ 1 + ⁇ s ⁇ i ⁇ Di Ds
  • ⁇ i and Di respectively represent the dielectric constant and thickness of the insulating film 160 .
  • Ds used in this case is the thickness of the depletion layer of the semiconductor element to which the voltage Vth is applied, and different from Dc + Db of Equation (7), strictly speaking.
  • a condition for operating an MISFET safely is to set Vth to be equal to or greater than a certain positive value.
  • a MISFET or any other switching element for use in a power electronic circuit should have a gate threshold voltage Vth that is normally greater than 2 V. This is because an element, of which the threshold voltage Vth is equal to or smaller than 2 V, would switch current erroneously due to the noise involved with the switching operation, thus making it impossible to guarantee that such an element should operate safely.
  • the minimum voltage Vf0 between the drain and source electrodes, at which forward current starts to flow through the diode should be set to be equal to or smaller than a certain value. Particularly, even if a huge amount of current that should flow when the semiconductor element functions as a switching element flowed in the reverse direction when the semiconductor element functions as a diode but if the turn-on voltage Vf0 of the diode is set to be smaller than 1 V, a structure in which almost no current flows through the parasitic body diode is realized.
  • the switching current (i.e., current in the positive direction) of the MISFET is ordinarily limited so that the forward voltage Vf in the positive direction becomes smaller than 2 V in view of the heat that could be generated from the semiconductor element and other problems.
  • the voltage Vf is defined to be the product of the switching current and the ON-state resistance of the MISFET (which relates to a voltage drop).
  • the semiconductor element operates as an inverter, this current becomes diode current to make the inverter electrically conductive. That is why the forward voltage (i.e., Vf in the reverse direction) of the diode current is obtained by adding Vf0 to Vf in the positive direction (which is less than 2 V). If Vf0 is less than 1 V, this value is limited to less than 3 V.
  • That diode forward voltage of less than 3 V is approximately equal to or smaller than the built-in potential of about 3 V at the pn junction of silicon carbide. Consequently, if Vf0 is less than 1 V, almost no current will flow through the parasitic body diode.
  • Ds should be set so as to satisfy the following Inequality (9") Ds ⁇ ⁇ s ⁇ i ⁇ Di 2 Vfo - 1
  • the Di and Vf0 settings may change depending on in what situation the semiconductor element of the present invention is used. That is why in the semiconductor element of the present invention, it is essential to set Ds based on given Di and Vf0 so as to satisfy this Inequality (9").
  • Inequality (9") can be modified into the following Inequality (10): Ds ⁇ ⁇ s ⁇ i ⁇ Di
  • Di As an ordinary silicon carbide semiconductor element is driven with a gate voltage of 20 V, Di is usually set to be 70 nm and it is preferred that Ds satisfy the following Inequality (12): Ds ⁇ about 140 nm
  • Equation (9) is generalized on the condition that Vth > 2 V and Vf0 ⁇ 1 V are satisfied, the following Inequality (13) is obtained: 1 + ⁇ s ⁇ i ⁇ Di Ds > 2 Pbi - q 2 ⁇ ⁇ s ⁇ Nb ⁇ Db ⁇ Db + 2 ⁇ Dc - Nc ⁇ Dc 2 > 2
  • Di is set to be 70 nm, then the following Inequality (15) is obtained with respect to Ds: Ds ⁇ 50 ⁇ nm
  • Equation (9) is generalized on the condition that Vth > 2 V and Vf0 ⁇ 0.5 V are satisfied, the following Inequality (19) is obtained: 1 + ⁇ s ⁇ i ⁇ Di Ds > 2 Pbi - q 2 ⁇ ⁇ s ⁇ Nb ⁇ Db ⁇ Db + 2 ⁇ Dc - Nc ⁇ Dc 2 > 4
  • the digit of Nc is changed in five stages from 10 16 cm -3 through 10 20 CM -3 .
  • the ordinate represents Vf0 and the abscissa represents Vth.
  • Dc is 10 nm, 50 nm, 100 nm, 500 nm or 1000 nm.
  • Nb is 10 19 cm -3 , 10 18 cm -3 and 10 17 cm -3 , respectively.
  • Vth and Vf0 were calculated by the newly derived Equations (7) and (8), respectively.
  • the ordinate represents Dc and the abscissa represents Nc.
  • each of the numerical values on the axis of abscissas indicates the exponent of 10. Specifically, "16" means 1 ⁇ 10 16 (cm -3 ) and "16.5" means 1 ⁇ 10 16.5 (cm -3 ). The same can be said about the numerical value on the axis of abscissas shown in FIGS. 4(b) and 4(c) to be described below.
  • the thickness Dc of the channel layer is normally set to be 50 nm or more.
  • the ordinate represents Vth and the abscissa represents Nc.
  • FIG. 4(c) is a graph showing respective portions of FIGS. 4(a) and 4(b) in combination.
  • the ordinate on the left-hand side represents Dc
  • the ordinate on the right-hand side represents Vth
  • the abscissa represents Nc.
  • FIGS. 5(a), 5(b) and 5(c) are graphs corresponding to FIGS. 4(a), 4(b) and 4(c) , respectively.
  • the ordinate represents the thickness Dc of the channel layer and the abscissa represents the dopant concentration Nc of the channel layer.
  • each of the numerical values on the axis of abscissas indicates the exponent of 10. For example, "18" means 1 ⁇ 10 18 (cm -3 ).
  • the results shown in FIG. 6 revealed that if Dc ⁇ 50 nm and Nc>1 ⁇ 10 18 cm -3 were satisfied, a range where Vth>2 V could be created.
  • the thickness and the dopant concentration of the channel layer should be set to fall within appropriate ranges.
  • the thickness Dc of the channel layer is preferably smaller than 50 nm, and more preferably equal to or smaller than 40 nm.
  • Vf0 is set to fall within the range of 0.5 V to 1.0 V with Vth>2 V satisfied.
  • Table 1 shows examples of conditions for setting Vf within the range of 0.6 V to 0.9 V: Table 1 Vf0 (volts) Lower limit of Vth/Vfo Lower limit of Nb, Nc (cm -3 ) 0.9 2.2 1 ⁇ 10 17 0.8 2.5 2 ⁇ 10 17 0.7 2.9 3 ⁇ 10 17 0.6 3.3 Nb > 1 ⁇ 10 18 Nc > 5 ⁇ 10 17
  • the lower limit of Vth/Vfo in Table 1 corresponds to the rightmost numerical value in Inequalities (13) and (16).
  • the embodiment of the present invention described above is a semiconductor element including a MISFET with a planar structure.
  • the semiconductor element of the present invention may also be a semiconductor element including a MISFET with a trench structure.
  • silicon carbide SiC
  • the present invention can also be carried out in the same way using GaN or any other wide bandgap semiconductor as when silicon carbide is used.
  • the MISFET can have its threshold value Vth increased sufficiently when operated as such (i.e., as a MISFET) and can also have the absolute value of its turn-on voltage decreased sufficiently when operated as a diode.
  • the present invention provides a semiconductor element that can drive a power electronic circuit such as an inverter with good stability without increasing the number of components.

Claims (7)

  1. Halbleiterbauelement mit einem Metall-Isolator-Halbleiter-Feldeffekttransistor, wobei der Metall-Isolator-Halbleiter-Feldeffekttransistor umfasst:
    einen Halbleiter mit einer breiten Bandlücke, der umfasst:
    einen Body-Bereich (130) eines ersten Leitfähigkeitstyps,
    einen Source-Bereich (140) eines zweiten Leitfähigkeitstyps, wobei der Source-Bereich wenigstens einen Teil des Body-Bereichs kontaktiert,
    einen Drift-Bereich (120) des zweiten Leitfähigkeitstyps, wobei der Drift-Bereich von dem Source-Bereich über diesen Teil des Body-Bereichs isoliert ist, und
    eine Kanalschicht (150) des zweiten Leitfähigkeitstyps, wobei die Kanalschicht die Fläche dieses Teils des Body-Bereichs kontaktiert, der zwischen dem Source-Bereich und dem Drift-Bereich liegt,
    einen Isolierfilm (160), der die Fläche der Kanalschicht kontaktiert,
    eine Gate-Elektrode (165), die der Kanalschicht mit dazwischen dem Isolierfilm zugewandt ist,
    eine Source-Elektrode (145) die den Source-Bereich kontaktiert, und
    eine Drain-Elektrode (170), die elektrisch mit dem Drift-Bereich verbunden ist, wobei
    wenn angenommen wird, dass
    das Potential der Drain-Elektrode (170) in Bezug auf das Potential der Source-Elektrode (145) durch Vds wiedergegeben wird,
    das Potential der Gate-Elektrode (165) in Bezug auf das Potential der Source-Elektrode (145) durch Vgs wiedergegeben wird,
    die Gate-Schwellspannung des Metall-Isolator-Halbleiter-Feldeffekttransistors durch Vth wiedergegeben wird,
    die Richtung des von der Drain-Elektrode (170) zu der Source-Elektrode (145) fließenden Stroms als eine Vorwärtsrichtung definiert ist, und
    die Richtung des von der Source-Elektrode (145) zu der Drain-Elektrode (170) fließenden Stroms als eine Rückwärtsrichtung definiert ist,
    wenn Vgs ≥ Vth,
    dann macht der Metall-Isolator-Halbleiter-Feldeffekttransistor die Drain-Elektrode (170) und die Source-Elektrode (145) elektrisch leitend miteinander über die Kanalschicht (150), und
    wenn 0 Volt ≤ Vgs < Vth,
    dann funktioniert der Metall-Isolator-Halbleiter-Feldeffekttransistor als eine Diode, die keinen Stromfluss in der Vorwärtsrichtung gestattet, aber einen Stromfluss in der Rückwärtsrichtung von der Source-Elektrode (145) zu der Drain-Elektrode (170) über die Kanalschicht (150) gestattet, wenn Vds < 0 Volt, und
    wenn das Potential Vgs der Gate-Elektrode in Bezug auf das Potential der Source-Elektrode (145) 0 Volt ist,
    dann wird eine Verarmungsschicht mit einer Dicke Dc, die vollständig in der Dickenrichtung verarmt wurde, in wenigstens einem Teil der Kanalschicht (150) aufgrund des Vorhandenseins eines pn-Übergangs zwischen dem Teil des Body-Bereichs (130) und der Kanalschicht (150) gebildet, und wird eine weitere Verarmungsschicht mit einer Dicke Db, gemessen von der Übergangsfläche des pn-Übergangs in dem Teil des Body-Bereichs (130) gebildet, und wobei
    wenn angenommen wird, dass
    die dielektrische Konstante des Halbleiters mit einer breiten Bandlücke durch εs wiedergegeben wird,
    die dielektrische Konstante und die Dicke des Isolationsfilms jeweils durch εi und Di wiedergegeben werden,
    die Summe aus Dc und Db durch Ds wiedergegeben wird, und
    der absolute Wert einer Einschaltspannung der Diode durch Vf0 wiedergegeben wird, dann wird Ds < Di • εs/(εi (2/Vf0-1)) erfüllt,
    wobei die Einschaltspannung der Diode als die Größe eines Potentials definiert ist, bei dem der Strom von der Source-Elektrode (145) zu der Drain-Elektrode (170) zu fließen beginnt, während das Potential der Drain-Elektrode (170) in Bezug auf dasjenige der Source-Elektrode (145) von null Volt vermindert wird,
    wobei der Halbleiter mit der breiten Bandlücke aus Siliziumcarbid ausgebildet ist, und wobei
    wenn angenommen wird, dass die Dotierungskonzentrationen des Body-Bereichs (130) und der Kanalschicht (150) jeweils durch Nb und Nc wiedergegeben werden,
    Vf0 < 1 Volt,
    Ds < 2Di,
    Nb > 1 × 1017 cm-3, und
    Nc > 1 × 1017 cm-3 erfüllt werden.
  2. Halbleiterbauelement nach Anspruch 1, wobei:
    wenn angenommen wird, dass
    die Dotierungskonzentration des Body-Bereichs durch Nb wiedergegeben wird,
    die Dotierungskonzentration der Kanalschicht (150) durch Nc wiedergegeben wird,
    das Kontaktpotential des pn-Übergangs durch Pbi wiedergegeben wird, und
    die Elementarladung q ist,
    (1+(ss/ei) • (Di/Ds))>2/(Pbi-(0,5q/εs) • (Nb • Db (Db+2Dc)-Nc • Dc2))>2 erfüllt wird.
  3. Halbleiterbauelement nach Anspruch 1, wobei der Halbleiter mit einer breiten Bandlücke aus Siliziumcarbid besteht und wobei:
    wenn angenommen wird, dass
    die Dotierungsmittelkonzentrationen des Body-Bereichs (130) und der Kanalschicht (150) jeweils durch Nb und Nc wiedergegeben werden,
    Vf0 < 0,5 Volt,
    Ds < (2/3) • Di,
    Nb > 1 × 1018 cm-3, und
    Nc > 1 × 1018 cm-3 erfüllt werden.
  4. Halbleiterbauelement nach Anspruch 3, wobei:
    wenn angenommen wird, dass
    die Dotierungsmittelkonzentration des Body-Bereichs durch Nb wiedergegeben wird,
    die Dotierungsmittelkonzentration der Kanalschicht (150) durch Nc wiedergegeben wird,
    das Kontaktpotential des PN-Übergangs durch Pbi wiedergegeben wird, und
    die Elementarladung q ist,
    (1+(Es/ei) • (Di/Ds))>2/(Pbi-(0,5q/εs) • (Nb • Db (Db+2Dc)-Nc • Dc2))>4 erfüllt wird.
  5. Halbleiterbauelement nach einem der Ansprüche 1 bis 4, wobei Ds größer als 14 nm ist.
  6. Halbleiterbauelement nach einem der Ansprüche 1 bis 5, wobei Nb und/oder Nc gleich oder kleiner als 1,4×1019 cm-3 ist.
  7. Halbleiterbauelement nach Anspruch 1, wobei Ds kleiner als 50 nm ist.
EP11833583.5A 2010-10-29 2011-10-14 Halbleiterbauelement Active EP2482315B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010243221 2010-10-29
PCT/JP2011/005769 WO2012056642A1 (ja) 2010-10-29 2011-10-14 半導体素子

Publications (3)

Publication Number Publication Date
EP2482315A1 EP2482315A1 (de) 2012-08-01
EP2482315A4 EP2482315A4 (de) 2013-08-28
EP2482315B1 true EP2482315B1 (de) 2015-08-12

Family

ID=45993390

Family Applications (1)

Application Number Title Priority Date Filing Date
EP11833583.5A Active EP2482315B1 (de) 2010-10-29 2011-10-14 Halbleiterbauelement

Country Status (5)

Country Link
US (1) US8742427B2 (de)
EP (1) EP2482315B1 (de)
JP (1) JP4965754B2 (de)
CN (1) CN102598265A (de)
WO (1) WO2012056642A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9123798B2 (en) * 2012-12-12 2015-09-01 General Electric Company Insulating gate field effect transistor device and method for providing the same
JP2015046502A (ja) * 2013-08-28 2015-03-12 住友電気工業株式会社 炭化珪素半導体装置およびその製造方法
JP6601086B2 (ja) * 2015-09-16 2019-11-06 富士電機株式会社 半導体装置及びその製造方法
DE112017003513B4 (de) * 2016-07-14 2024-03-07 Mitsubishi Electric Corporation Halbleitereinheit und Verfahren zur Herstellung derselben
JP6814965B2 (ja) * 2017-03-06 2021-01-20 パナソニックIpマネジメント株式会社 半導体エピタキシャルウェハ、半導体素子、および半導体素子の製造方法
JP7054853B2 (ja) * 2018-02-07 2022-04-15 パナソニックIpマネジメント株式会社 炭化珪素半導体素子およびその製造方法

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5510641A (en) * 1992-06-01 1996-04-23 University Of Washington Majority carrier power diode
US5506421A (en) * 1992-11-24 1996-04-09 Cree Research, Inc. Power MOSFET in silicon carbide
RU2120169C1 (ru) * 1993-09-08 1998-10-10 Сименс АГ Устройство установки переменного тока
JP3334290B2 (ja) * 1993-11-12 2002-10-15 株式会社デンソー 半導体装置
US5744994A (en) 1996-05-15 1998-04-28 Siliconix Incorporated Three-terminal power mosfet switch for use as synchronous rectifier or voltage clamp
US5818084A (en) * 1996-05-15 1998-10-06 Siliconix Incorporated Pseudo-Schottky diode
US6531738B1 (en) * 1999-08-31 2003-03-11 Matsushita Electricindustrial Co., Ltd. High voltage SOI semiconductor device
US6956238B2 (en) * 2000-10-03 2005-10-18 Cree, Inc. Silicon carbide power metal-oxide semiconductor field effect transistors having a shorting channel and methods of fabricating silicon carbide metal-oxide semiconductor field effect transistors having a shorting channel
WO2003028110A1 (fr) * 2001-09-14 2003-04-03 Matsushita Electric Industrial Co., Ltd. Semi-conducteur
US6940110B2 (en) * 2002-11-29 2005-09-06 Matsushita Electric Industrial Co., Ltd. SiC-MISFET and method for fabricating the same
US6995473B2 (en) * 2002-12-19 2006-02-07 Matsushita Electric Industrial Co., Ltd. Stacked semiconductor transistors
CN1532943B (zh) * 2003-03-18 2011-11-23 松下电器产业株式会社 碳化硅半导体器件及其制造方法
US7473929B2 (en) * 2003-07-02 2009-01-06 Panasonic Corporation Semiconductor device and method for fabricating the same
JP4948784B2 (ja) * 2005-05-19 2012-06-06 三菱電機株式会社 半導体装置及びその製造方法
CN101233615B (zh) * 2005-07-25 2012-01-04 松下电器产业株式会社 半导体元件和电气设备
EP1909326A4 (de) * 2005-07-26 2009-05-06 Panasonic Corp Halbleiterelement und elektrische einrichtung
JP5036233B2 (ja) * 2006-07-06 2012-09-26 シャープ株式会社 半導体スイッチング素子および半導体回路装置
US7595241B2 (en) * 2006-08-23 2009-09-29 General Electric Company Method for fabricating silicon carbide vertical MOSFET devices
US7598567B2 (en) * 2006-11-03 2009-10-06 Cree, Inc. Power switching semiconductor devices including rectifying junction-shunts
WO2008149922A1 (ja) * 2007-06-06 2008-12-11 Rohm Co., Ltd. 半導体装置
JP2010027833A (ja) 2008-07-18 2010-02-04 Mitsubishi Electric Corp 炭化珪素半導体装置およびその製造方法
US8022474B2 (en) * 2008-09-30 2011-09-20 Infineon Technologies Austria Ag Semiconductor device
US20100171155A1 (en) * 2009-01-08 2010-07-08 Samar Kanti Saha Body-biased Silicon-On-Insulator Junction Field-Effect Transistor Having A Fully Depleted Body and Fabrication Method Therefor
CN102414818B (zh) * 2009-04-30 2013-03-20 松下电器产业株式会社 半导体元件、半导体装置及电力变换器
US8283973B2 (en) * 2009-08-19 2012-10-09 Panasonic Corporation Semiconductor element, semiconductor device, and electric power converter
US8610130B2 (en) * 2009-10-30 2013-12-17 Cree, Inc. Monolithic high voltage switching devices
WO2011089861A1 (ja) 2010-01-19 2011-07-28 パナソニック株式会社 半導体装置およびその製造方法

Also Published As

Publication number Publication date
EP2482315A4 (de) 2013-08-28
EP2482315A1 (de) 2012-08-01
JPWO2012056642A1 (ja) 2014-03-20
JP4965754B2 (ja) 2012-07-04
US8742427B2 (en) 2014-06-03
CN102598265A (zh) 2012-07-18
WO2012056642A1 (ja) 2012-05-03
US20120305944A1 (en) 2012-12-06

Similar Documents

Publication Publication Date Title
EP2610914B1 (de) Halbleiterelement
US8933463B2 (en) Semiconductor element, semiconductor device, and power converter
US8283973B2 (en) Semiconductor element, semiconductor device, and electric power converter
US7719053B2 (en) Semiconductor device having increased gate-source capacity provided by protruding electrode disposed between gate electrodes formed in a trench
US9324807B1 (en) Silicon carbide MOSFET with integrated MOS diode
CN108780816B (zh) 碳化硅装置及其制作方法
CN110176454B (zh) 多晶体管器件
US20180019309A1 (en) Semiconductor device based on wideband gap semiconductor materials
EP2482315B1 (de) Halbleiterbauelement
US11444155B2 (en) Silicon carbide semiconductor device
EP1033756A2 (de) Halbleiteranordnung mit einer leichtdotierten Schicht und Leistungswandler mit derselben
US9735263B2 (en) Transistor and switching system comprising silicon carbide and oxides of varying thicknesses, and method for providing the same
US10355132B2 (en) Power MOSFETs with superior high frequency figure-of-merit
EP4008025B1 (de) Siliziumkarbid-transistoranordnung
CN113410284A (zh) 碳化硅半导体结构和碳化硅半导体器件
US20240030315A1 (en) Vertical oriented semiconductor device comprising well regions having a lateral doping gradient with monotonic decreasing doping concentration, as well as a corresponding method of manufacturing such a vertical oriented semiconductor device
US20230352520A1 (en) Wide band gap semiconductor device
US20240047515A1 (en) Vertical oriented semiconductor device in which well regions are created in a semiconductor body, and a method of manufacturing the same
CN112768521B (zh) 横向双扩散金属氧化物半导体器件
CN117613098A (zh) 垂直沟槽型电容耦合栅控结型场效应晶体管及其制备方法

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20120426

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

REG Reference to a national code

Ref country code: DE

Ref legal event code: R079

Ref document number: 602011018812

Country of ref document: DE

Free format text: PREVIOUS MAIN CLASS: H01L0027040000

Ipc: H01L0029780000

A4 Supplementary search report drawn up and despatched

Effective date: 20130729

RIC1 Information provided on ipc code assigned before grant

Ipc: H01L 29/78 20060101AFI20130723BHEP

Ipc: H01L 29/12 20060101ALI20130723BHEP

Ipc: H01L 29/06 20060101ALI20130723BHEP

DAX Request for extension of the european patent (deleted)
17Q First examination report despatched

Effective date: 20140715

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LT

INTG Intention to grant announced

Effective date: 20150303

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: AT

Ref legal event code: REF

Ref document number: 742814

Country of ref document: AT

Kind code of ref document: T

Effective date: 20150815

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602011018812

Country of ref document: DE

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG4D

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 742814

Country of ref document: AT

Kind code of ref document: T

Effective date: 20150812

REG Reference to a national code

Ref country code: NL

Ref legal event code: MP

Effective date: 20150812

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150812

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20151112

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150812

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20151113

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150812

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150812

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150812

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150812

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20151212

Ref country code: RS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150812

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150812

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150812

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20151214

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150812

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150812

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150812

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150812

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150812

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150812

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602011018812

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20151014

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150812

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150812

26N No opposition filed

Effective date: 20160513

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20151112

REG Reference to a national code

Ref country code: IE

Ref legal event code: MM4A

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20151031

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20151031

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20160630

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150812

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20151102

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20151112

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20151014

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150812

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150812

Ref country code: SM

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150812

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO

Effective date: 20111014

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150812

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150812

Ref country code: MT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150812

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150812

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150812

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20231020

Year of fee payment: 13