EP2360661B1 - Circuit substrate, display panel, and display device - Google Patents

Circuit substrate, display panel, and display device Download PDF

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Publication number
EP2360661B1
EP2360661B1 EP09827400.4A EP09827400A EP2360661B1 EP 2360661 B1 EP2360661 B1 EP 2360661B1 EP 09827400 A EP09827400 A EP 09827400A EP 2360661 B1 EP2360661 B1 EP 2360661B1
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EP
European Patent Office
Prior art keywords
wiring
external connection
wirings
circuit substrate
connection terminal
Prior art date
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EP09827400.4A
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German (de)
English (en)
French (fr)
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EP2360661A4 (en
EP2360661A1 (en
Inventor
Hiroyuki Moriwaki
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Sharp Corp
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Sharp Corp
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Publication of EP2360661A4 publication Critical patent/EP2360661A4/en
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/361—Assembling flexible printed circuits with other printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09409—Multiple rows of pads, lands, terminals or dummy patterns; Multiple rows of mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09436—Pads or lands on permanent coating which covers the other conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10128—Display
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H05K3/323—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads

Definitions

  • the present invention relates to a circuit substrate, a display panel and a display device. More specifically, the present invention relates to a circuit substrate suitable for narrowing the frame of a display device, and to a display panel and a display device provided with such a circuit substrate.
  • LCDs liquid crystal displays
  • PDPs plasma displays
  • inorganic electroluminescent (inorganic EL) displays organic electroluminescent (organic EL) displays
  • Electronic portable devices such as mobile phones, PDAs and the like, to which such flat panel displays are fitted, are required to be ever smaller and lighter, which translates into a trend towards a smaller periphery (frame region) of the display region, i.e. into narrower frames.
  • peripheral circuits required for driving circuits have been mounted at the frame region of a substrate that makes up the display panel.
  • display devices in which a full monolithic-type circuit substrate, where peripheral circuits are assembled into the frame region of the substrate, are set have been developed in recent years with a view to, for instance, cutting costs and achieving thinner profiles.
  • Examples of conventional display devices include a display device provided with: common wirings that feed scanning line driving circuits that drive scanning lines, and common wirings that feed signal line driving circuits that drive signal lines; interlayer dielectrics that isolate respective common wirings; and a plurality of external connection terminals positioned on a plurality of respective contact holes that are provided in the interlayer dielectrics, in such a manner that part of each common wiring is exposed (for instance, Patent document 1).
  • a display device an anisotropic conductive film is disposed on the external connection terminals, such that connection to the exterior is elicited by way of the anisotropic conductive film.
  • Patent Document 1 Japanese Kokai Publication No. H10-282522
  • the external connection terminals and the common wirings are connected by way of contact holes, and an external member such as a flexible printed circuit (FPC) board is bonded to the external connection terminals by way of the anisotropic conductive film that comprises conductive particles.
  • FPC flexible printed circuit
  • the conductive film that makes up the external connection terminals may become crushed by the conductive particles if the latter overlap the contact holes. This has been found to give rise to connection faults.
  • configurations where common wirings and external connection terminals overlap make for a smaller frame area, as compared with configurations where the external connection terminals and the common wirings are disposed without overlapping each other.
  • US 2005/072597 A1 discloses a bonding pad structure of a display device.
  • a first conductive layer is formed overlying a substrate, a protection layer is formed overlying the substrate and the first conductive layer, and a second conductive layer is formed overlying the protection layer.
  • An opening structure penetrates the second conductive layer and the protection layer to expose the first conductive layer.
  • a third conductive layer is formed overlying the second conductive layer to contact the sidewall and bottom of the opening structure.
  • the third conductive layer is electrically connected to the second conductive layer to provide a first electrical-connection path
  • the third conductive layer is electrically connected to the first conductive layer to provide a second electrical-connection path.
  • JP 2000 221540 A discloses that a dummy contact hole is disposed between adjacent terminals, thereby, the conductive particles of ACF are made to remain on the organic film to prevent the absence of the contact between the lower layer metal of the terminals and the connecting line of the TAB.
  • the contact hole for connecting the upper layer transparent electrode of the terminals and the lower layer metal are composed of plural via holes, by which the conductive particles of the ACF on the upper layer transparent electrodes are sufficiently made to remain and the connecting with the connecting wires of the TAB is improved.
  • JP 2002 258768 A discloses that with respect to an electrooptical device where wiring is formed in an edge side area along the edge side of a substrate holding an electrooptical material and packaged parts like an IC chip are mounted in this edge side area, a protection layer covering the wiring and a connection terminal having a first part brought into contact with the wiring through an aperture part provided in the protection layer and a second part placed on the surface of the protection layer is provided. Conductive particles are interposed between the second part of the connection terminal and a terminal of the packaged parts to electrically connect the connection terminal and the terminal of packaged parts.
  • JP 10 282522 A discloses that an external connecting terminal group constituted of an external connecting terminal supplying a driving circuit with power source voltage and the external connecting terminal supplying the driving circuit with the power source voltage is arranged in an area at the outside of the driving circuit.
  • the external connecting terminal of the center part of the external connecting terminal is connected to the driving circuit, and on the other hand, the external connecting terminals at both ends are connected to the driving circuit opposed with the display area between.
  • a through-hole where parts of plural common wirings are respectively exposed is provided on the insulating film between the layers coated with the plural common wirings connected to a scanning line driving circuit or the like, and the common wiring and the external connecting terminal are respectively connected through the through-hole, so that the common wiring and the external connecting terminal are three-dimensionally arranged and the area of an insulated substrate is reduced.
  • the inventors conducted various studies on configurations of circuit substrates wherein an external connection terminal is connected to wiring by way of at least one contact hole, and wherein the circuit substrate is provided with an anisotropic conductive film that comprises conductive particles, on the external connection terminal, and focused on the relationship between contact holes and the anisotropic conductive film that is disposed on the external connection terminal.
  • the inventors found that the conductive particles in the anisotropic conductive film may give rise to disconnection of the external connection terminal and to connection faults, among other problems, upon connection of an external member or the like to the external connection terminal.
  • connection faults between wiring and an external connection terminal can be prevented, without overlapping of the conductive particles with the entire region of the contact holes, by setting the length from one end to the other end, in a plan view, of a region, at which one or more contact holes connected to a specific external connection terminal is formed, to be greater than the diameter of each of the conductive particles.
  • the inventors arrived at the present invention upon envisaging that the above finding could allow curbing drops in manufacturing yield due to connection faults or the like.
  • the circuit substrate of the present invention is a circuit substrate in which wiring, an insulating film and an external connection terminal are sequentially disposed on a substrate.
  • the circuit substrate of the present invention is a circuit substrate wherein wiring and an external connection terminal are disposed on a substrate, and an insulating film is disposed therebetween.
  • the wiring is ordinarily a member that affords current paths in the circuit substrate.
  • Such wiring is not particularly limited, and in the case of wiring provided in a display device may include, for instance, power supply wiring for supply of power from outside, or signal wiring for transmitting a signal from outside or for transmitting a signal from the circuit substrate towards the exterior.
  • signal wiring is connected to, for instance, a driver circuit in the circuit substrate. If the driver circuit or the like is provided externally, the signal wiring may be provided in the form of, for instance, source wiring, gate wiring and storage capacitance wiring that transmit signals to pixels in order for the latter to carry out display.
  • the external connection terminal is a terminal used for transmitting external power and/or signals from the exterior (for instance, from an external member such as an FPC) to the wiring, or a terminal used for transmitting signals from the circuit substrate to the exterior. That is, the external connection terminal has electrical conductivity.
  • the configuration of the external connection terminal is not particularly limited, and the external connection terminal may be, for instance, a single-layer film consisting of a single-layer conductive film, or a multilayer film comprising a stack of a plurality of conductive films.
  • the insulating film is a film formed of an insulating material for electrically isolating (insulating) between the wiring and the external connection terminal, at portions other than the portions at which the foregoing are connected by way of contact holes or the like.
  • Examples of the material that can be used to form the insulating film include, but not limited thereto, for instance organic insulating materials, or inorganic insulating materials such as inorganic oxides, inorganic nitrides or the like.
  • the insulating film may be one layer or a plurality of layers. In case that the insulating film comprises a plurality of layers, conductive layers may be interposed between respective insulating films, provided that the conductive layers are arranged in such a way so as not to connect electrically between the plurality of external connection terminals.
  • the circuit substrate is provided with an anisotropic conductive film comprising conductive particles, on the external connection terminals.
  • the anisotropic conductive film is a film that has conductivity in an out-plane direction (normal direction with respect to the plane of the substrate) but lacks conductivity in an in-plane direction (direction within the plane of the substrate).
  • the terminals of the external member and the external connection terminals of the circuit substrate can be electrically connected to each other in a one-to-one basis.
  • the anisotropic conductive film has adhesiveness, to elicit physical adhesion between the external connection terminals and the external member.
  • anisotropic conductive film examples include anisotropic conductive films that electrically connect the external connection terminals to the external member by way of conductive particles contained in an insulating material.
  • the shape of the conductive particles is not particularly limited. The particles may be cubic, octahedral or the like, but preferably spherical.
  • the external connection terminal is connected to the wiring by way of at least one contact hole formed in the insulating film, such that the length from one end to the other end, in a plan view, of a region formed with one or more contact holes that connect to a specific external connection terminal is greater than the diameter of each of the conductive particles.
  • the external member and the external connection terminals are connected by way of an anisotropic conductive film, and the external connection terminals and wiring disposed directly below (at an region of overlap, in a plan view) the external connection terminals are connected by way of contact holes formed in the insulating film.
  • Two modes can be roughly distinguished herein, namely an mode (first mode) wherein one contact hole is provided for one external connection terminal, and an mode (second mode) wherein a plurality of contact holes is provided for one external connection terminal, as modes wherein the length, from one end to the other end, of a region at which there are formed one or more contact holes that connect to a specific external connection terminal is greater than the diameter of each of the conductive particles.
  • a conductive particle 817b may end up breaking a conductive portion of a contact hole 818 that connects a wiring 815 and an external connection terminal 816 on a insulating film 814 formed at a region in which the contact hole 818 is not formed. This may give rise to a connection fault.
  • One factor underlying the above occurrence is that the conductive layer on the contact hole wall surface is thinner than the conductive layer on the surface of the terminal.
  • a connection fault may occur due to breakage of the contact hole wall surface and/or of the conductive layer (external connection terminal) in the vicinity of the contact hole.
  • the external connection terminal is connected to the wiring via only one contact hole.
  • at least part of the contact hole has a greater diameter than the diameter of each of the conductive particles.
  • the major-axis length of the contact hole (in square or perfectly circular contact holes, it can be considered that major axis is equal to minor axis) may be greater than the diameter of each of the conductive particles.
  • Mode 1 (first mode) allows effectively suppressing disconnection between wiring and external connection terminals caused by contact hole breakage on account of pushing by conductive particles. The mode is effective for preventing connection faults.
  • the diameter of conductive particles denotes the diameter of the conductive particles in case of spherical conductive particles, and denotes the largest diameter of the conductive particles when the latter are non-spherical, for instance ellipsoidal or the like.
  • the diameter of the conductive particles can be measured, for instance, by optical microscopy.
  • the conductive particle used for measurements may be, for instance, one arbitrarily selected particle from among a plurality of conductive particles that overlap the specific external connection terminal.
  • the external connection terminal is connected to wiring by way of a plurality of contact holes, such that the length, from one end to the other end in a plan view, of a region at which the plurality of contact holes is formed is greater than a diameter of each of the conductive particles.
  • a plurality of contact holes one group of contact holes
  • the distance between one site at the outer edge of one contact hole up to a site at the outer edge of another contact hole is greater than the diameter of each of conductive particles.
  • the distance L from one end to the other end of a plurality of contact holes 8 is sufficient for the distance L from one end to the other end of a plurality of contact holes 8 to be greater than the diameter of a conductive particle 17b.
  • the length from end to end of two or more contact holes connected to one external connection terminal i.e. the greatest length from one arbitrary site at the outer edge of a contact hole provided in one external connection terminal, up to the other site (may be one site at the outer edge of the same contact hole, or one site at the outer edge of another contact hole), need only be greater than the diameter of each of the conductive particles.
  • connection between wiring and external connection terminals can be secured in a particularly reliable manner in a mode wherein each contact hole has a diameter greater than the diameter of each of the conductive particles.
  • the greatest length, from one end to the other end, of the region at which there are formed one or more contact holes that connect to a specific external connection terminal is preferably 1.5 or more times as long as the diameter of each of the conductive particles, in terms of securing a margin for deformation that arises from pushing pressure, with a view to preventing connection faults more reliably.
  • the sizes of the contact holes provided in the substrate are dissimilar.
  • the diameter of the contact holes may be different for each external connection terminal to which the contact hole is connected.
  • the anisotropic conductive film need only contain conductive particles having a diameter smaller than the length, from one end to the other end, of one contact hole or one group of contact holes formed to the smallest size from among a plurality of contact holes in the substrate (instance where one contact hole is formed in one external connection terminal) and a plurality of groups of contact holes (instance where a plurality of contact holes is formed in one external connection terminal).
  • the contact holes formed in the insulating film are ordinarily formed by dry etching, wet etching or the like.
  • the length of the contact hole, from one end to the other end may be dissimilar between the top face (face on the side of the external connection terminal) and the bottom face (face on the side of the substrate) of the insulating film, if the hole is formed to a tapered or reverse-tapered shape.
  • the length, from one end to the other end, of the region at which there are formed one or more contact holes that connect to a specific external connection terminal need only be greater than the diameter each of of the conductive particles at least at the top face of the insulating film. Breakage of the external connection terminal on account of the conductive particles can be fully prevented if the length, from one end to the other end, of the contact hole, at least at the top face of the insulating film, is greater than the diameter of each of the conductive particles.
  • the shape of the contact hole is not particularly limited, and may be polygonal, for instance, square, rectangular or triangular; or rounded, for instance perfectly circular, elliptical or the like.
  • the shape of the contact hole, in a plan view is an elliptical shape
  • the reliability of the connections can be increased by preventing complete breakage of the conductive portion between the wiring and the external connection terminal, if the major axis of the ellipse is greater than the diameter of each of the conductive particles, even if the minor axis of the ellipse is smaller than the diameter of each of the conductive particles.
  • the contact hole may be an elongated hole, in a plan view, such that the largest diameter of the elongated hole is greater than the diameter of each of the conductive particles.
  • the largest diameter of the elongated hole is preferably 1.5 or more times as long as the diameter of each of the conductive particles.
  • the shape of the elongated hole has a minor axis and a major axis, the shape being for instance an ellipse, a rectangular shape, an isosceles triangular shape or the like.
  • minor axis denotes the shortest diameter of the hole in a plan view
  • major axis denotes the longest diameter of the hole in a plan view.
  • the area of the contact hole is not particularly limited, but is preferably greater than the area of conductive particles, in a plan view.
  • a contact hole having a large area entails a greater contact area between the wiring and the external connection terminal. The resistance at the connection portion can be reduced as a result.
  • the external member connected to the anisotropic conductive film is not particularly limited, and may be, for instance, an electronic component such as a resistor, a capacitor, a coil, a connector, a diode, a transistor or the like; or a flexible printed circuit (FPC) board, a chip (COG: Chip on Glass) or resin film (COF: Chip on film) having formed thereon an integrated circuit (IC) that comprises circuit elements and wiring.
  • FPC flexible printed circuit
  • COG Chip on Glass
  • COF Chip on film
  • IC integrated circuit
  • Other examples include, for instance, a printed wiring board (PWB), a printed circuit board (PCB), a tape carrier package (TCP) or the like.
  • PWB printed wiring board
  • PCB printed circuit board
  • TCP tape carrier package
  • the circuit substrate of the present invention comprises preferably an external member on an anisotropic conductive film.
  • the external member comprises a conductive protrusion at a region overlapping the external connection terminal.
  • Such conductive protrusions are also referred to as "external connection wiring" or "bumps".
  • the conductive protrusion is connected to the external connection terminal by way of the conductive particles in the anisotropic conductive film.
  • the configuration of the circuit substrate of the present invention is not particularly limited as regards the presence or absence of constituent elements other than the above-described essential constituent elements, namely the wirings, the insulating film, the external connection terminal, the anisotropic conductive film and the contact holes.
  • the circuit substrate of the present invention may be appropriately used as a display device substrate employed in liquid crystal display devices or the like.
  • the circuit substrate may be provided with, for instance, switching elements, such as thin film transistors (TFTs) for driving the pixels, as the smallest units that make up the display image, wiring such as source wiring and gate wiring that transmit signals to the pixels, as well as pixel electrodes for eliciting display.
  • switching elements such as thin film transistors (TFTs) for driving the pixels, as the smallest units that make up the display image
  • wiring such as source wiring and gate wiring that transmit signals to the pixels, as well as pixel electrodes for eliciting display.
  • the circuit substrate may be provided with circuits such as driver circuits, power supply circuits, electrostatic discharge (ESD) protective circuits or the like.
  • driver circuits include, for instance, source driver circuits and gate driver circuits.
  • circuits that make up a driver circuit include, for instance, transmission gates, latch circuits, timing generators, inverter circuits by a power source circuit or the like.
  • the wiring has a wide portion that projects laterally with respect to the extension direction of the wiring, in a plan view, such that the contact hole is provided in the wide portion.
  • the wiring has a wide portion that widens laterally with respect to the extension direction of the wiring, in a plan view; a contact hole is formed in the insulating film, on the wide portion; and the wiring and the external connection terminal are connected by way of the contact hole.
  • the area of the contact hole formed in the insulating film can be increased thanks to the wide portion that projects with respect to the extension direction. This allows effectively preventing connection faults.
  • the extension direction is the direction in which wiring extends linearly.
  • the extension direction denotes the direction in which the wiring extends at the site where the wiring is connected to the external connection terminal; in other words, the direction pointing from the bent portion towards the external connection terminal.
  • the extension direction is the direction denoted by the blanked arrow in Fig. 1 .
  • the lateral direction with respect to the extension direction is the width direction of the wiring, for instance the direction denoted by the double-headed arrow in the circuit substrate illustrated in Fig. 1 .
  • the wide portion projects laterally towards only one side with respect to the wiring extension direction, in a plan view.
  • the feature of projecting towards only one side with respect to the extension direction means that the width of the wiring increases (widens) towards either side in the width direction of the wiring.
  • the wiring width can be expanded only in a direction in which other wiring or the like is not disposed, and hence the length from one end to the other end of the contact hole increases, without widening of the distance between wirings. Connection faults between the wiring and the external connection terminal can be prevented thereby.
  • the distance between the wirings can be reduced, while preventing contact between wirings, to a greater extent than in the case where the wide portion projects towards both sides in the width direction. This allows reducing, as a result, the wiring area.
  • the line width in the pads of contact holes is ordinarily greater than the wiring width. In a mode where the wide portion projects laterally towards both sides in the width direction, therefore, the distance between wirings is larger, and it becomes difficult to increase the number of wirings that are disposed under the external connection terminal.
  • the shape of the wide portion is not particularly limited, so long as it expands laterally with respect to the extension direction.
  • the shape may be, for instance, that of a wide portion 19a in which wiring 19 widens in the form of a semicircle, as illustrated in Fig. 14(a) , or the shape of a wide portion 20a in which wiring 20 widens in the form of a square, as illustrated in Fig. 14(b) , or the shape of a wide portion 21a in which wiring 21 widens in the form of a triangle, as illustrated in Fig. 14(c) .
  • the mode of Fig. 14(a) the mode of Fig. 14(b) and the mode of Fig.
  • the wide portion is referred to as a wiring portion within the area indicated by the double-headed arrow in the figure.
  • a shape widened in the form of a square shape is suitable in terms of increasing the area of the wide portion.
  • the corners thereof become ordinarily rounded, for reasons of patterning precision. Even with rounded corners, a square shape and a triangular shape may be regarded as such if the shape is substantially square or triangular.
  • the wide portion 15a may be formed at the leading end of the wiring 15, as illustrated in Fig. 12(a) .
  • the wide portion 16a may be formed halfway the wiring 16, as illustrated in Fig. 12(b) .
  • the circuit substrate has, in a plan view, two or more wirings extending parallelly, and two or more external connection terminals arrayed in the extension direction of the wirings; the two or more wirings have each a wide portion projecting towards an end portion side or an inward side of the circuit substrate, and a wiring disposed on the side toward which the wide portion projects is shorter, in the extension direction, than an adjacent wiring.
  • the circuit substrate has, in a plan view, two or more wirings extending parallelly, and two or more external connection terminals arrayed in the extension direction of the wirings; the two or more wirings have each a wide portion projecting towards an end portion side of the circuit substrate, and a wiring disposed at the end portion side is shorter, in the extension direction, than an adjacent wiring (adjacent wiring disposed on an inward side); and (2) the circuit substrate has, in a plan view, two or more wirings extending parallelly, and two or more external connection terminals arrayed in the extension direction of the wirings; the two or more wirings have each a wide portion projecting towards the inward side of the circuit substrate, and a wiring disposed on an inward side is shorter, in the extension direction, than an adjacent wiring (adjacent wiring disposed on an end portion side).
  • the direction in which the wide portion projects is a direction towards either side, with respect to the wiring extension direction, and there is shortened the length, in the extension direction, of the wiring disposed on the side towards which the wide portion projects.
  • the wide portion projects towards a side on which no wiring is disposed. Even if a wide portion is provided, therefore, the spacing between wirings that extend parallelly does not become shorter at the wide portion of one wiring and the another wiring adjacent to the wiring, and thus the wide portion can be provided while securing sufficient distance between wirings.
  • the area of the region at which the wiring is disposed can be reduced as a result. This affords a narrower frame in cases where the circuit substrate of the present invention is used as a display device substrate.
  • the length in the extension direction denotes herein the length in the direction of the external connection terminal, from a portion at which wiring bends, for instance as indicated by B1, B2 and so forth in the circuit substrate illustrated in Fig. 1 .
  • the term "parallel” applies not only to perfect parallelism, but also to instances of substantial parallelism, such as instances where the angle formed between wirings is no greater than 5°, in a case of two or more wirings that extend parallelly to each other.
  • the end portion side of the circuit substrate denotes herein a side close to the end portion of the circuit substrate, from among both sides with respect to the wiring extension direction.
  • the inward side of the circuit substrate denotes herein a side opposite to the side close to the end portion of the circuit substrate, from among both sides with respect to the wiring extension direction.
  • the arrangement mode of the two or more external connection terminals is not limited, so long as the two or more external connection terminals are arrayed in the direction in which the wirings extend.
  • an external connection terminal whose short side is parallel to the wiring extension direction may be arranged alternately with an external connection terminal whose long side is parallel to the wiring extension direction.
  • the external connection terminals whose short side is parallel to the wiring extension direction are arrayed along a row, with spacings in between, in terms of reducing the area of the region at which wiring is disposed and afford thus a narrower frame.
  • the above-described mode (1) is suitable for equalizing wiring resistance between wirings on the end portion side and wirings on the inward side, and is advantageous for increasing the operational stability of the circuit substrate. That is because, as in the circuit substrate illustrated in Fig. 1 , when two or more parallel wirings bend at a corner of the substrate, a wiring on the end portion side is longer than a wiring on the inward side, and hence the length of the wiring on the end portion side, along the extension direction from the bent leading ends, is shorter than that of the wiring on the inwards side.
  • the lengths of the wirings on the end portion side and on the inward side can be made similar to each other thereby.
  • the above-described mode (2) is suitable for reducing the area of the region at which the wiring is disposed.
  • This is advantageous for achieving a narrower frame, in cases where the circuit substrate of the present invention is used as a display device substrate. That is because making inward-side wirings shorter in the extension direction than wirings on the end portion side allows forming a region in which no wiring is disposed, and allows arranging elements such as circuit-forming wiring, a thin-film transistor or the like, at a region close to the inward side below the external connection terminal.
  • wiring disposed on the end portion side of the circuit substrate is longer than wiring disposed on the inward side. Therefore, circuits such as transistors, as well as wiring connected thereto, are disposed below the external connection terminal, and there is reduced the area for forming the circuits or the like.
  • the two or more wirings are connected to the external connection terminal by way of contact holes having dissimilar area.
  • the arrangement relationship between the wiring and the external connection terminal may be, for instance, the one illustrated in Fig. 5 , wherein a wiring points towards the wiring extension direction, an adjacent wiring thereto is already connected to another external connection terminal, and no wiring is disposed at one of the wide portions of the wiring (on one side with respect to the extension direction).
  • the area of the wide portion can be increased in such a case, and hence the area of the contact hole can be made accordingly greater.
  • This allows adjusting the contact resistance between the external connection terminal and the wirings, which in turns allows compensating differences in wiring resistance due to differences in wiring length. Also, the occurrence of connection faults can be suppressed by increasing the area of the contact holes.
  • the two or more wirings are connected to contact holes such that the longer the wiring length, the greater the area of the contact hole is.
  • the resistance of wiring increases as the wiring length increases.
  • wiring resistance is smaller in shorter wiring, positioned inward of the circuit substrate, than in longer wiring, positioned on the end portion side of the circuit substrate, for instance in the case illustrated in Fig. 5 . Therefore, wiring resistance can be made uniform, and the resistance of the contact hole portions can be adjusted, by increasing the area of the contact holes for wiring having a long wiring length, and decreasing the area of contact holes having a short wiring length. More uniform wiring resistance translates into enhanced operation stability of the circuit substrate.
  • wiring length denotes the length of a continuous stretch of wiring that is joined to an element in a circuit.
  • the continuous stretch of wiring may be made up of wirings formed in different layers but connected to each other.
  • the present invention is also a display panel provided with the above-described circuit substrate, and a display device provided with such a display panel.
  • the present invention can be used in various types of display device, for instance in liquid crystal displays, plasma displays, inorganic electroluminescent displays, organic electroluminescent displays and the like.
  • connection faults between wiring and external connection terminals can be suppressed by setting the length, from one end to the other end, of a region at which there are formed one or more contact holes that connect to one external connection terminal, to be greater than the diameter of conductive particles, as described above. Manufacturing yields can be improved and productivity can be likewise enhanced as a result.
  • connection faults forming a wide portion in wiring allows also shortening the distance between wirings. This affords a narrower frame in the display device, and allows reducing the size and weight of the display device.
  • the display device can therefore be suitable used in portable electronic devices such as mobile phones, PDAs and the like.
  • the circuit substrate of the present invention affords stable connection between wiring and external connection terminals, and allows suppressing the occurrence of connection faults.
  • Fig. 1 is a plan-view schematic diagram illustrating an end portion of a circuit substrate according to Embodiment 1.
  • Fig. 2 is a cross-sectional schematic diagram of the circuit substrate illustrated in Fig. 1 cut along line segment A-B.
  • the circuit substrate according to Example 1 is a display device substrate used in liquid crystal display devices.
  • thin film transistors for pixel driving, as well as pixel electrodes, driver circuits and so forth are formed on the inward side of the circuit substrate.
  • the end portion of the circuit substrate according to Example 1 has a substrate 110, and sequentially formed thereon, a base coat film 111, a first insulating film 112, a second insulating film 113, wirings 115, and a third insulating film 114.
  • External connection terminals 116 being a stack of a metal film 116a and a transparent conductive film 116b, are disposed on the third insulating film 114.
  • the film thickness of the third insulating film 114 is, for instance, 0.5 to 4 ⁇ m, and the film thickness of each external connection terminal is, for instance, 100 to 1000 nm.
  • the external connection terminals 116 are connected to wide portions 115a of wiring by way of contact holes 118 formed in the third insulating film 114.
  • An anisotropic conductive film 117 is disposed on the external connection terminals 116, in order to electrically connect the external connection terminals 116 and external connection wirings 119a of a flexible printed circuit (FPC) board 119.
  • the anisotropic conductive film 117 contains conductive particles 117b in an insulating material 117a.
  • the external connection wirings 119a and so forth are provided on the surface of a resin substrate 119b.
  • the wirings 115 and the external connection terminals 116 of the circuit substrate according to Example 1 are connected by way of the contact holes 118 formed in the third insulating film 114, at the wide portions 115a of the wirings 115 that extend parallelly.
  • the wirings 115 extend along the end portion of the substrate 110, and bend downwards, from the right direction in Fig. 1 , in the vicinity of a corner of the substrate 110.
  • a plurality of identically-shaped external connection terminals 116 are arrayed, spaced apart from each other, downwards from a corner of the substrate 110.
  • Each wiring 115 extends downwards in Fig.
  • the wide portions 115a are portions in which wiring is made wider, projecting towards the end portion of the substrate 110 (outwards), in order to for the contact holes 118 to be disposed therein.
  • the wide portions 115a are termini of the wirings 115. From among wirings 115 that extend parallelly, the further a wiring 115 is formed towards the end portion of the substrate 110, the further up in Fig. 1 the respective wide portion 115a is provided, i.e. the shorter becomes the length of the wiring having a bent leading end.
  • the width of the wirings 115 is, for instance, 2 to 4 ⁇ m.
  • the width of the wide portions 115a (lateral width with respect to the extension direction), is for instance 4 to 6 ⁇ m.
  • the contact holes 118 are shaped as a rectangle having a major-axis length (diameter length) of, for instance, 3 to 8 ⁇ m.
  • the major-axis length of the contact holes denotes the length at the top face of the third insulating film 114.
  • the diameter of each of the conductive particles 117b is set to be smaller than the major-axis length of the contact hole, for instance from 2 to 6 ⁇ m. The value thereof is based on the diameter (largest diameter) after mounting of the FPC 119, in a plan view of the circuit substrate.
  • the diameter of the conductive particles can be calculated by optical measurement methods using an optical microscope. The above considerations on the value of the diameter of the conductive particles apply also to other embodiments described below.
  • the largest diameter of the contact holes 118 is greater than the diameter of the conductive particles 117b.
  • the external connection terminals 116 and the external connection wirings 119a of the FPC 119 do not become electrically disconnected, even if the transparent conductive film 116b and the metal film 116a that make up the external connection terminals 116 are crushed by the conductive particles 117b. Connection reliability is thus excellent.
  • the distance between wirings 115 can be shortened thanks to the wide portions 115a that are formed in the wirings 115 and that protrude only towards the end portion of the circuit substrate. This allows reducing, as a result, the area that must be secured within the plane the substrate in order to arrange the wirings 115, and enables frame narrowing.
  • the wirings 115 disposed on the circuit substrate, on the end portion side are connected to the external connection terminals 116 in such a manner that there decreases the length from the bent portion of the wirings. This allows the length of wirings disposed on the side of the end portion to be similar to the length of wirings disposed on the inward side, and allows uniformizing resistance between wirings 115.
  • the length of wiring P disposed outermost on the end portion side of the circuit substrate equals A1+B1
  • the length of adjacent wiring Q equals A2+B2.
  • A1>A2 and B1 ⁇ B2 and hence the wiring lengths in wiring P and wiring Q become similar, whereby resistance between both wirings can be made more uniform, as compared with a case in which wirings are connected, to external connection terminals, sequentially from wiring disposed on the inward side.
  • Fig. 3 is a plan-view schematic diagram illustrating an end portion of a circuit substrate according to Example 2.
  • Fig. 4 is a cross-sectional schematic diagram of the circuit substrate illustrated in Fig. 3 cut along line segment C-D.
  • the thickness of the wirings, insulating film and so forth in the circuit substrate according to Example 2 are identical to those in Example 1.
  • the circuit substrate according to Embodiment 2 has a substrate 210, and sequentially stacked thereon, a base coat film 211, a semiconductor layer 220, a first insulating film (gate insulator) 212, gate wirings 222 and a second insulating film 213.
  • Wirings 215 ( Fig. 4 shows a wide portion 215a of the wirings 215) and source/drain wirings 221 are disposed on the second insulating film 213.
  • the source/drain wirings 221 are connected to the semiconductor layer 220 by way of contact holes 218 formed in the second insulating film 213 and the first insulating film (gate insulator) 212.
  • a third insulating film 214 is disposed on the wirings 215 and the source/drain wirings 221.
  • External connection terminals 216 being a stack of a metal film 216a and a transparent conductive film 216b, are disposed on the third insulating film 214.
  • the external connection terminals 216 are connected to wide portions 215a of the wirings 215 by way of the contact holes 218 formed in the third insulating film 214.
  • An anisotropic conductive film 217 is disposed on the external connection terminals 216, in order to electrically connect the external connection terminals 216 and external connection wirings 219a of the FPC 219.
  • the anisotropic conductive film 217 contains conductive particles 217b in an insulating material 217a.
  • the external connection wirings 219a and so forth are provided on the surface of a resin substrate 219b.
  • the wirings 215 and the external connection terminals 216 of the circuit substrate according to Example 2 are connected by way of the contact holes 218 formed in the third insulating film 214, at the wide portions 215a of the wirings 215 that extend parallelly.
  • the wirings 215 are connected to the external connection terminals 216 in such a manner that the length from the bent portion of the wiring is shorter the further the wiring is disposed inwards of the circuit substrate.
  • the wirings 215 have a wide portions 215a that widen (project) towards the inward side of the circuit substrate.
  • the width of the wirings 215 is for instance 2 to 4 ⁇ m, and the width of the wide portions 215a is for instance 4 to 6 ⁇ m.
  • the contact holes 218 are shaped as a rectangle having a major-axis length of, for instance, 3 to 8 ⁇ m, larger than the diameter of conductive particles.
  • the major-axis length (diameter length) of the contact holes denotes the length at the top face of the third insulating film 214.
  • Example 2 the connection position of the external connection terminals 116 to the wirings 115 shifts from the inwards side towards the end portion of the circuit substrate, as viewed from a corner of the circuit substrate, downwards in a longitudinal direction. An empty region is thus formed in the vicinity of the inward side of the circuit substrate, below the external connection terminal to which there is connected the wiring disposed on the end portion side of the circuit substrate.
  • wirings that make up transistors, as well as a semiconductor layers and the like can be formed below the external connection terminals 116, in addition to the wirings 115 that are connected to the external connection terminals 116.
  • a narrower frame can be achieved thereby.
  • Fig. 5 is a plan-view schematic diagram illustrating an end portion of a circuit substrate according to an Embodiment of the invention.
  • Fig. 6 is a cross-sectional schematic diagram of the circuit substrate illustrated in Fig. 5 cut along line segment E-F.
  • the thickness of the wirings, insulating film and so forth in the circuit substrate according to the Embodiment are identical to those in Example 1.
  • the circuit substrate according to the Embodiment is a display device substrate used in liquid crystal display devices.
  • thin film transistors for pixel driving, as well as pixel electrodes, driver circuits and so forth are formed on the inward side of the circuit substrate.
  • a substrate 310 has sequentially stacked thereon a base coat film 311, a first insulating film (gate insulator) 312, a second insulating film 313, wirings 315 and a third insulating film 314.
  • External connection terminals 316 being a stack of a metal film 316a and a transparent conductive film 316b, are disposed on the third insulating film 314.
  • the external connection terminals 316 are connected to wide portions 315a of wiring by way of contact holes 318 formed in the third insulating film 314.
  • An anisotropic conductive film 317 for electrically connecting the external connection terminals 316 and external connection wirings 319a of an FPC 319, is disposed on the external connection terminal 316.
  • the anisotropic conductive film 317 contains conductive particles 317b in an insulating material 317a.
  • the external connection wirings 319a and so forth are provided on the surface of a resin substrate 319b.
  • the wide portions 315a of the wirings 315 extending parallelly are connected to the external connection terminals 316 by way of respective contact holes 318 that are formed in the third insulating film 314, as illustrated in Fig. 5 .
  • the wirings 315 are connected to the external connection terminals 316 in such a manner that the length from the bent portion of the wiring is shorter the further the wiring is disposed inwards in the circuit substrate.
  • Each wiring 315 has a wide portion 315a that widens (projects) towards the inward side of the circuit substrate.
  • the width of the wirings 315 is, for instance, 2 to 4 ⁇ m.
  • the width of the wide portions 315a is set in such a manner so as to become consecutively smaller for wirings disposed further inwards from the wiring that is disposed on the end portion side of the circuit substrate, and is set to, for instance, 4 to 6 ⁇ m.
  • the contact holes 318 are rectangular in shape, and the diameter length of the contact holes 318 is designed, like the width of the wide portions 315a, in such a manner so as to become consecutively smaller for contact holes disposed further inwards from the wiring that is disposed on the end portion side of the circuit substrate.
  • the major-axis length of the contact holes 318 is larger than the diameter of the conductive particles 317b.
  • the longer the wirings 315 are, the larger becomes the area of the wide portions 315a and the contact holes 318.
  • This allows uniformizing resistance between wirings 315.
  • the increased wiring resistance derived from the longer wiring length can be brought close to that of other shorter wiring.
  • the wiring length is C1+D1 for a wiring R disposed furthest inward within the area shown in the figure
  • the length of a wiring S disposed second is C2+D2, such that the length of wiring R disposed further inward is longer.
  • the area of the contact holes 318 is greater for wirings disposed further outwards.
  • Fig. 7 is a plan-view schematic diagram illustrating an end portion of a circuit substrate according to Example 4.
  • the configuration of the circuit substrate according to Example 4 is substantially identical to that of Example 1, except that herein the area of the contact holes is different, and the wiring shape is different in that, for instance, no wide portions are provided.
  • wirings 415 extending parallelly are connected to external connection terminals 416 by way of contact holes 418 that are formed in a third insulating film 414.
  • the contact holes 418 are provided as a plurality thereof for each wiring, and are connected to each external connection terminal 416 at a plurality of sites.
  • the width of the wirings 415 ranges from 3 to 5 ⁇ m.
  • the major-axis length of the contact holes 418 ranges from 2 to 4 ⁇ m, and the spacing between contact holes 418 ranges from 2 to 4 ⁇ m.
  • Six contact holes 418 are formed in each wiring. Therefore, the length of the region at which the contact holes 418 are formed in one external connection terminal 416, from one end to the other end of the region, ranges from 22 ⁇ m (namely 6 ⁇ 2 ⁇ m+5 ⁇ 2 ⁇ m) to 44 ⁇ m (namely 6 ⁇ 4 ⁇ m+5 ⁇ 4 ⁇ m).
  • the diameter of each of the conductive particles ranges from 2 to 6 ⁇ m.
  • the plurality of contact holes 418 is formed on one wiring 415, and is connected to the external connection terminal 416 at a plurality of sites.
  • Fig. 8 is a plan-view schematic diagram illustrating an end portion of a circuit substrate according to Example 5.
  • the configuration of the circuit substrate according to Example 5 is substantially identical to that of Example 1, except that herein the area of the contact holes is different, and the wiring shape is different in that, for instance, no wide portions are provided.
  • wirings 515 extending parallelly are connected to external connection terminals 516 by way of contact holes 518 that are formed in a third insulating film 514.
  • the contact holes 518 are shaped as elongated holes (rectangular-shaped) in the extension direction of the wirings 515.
  • Such a shape allows preventing connection faults in that the entire connection portion is not destroyed even when part of the contact hole is crushed by conductive particles.
  • the major diameter of the rectangular shape ranges from 3 to 20 ⁇ m, which is larger than the diameter of conductive particles.
  • No wide portion is formed in the wiring of Example 5. In a more preferred embodiment, however, a wide portion is formed in the wirings 515, and the contact holes 518 are elongated holes.
  • Fig. 9 is a plan-view schematic diagram illustrating an end portion of a circuit substrate according to Example 6.
  • the configuration of the circuit substrate according to Example 6 is substantially identical to that of Example 1, except that herein the area of the contact holes is different, and the wiring shape, such as the shape of the wide portions, is different, as illustrated in Fig. 9 .
  • wirings 615 extending parallelly are connected to external connection terminals 616 by way of contact holes 618 that are formed in a third insulating film 614.
  • the wirings 615 have wide portions 615a that protrude laterally towards both sides with respect to the direction in which the wirings extend (extension direction).
  • the major-axis length of the contact holes 618 ranges from 4 to 9 ⁇ m.
  • the diameter of each of the conductive particles 617b ranges from 3 to 6 ⁇ m.
  • the major-axis length of the contact holes 618 is larger than the diameter of each of the conductive particles 617b. Disconnection due to the conductive particles 617b can be prevented thereby, since the major-axis length of the contact holes 618 is thus larger than the diameter of each of the conductive particles 617b.
  • the width of the wirings 615 ranges from 2 to 4 ⁇ m, and the width of the wide portions 615a ranges from 3 to 6 ⁇ m.
  • Example 6 the wide portions are formed projecting laterally towards both sides with respect to the wiring extension direction. Therefore, the distance between wirings at the wide portions is smaller than in the configurations depicted in the Embodiment and Examples 1 to 5. As a result, the spacing between wirings may have to be kept not smaller than a given spacing, in order to prevent short-circuits between wirings at the wide portions, and the number of wirings that are disposed directly below the external connection terminals may be limited.
  • Fig. 10 is a plan-view schematic diagram illustrating an end portion of a circuit substrate according to Comparative Example 1.
  • Fig. 11 is a cross-sectional schematic diagram of the circuit substrate illustrated in Fig. 10 cut along line segment G-H.
  • a first insulating film 813 and wirings 815 are disposed on a substrate 810, at an end portion of the circuit substrate according to Comparative Example 1.
  • a second insulating film 814 is disposed on the wirings 815, and external connection terminals 816 formed out of metal are disposed on the second insulating film 814.
  • the external connection terminals 816 are connected to the wirings 815 by way of contact holes 818 formed in the third insulating film 814.
  • An anisotropic conductive film 817 for connection between the external connection terminals 816 and external connection wirings 819a of a flexible printed circuit (FPC) board 819, is disposed on the external connection terminals 816.
  • the anisotropic conductive film 817 contains conductive particles 817b in an insulating material 817a.
  • the external connection wirings 819a formed on the anisotropic conductive film 817 are electrically connected to the external connection terminals 816 by way of the anisotropic conductive film 817.
  • the external connection wirings 819a and so forth are provided on the surface of a resin substrate 819b.
  • the leading ends of the wirings 815 extending parallelly are connected to the external connection terminals 816 by way of the contact holes 818 that are formed in the second insulating film 814, as illustrated in Fig. 10 .
  • the major-axis length of the contact holes 818 is 2 ⁇ m.
  • the major-axis length of the contact holes 818 denotes the length at the top face of the second insulating film 814.
  • the diameter of the conductive particles 817b is 5 ⁇ m.
  • a method for manufacturing the circuit substrates according to the Embodiment and the examples is explained below.
  • the manufacturing method will be explained based on an example of the circuit substrate according to Example 2 illustrated in Fig. 3 and 4 , but the circuit substrates of the Embodiment and Examples 1 and 4 to 6 can also be manufactured in accordance with the same method, after suitable modification of, for instance, wiring shape and contact hole shape.
  • the insulating substrate 210 is firstly subjected to cleaning and pre-annealing.
  • the type of the insulating substrate 210 is not particularly limited, but is preferably, for instance, a glass substrate or resin substrate, from the viewpoint of costs, among others. Steps (1) to (10) below are carried out next.
  • the base coat film 211 Through sequential formation of a SiON film and a SiOx film by plasma-enhanced chemical vapor deposition (PECVD).
  • a starting material gas for forming the SiON film include, for instance, a mixed gas of monosilane (SiH 4 ), nitrous oxide gas (N 2 O) and ammonia (NH 3 ).
  • the SiOx film is formed using tetraethyl ortho silicate (TEOS) gas as a starting material gas.
  • TEOS tetraethyl ortho silicate
  • the base coat film 211 there may be used a silicon nitride (SiNx) film formed using, for instance, a mixed gas of monosilane (SiH 4 ) and ammonia (NH 3 ) as a starting material gas.
  • SiNx silicon nitride
  • An amorphous silicon (a-Si) film is formed by PECVD.
  • starting material gas for forming the a-Si film include, for instance, SiH4, disilane (Si 2 H 6 ) and the like.
  • the a-Si film formed by PECVD comprises hydrogen, and hence a treatment for lowering the hydrogen concentration in the a-Si layer is performed at about 500°C (dehydrogenation treatment).
  • Laser annealing is performed next, followed by formation of a polysilicon (p-Si) film through melting of the a-Si film, cooling and solidification. Laser annealing is performed, for instance, using an excimer laser.
  • a metallic catalyst may be applied, without performing a dehydrogenation treatment.
  • a thermal treatment for solid-phase crystallization may be carried out, as a pre-treatment of laser annealing for forming the p-Si film.
  • dry etching is carried out using carbon tetrafluoride (CF 4 ) gas, to pattern the p-Si film and form the semiconductor layer 220.
  • a source region, a drain region, a channel region and so forth are formed, for instance by ion doping, in the semiconductor layer 220 after the belowdescribed first insulating film formation step, or after a gate electrode formation step.
  • the first insulating film (gate insulator) 212 comprising silicon oxide is formed using TEOS gas as a starting material gas.
  • the material of the first insulating film 212 is not particularly limited, and there may be used, for instance, a SiN x film, a SiON film or the like.
  • the starting material gas for forming the SiN x film and the SiON film may be the same as the starting material gas in the base coat film formation step described above.
  • the first insulating film 212 may be a stack comprising the above-mentioned plurality of materials.
  • a tantalum nitride (TaN) film and a tungsten (W) film are formed by sputtering.
  • a resist film is patterned to a desired shape, by photolithography, after which the gate electrode 222 is formed by dry etching using an etching gas in the form of a mixed gas in which there are adjusted the quantities of, for instance, argon (Ar), sulfur hexafluoride (SF 6 ), carbon tetrafluoride (CF 4 ), oxygen (O 2 ), chlorine (Cl 2 ) and the like.
  • the material of the gate electrode 222 there can be used a high-melting point metal having a planarized surface and stabilized characteristics and/or a low resistance metal , for instance tantalum (Ta), molybdenum (Mo), molybdenum tungsten (MoW) aluminum (Al) or the like.
  • the gate electrode 222 may be a stack comprising the above-mentioned plurality of materials.
  • a SiNx film as the second insulating film 213, is formed on the entire surface of the substrate, by PECVD.
  • a SiON film, TEOS film or the like may be used as the second insulating film 213.
  • a thin cap film (for instance, a TEOS film) about 50 nm thick may be formed under the second insulating film 213 in order to stabilize electric characteristics and enhance reliability of TFT characteristics by preventing, for instance, transient degradation.
  • a resist film is patterned to a desired shape, by photolithography, after which the first insulating film 212 and the second insulating film 213 are wet-etched using a hydrofluoric acid-based etching solution, to form thereby a contact hole for connecting the source/drain wiring 221 and the semiconductor layer 220.
  • Etching may be dry etching or a combination of wet etching and dry etching.
  • a titanium (Ti) film, an aluminum (Al) film and a Ti film are formed, in this order, by sputtering or the like.
  • a resist film is patterned to a desired shape, by photolithography, after which the Ti/Al/Ti metal multilayer film is patterned by dry etching, to form the first source/drain wiring 221.
  • the source region and drain region of the semiconductor layer 220 and the first source/drain wiring 221 are conductively connected by way of the contact hole formed in the first insulating film 212 and the second insulating film 213.
  • An Al-Si alloy or the like may be used, instead of Al, as the metal that makes up the source/drain wiring 221.
  • Al is used for lowering wiring resistance, but the above-described gate electrode materials (Ta, Mo, MoW, W, TaN or the like) may be used in a case of short wiring structures, where high heat resistance is required and a certain increase in resistance values is allowable.
  • the third insulating film 214 comprising silicon oxide is formed on the entire surface of the substrate, using TEOS gas as a starting material gas.
  • TEOS gas as a starting material gas.
  • a SiON film, TEOS film or the like may be used as the third insulating film 214.
  • An organic insulating film may also be used.
  • a resist film is formed on the entire surface of the substrate, and the resist film is patterned to a desired shape, by photolithography, after which the third insulating film 214 is wet-etched using a hydrofluoric acid-based etching solution, to form the contact hole 218 for connection between the external connection terminal 216 and the wiring 215.
  • Etching may be dry etching. Also, development of the resist film and etching of the third insulating film 214 may be carried out simultaneously.
  • a metal film and an ITO film are formed, by sputtering or the like, on the third insulating film 214 having the contact hole 218 formed therein, and a desired shape is patterned by photolithography, to form thereby the transparent conductive film 216b and the metal film 216a that make up the external connection terminal 216.
  • the metal film 216a is not particularly limited, but is preferably, for instance, a multilayer film of an aluminum film and a molybdenum film.
  • Aluminum films have high conductivity, but are susceptible to electrochemical corrosion. Accordingly, corrosion of the aluminum film can be prevented by forming a molybdenum film, as a barrier film, on the aluminum film. Ordinarily, the aluminum film and the molybdenum film are patterned together simultaneously.
  • the end portion of the aluminum film is covered by forming thereon a transparent conductive film, of ITO or the like, in order to prevent corrosion of the end portion. Corrosion prevention can be afforded thereby.
  • the transparent conductive film 216b is formed in the same step as that of the pixel electrodes that drive the pixels of the display device. Doing so allows streamlining the manufacturing process.
  • the external connection terminals are multilayer films of a metal film and a transparent conductive film, but are not particularly limited thereto, and may comprise a metal film alone.
  • the anisotropic conductive film 217 is affixed to the external connection terminal 216, and the FPC 219 having the external connection wirings 219a is affixed to the anisotropic conductive film 217.
  • a sealing material is formed on the circuit substrate, followed by affixing to an opposed substrate that has formed thereon, for instance, color filters and the like.
  • the sealing material that is used is not particularly limited, and may be a UV-curable resin, a thermosetting resin or the like. Thereafter, a liquid crystal is sealed between the circuit substrate and the opposed substrate, to complete thereby the liquid crystal display panel.
  • a liquid crystal display device can then be obtained by mounting polarizers and so forth on the liquid crystal display panel.
  • a narrow-frame display device can be achieved by reducing the substrate area that is devoted to laying the wiring.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)
EP09827400.4A 2008-11-19 2009-07-01 Circuit substrate, display panel, and display device Not-in-force EP2360661B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008296055 2008-11-19
PCT/JP2009/062060 WO2010058619A1 (ja) 2008-11-19 2009-07-01 回路基板、表示パネル及び表示装置

Publications (3)

Publication Number Publication Date
EP2360661A1 EP2360661A1 (en) 2011-08-24
EP2360661A4 EP2360661A4 (en) 2013-01-02
EP2360661B1 true EP2360661B1 (en) 2014-01-08

Family

ID=42198060

Family Applications (1)

Application Number Title Priority Date Filing Date
EP09827400.4A Not-in-force EP2360661B1 (en) 2008-11-19 2009-07-01 Circuit substrate, display panel, and display device

Country Status (7)

Country Link
US (1) US20110205716A1 (ja)
EP (1) EP2360661B1 (ja)
JP (1) JP5043202B2 (ja)
CN (1) CN102203840A (ja)
BR (1) BRPI0921573A2 (ja)
RU (1) RU2483389C2 (ja)
WO (1) WO2010058619A1 (ja)

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Also Published As

Publication number Publication date
US20110205716A1 (en) 2011-08-25
EP2360661A4 (en) 2013-01-02
EP2360661A1 (en) 2011-08-24
WO2010058619A1 (ja) 2010-05-27
CN102203840A (zh) 2011-09-28
RU2483389C2 (ru) 2013-05-27
RU2011124958A (ru) 2012-12-27
JP5043202B2 (ja) 2012-10-10
BRPI0921573A2 (pt) 2016-02-10
JPWO2010058619A1 (ja) 2012-04-19

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