EP2338066A1 - Dispositif et procédé de vérification d'un générateur d'impulsions à fréquence modulée - Google Patents

Dispositif et procédé de vérification d'un générateur d'impulsions à fréquence modulée

Info

Publication number
EP2338066A1
EP2338066A1 EP09782155A EP09782155A EP2338066A1 EP 2338066 A1 EP2338066 A1 EP 2338066A1 EP 09782155 A EP09782155 A EP 09782155A EP 09782155 A EP09782155 A EP 09782155A EP 2338066 A1 EP2338066 A1 EP 2338066A1
Authority
EP
European Patent Office
Prior art keywords
signal
frequency
measuring
measurement
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP09782155A
Other languages
German (de)
English (en)
Inventor
Hans-Georg Drotleff
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP2338066A1 publication Critical patent/EP2338066A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2822—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere of microwave or radiofrequency circuits
    • G01R31/2824—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere of microwave or radiofrequency circuits testing of oscillators or resonators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
    • G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
    • G01R23/15—Indicating that frequency of pulses is either above or below a predetermined value or within or outside a predetermined range of values, by making use of non-linear or digital elements (indicating that pulse width is above or below a certain limit)
    • G01R23/155—Indicating that frequency of pulses is either above or below a predetermined value or within or outside a predetermined range of values, by making use of non-linear or digital elements (indicating that pulse width is above or below a certain limit) giving an indication of the number of times this occurs, i.e. multi-channel analysers (for pulse characteristics)

Definitions

  • Electromagnetic interference or interference is subject to strict regulations.
  • EMC limit values are set in order to limit the load to a minimum and thereby avoid damage to humans and other systems.
  • the limits may relate in particular to which intensities per frequency range may be emitted by electronic devices or systems.
  • Clocks are generally formed as integrated circuits (ICs) and are used in electronic systems for outputting a clock signal. They are designed in particular as oscillators or frequency synthesizers and output a clock signal having a nominal frequency or center frequency. Although clocks contribute significantly to the proper functioning of mostly digital systems, they are at the same time the EMC main generator sources in electronic circuits.
  • Shielding, coatings, or special filter components are known to reduce EMC emissions. Due to the ever higher power densities, in particular the higher clock speeds and the ever stricter E MV regulations, however, such measures fall on their efficiency and cost limits.
  • spread spectrum oscillators are increasingly being used to limit peak emissions. These scatter their clock signal over a wide teres frequency spectrum and thus limit the peak emissions related to the individual frequency ranges. This dispersion is generally achieved by a frequency modulation with a modulation frequency well below the clock frequency.
  • the modulation signal can z. B. have a triangular shape or any other convenient form. By such SSO can be z. B. achieve a peak emission reduction of up to 20 dB.
  • a spread spectrum oscillator is known for example from German patent application DE 10 2005 013 593 A1.
  • the frequency modulation is generally achieved by an additional circuit; In this case, however, can not be directly recognized during operation, whether this frequency modulation is correct. Furthermore, it can not be easily recognized in an electronic system whether an SSO has actually been installed or z. B. erroneously an oscillator with a fixed frequency. In this case, therefore, a significant EMC pollution of the environment may occur without this being directly detectable in the device or electronic device.
  • the clock cycles of the clock in particular an SSO, counted in a measuring period.
  • the measurement periods may be fixed in order to achieve directly comparable values; in principle, however, they can also be adjusted during the measurement; so z.
  • the measurement period in Depending on the determined modulation frequency can be adjusted below.
  • the count values or cycle counts determined in several measurement periods are subsequently compared; In particular, they can be compared with each other. The frequency modulation to be checked should thus lead to a change in the cycle counts in successive measurement periods.
  • the invention is based on the idea that the modulation frequency of a frequency-modulated clock, in particular an SSO, is substantially smaller than the center frequency of the clock.
  • a counter namely the cycle counter, which in particular is digital and determines cycle counts. Due to the frequency modulation, the number of clock cycles occurring in fixed measurement periods should vary; in the absence of frequency modulation, fixed or slightly fluctuating values should result.
  • the measurement periods are advantageously determined by a measurement signal with corresponding measurement frequency.
  • the measuring frequency should preferably be at least twice as high as the modulation frequency in order to satisfy the sampling theorem. It may advantageously be two to seven times the modulation frequency. If the measuring frequency is chosen too large, the quantitative determination of the modulation frequency and thus of the spread or the scattering is again made more difficult.
  • the cycle counter can in particular be reset directly by the measuring signal.
  • a simple metrological structure with a direct determination of the different cycle counts or cycle counter readings is possible, which are subsequently read out over several measurement cycles or measurement periods, in order to achieve the minimum and maximum cycle count possible.
  • intermediate buffers or intermediate buffers can be used, which are each overwritten with the highest or lowest cycle count determined.
  • the determined minimum and maximum values, z. B. also by doubble buffering by means of additional result buffer are evaluated below. The determination or evaluation can then take place after an evaluation period, the more, z. B. 240 or 256 measuring periods, so that should have been made by the sufficient number of minimum and maximum values.
  • the spread or spread can be determined quantitatively. Furthermore, the nominal frequency, i. in general, the center frequency can be determined.
  • z. B by using a measuring number counter to count the number of measurement periods or meter periods and possibly a monitoring counter or watchdog counter.
  • the result can be z. B. binary or output as a PWM signal and used directly in a system.
  • the method according to the invention and the device according to the invention can be implemented in different ways.
  • an implementation in a programmable logic device for. As an FPGA or ASIC done.
  • the z. B. essentially by the cycle counter, the buffer, possibly input and output flip-flops, a logic circuit and possibly a clock processing for the male, to be examined clock signal can be formed.
  • an internal oscillator or clock generator for generating the measuring frequency may also be provided, for. B. also an existing internal clock signal, in which case by z. B. an internal switching device switching between this internal clock and an external measurement signal can be made possible.
  • the device according to the invention can also be integrated together with the clock or SSO.
  • FIG. 1 shows a modulation profile of a spread spectrum oscillator as a frequency versus time
  • Fig. 2 shows EMC frequency spectra of an oscillator with and without frequency modulation
  • Fig. 3 shows a block diagram of an FPGA implementation of the device according to the invention
  • FIG. 3a shows a block diagram of another FPGA implementation of the device according to the invention
  • FIG. 44 shows a block diagram of a test arrangement in which the device according to the invention is used as an independent testing device;
  • Fig. 5 shows an integration of the method in an electronic system for activation / evaluation only in the production
  • FIG. 6 shows an integration of the method according to the invention in a device on a circuit carrier during activation / evaluation of the device
  • Fig. 7 shows the device as an independent component
  • Fig. 8 shows the device according to the invention when integrated with an SSO
  • Fig. 9 shows the integration with a microcontroller
  • Fig. 1100 shows for an implementation example the frequency modulation and details of the measurement signal
  • Fig. 1 1 of the calculated counter differences as a function of the measurement modulation frequency ratio in oscillators with different spread.
  • FIG. 1 shows the modulation profile of a SSO as a function of the frequency f as a function of the time t.
  • the center frequency fjnid is fixed here;
  • a modulation profile is launched, after which f is periodically modulated between a lower value f_min and an upper value f_max, z.
  • f_min a lower value
  • f_max an upper value
  • z a modulation profile
  • Figure 2 shows an EMC frequency spectrum, d. H. the electromagnetic radiation intensity I as a function of the frequency f, in the ninth harmonic of clock oscillators, the curve k1 shows an oscillator with unmodulated frequency f and the curve k2 a spread spectrum oscillator 1. This results in a reduction of the peak emission of the spread spectrum oscillator 1 with respect to the non-modulated oscillator. Outside of the spread, the intensity I given in decibels (dB) drops slowly.
  • FIG. 3 shows the implementation of the method according to the invention and of the device according to the invention in an FPGA (Field Programmable Gate Array) 2, in a correspondingly highly simplified representation.
  • the overall arrangement 10 from FIG. 3 is thus formed by the FPGA 2 and the SSO 1.
  • the clock signal to be examined is sent to a clock processing device 3 in the FPGA 2, which outputs a correspondingly processed clock signal having the same frequency f_sso, firstly in the clock input 4a of a flip-flop 4 and secondly in the clock input 5a a (digital) cycle counter 5 is input.
  • a measurement signal m with the measurement frequency f_m is input to the input 4b of the flip-flop 4 and output from the flip-flop 4 again as a second measurement signal with the same measurement frequency f_m; the flip-flop 4 thus serves only for stabilization and is functionally no longer relevant.
  • the measuring signal m is input to the reset input (reset input) 5b of the cycle counter 5 and thus resets it in each case.
  • the SSO frequency to be examined f_sso - in this embodiment after appropriate preparation in the clock conditioning device 3 - enumerated in the cycle counter 5 over a fixed measurement period T_m, which determines by the externally input measurement signal m with the measurement frequency f_m which resets the cycle counter 5 respectively.
  • the measurement frequency f_m of z. B. 50 kHz is higher than the modulation frequency f_mod of 10 kHz, so that several measurement cycles or cycle counts of the cycle counter 5 are read out during a modulation.
  • the cycle counts are the final counts before cycle counter 5 is reset.
  • the cycle counter 5 If there is actually a modulation, ie fjmod ⁇ 0, the cycle counter 5 outputs different cycle counts as signal z, depending on where in the time domain the oscillator modulation curve is in the counting period. If there is no modulation, these values should be the same in the different readout cycles or reset cycles.
  • the cycle counter 5 outputs its counter readings of each measuring period T_m as signal z (cycle count z) to an upper buffer 6 and a lower buffer 7.
  • the upper buffer 6 contains a maximum intermediate buffer 6a for storing a maximum value and a downstream result.
  • Buffer 6b Accordingly, the lower buffer 7 contains a minimum intermediate buffer 7a for storing a minimum value and a result buffer 7b.
  • the maximum intermediate buffer 6a is preinitialized with the value 0x0000, the minimum intermediate buffer 7a with the value 0xFFFF.
  • the values of the intermediate buffers 6a, 7a are respectively saved in the subsequent result buffer 6b, 7b, which as such is known as doubble buffering. This ensures that the intermediate buffers 6a, 7a can change from counting period to counting period, but the result buffers 6b, 7b are only updated after the intermediate buffers 6a, 7a stabilize or settle, respectively their minimum or have reached maximum meter readings. When outputting the result, only the result buffers 6b, 7b are taken into account, resulting in a stable display. Thus, an evaluation period is formed from a sufficient number of measurement periods.
  • An evaluation device 8 is designed as a logic unit; it accesses the result buffers 6b, 7b and returns a result to an output memory, e.g. B. an output flip-flop 9, which subsequently outputs the output signal S2 as a status output signal.
  • the output flip-flop 9 and the evaluation device 8 are clocked by the clock frequency f_sso.
  • a measurement number counter 13 may be provided which determines the number of measurement periods T_m, i. meter periods), and thus serves to determine the evaluation period.
  • T_m the number of measurement periods
  • the intermediate buffers 6, 7 have stabilized and correlate with the minimum and maximum frequency of the SSO 1, so that the difference of the buffered min and max values Zmin and Zmax of the cycle counter 5 with the spread of the Correlate SSO 1.
  • Zmin corresponds to the nominal frequency
  • Zmax corresponds to the nominal frequency.
  • the measurement number counter 13 is used to display the first e.g. 16 ignore cycle counts to avoid transients of the measurement signal m.
  • the measuring-number counter 13 is used to determine the time / measurement samples within which the intermediate buffers 6a, 7a stabilize at their max / min values Zmin, Zmax.
  • a watchdog counter (monitoring counter) 1 1 is advantageously provided, which also counts the number of SSO clock cycles and is reset again with the signal edge of the measurement signal m.
  • the watchdog counter 1 1 counts, in the case of a missing measurement signal m, in contrast to the cycle counter 5 only up to its maximum value and then remains at its max. Counter value stand. This makes it easy to determine whether an expected measurement signal is available.
  • the value of this watchdog counter 1 1 can be checked with respect to a valid value range.
  • a suitable hysteresis is preferably used which takes into account a tolerance of the measurement signal m.
  • Alternatively to the above numerical values can z. B.
  • f_mid 55 MHz with + 1-2% spread
  • a measurement frequency of fm 100 kHz
  • a modulation frequency f_mod of z. B. 20 kHz may be provided, whereby meter readings of about 500 can be achieved.
  • FIG. 4 shows a test arrangement 12, in which an independent testing device 14 is formed, with which an electronic device 16, which has an SSO 17 indicated here, can be examined externally.
  • the electronic device 16 may, for. B. as a circuit with a circuit carrier 20, z. B. a PCB or printed circuit board, the SSO 17 and corresponding other components may be formed.
  • the independent test means 17 has z. B. a power terminal 14a, an input 14b for an external measurement signal m2, a ground terminal 14c and a data output 14d for subsequent evaluation via a standard fürtechnik 22, z. B.
  • the test means 14 in this case has an FPGA 24 or other programmable switching device, for. B. an ASIC 24, and further an internal clock 25, in particular oscillator 25, for outputting an internal measurement signal m1, wherein the FPGA 24 optionally via an external switching signal (control signal) S4, which switches a switching device 54, between this internal Measuring signal m1 and the external measuring signal m2 can be switched.
  • an internal clock 25 z. B. an already existing in the system second clock source with a fixed frequency, z. B. from a second oscillator, optionally with frequency division with a PLL z. B. in the FPGA 24 already exists.
  • the z. B. may be formed as a test device with housing, the electronic device 16 z. B. in the final inspection or acceptance in the production to be examined.
  • an output signal S2 can from the output 14d z. B. an oscillator status output signal or a PWM-coded spread signal are output.
  • Switching between the external measuring signal m2 and the internal measuring signal m1 can be done here by additionally checking the internal measuring signal m1 serve, or also the optional use, if no external measuring signal m2 is available.
  • FIG. 5 shows the integration of the method according to the invention in an electronic device 26, which has a circuit carrier 27, e.g. B. a PCB or a printed circuit board and mounted on the circuit substrate 27 has a microcontroller 28, an oscillator 30 with a fixed clock for outputting an internal measurement signal m1, an FPGA 32 or other corresponding device and the SSO 34, wherein the components 28, 30, 32, 34 are formed accordingly as integrated circuits.
  • the FPGA 32 may in this case be constructed in accordance with the FPGA 10 of FIG.
  • On the circuit substrate 27 are further contact surfaces 36, 37, 38 provided for tapping by an external test device 40, to which an evaluation device 42 is connected for a standard strigtechnik.
  • the contact surface 37 serves to supply the measurement signal m from the test device 40 and the contact surface 38 for inputting an initialization signal from the test device 40 for initializing the measurement.
  • the output of the FPGA 32 as a status output, z. B. as a binary signal or PWM signal output.
  • FIG. 6 shows an electronic device 44 which differs from the device 26 from FIG. 5 with otherwise identical or corresponding functionality in that the test device or the test device 40 and the evaluation device 42 from FIG. 5 are already integrated in the FPGA 132, so that the activation and evaluation of the measurement can be carried out directly online at the user, ie later in the field for a current functional check.
  • an output signal S6 are output from the microcontroller 28 to the outside, for. B. via a data bus 29; when used in a vehicle z. B. the in-vehicle CAN bus 29.
  • the FPGA 132 thus outputs the output signal S2, z. B. as an oscillator status signal to the microcontroller 28, which outputs the corresponding output signal S6 to the outside.
  • the FPGA 132 may have a binary status output 31 to directly trigger an externally connected display device, in particular a signal lamp 46, for direct display of a function check, for. B. with lamp control in proper condition.
  • a signal lamp 46 for direct display of a function check, for. B. with lamp control in proper condition.
  • the measuring signal m can be used not only as a reset signal for the FPGA 32 or 132, but as shown also as a clock signal for the microcontroller 28 and optionally further components.
  • Figure 7 shows an implementation in a test and evaluation circuit 52 according to the invention, which is integrated on a semiconductor device. Furthermore, an internal oscillator 53 may be integrated, wherein a switching device 54 switches between an internal measuring signal m1 output by the oscillator 53 and an external measuring signal m2 to be applied if necessary.
  • the SSO signal with the frequency f_sso to be tested is input to an input 50a, the external measurement signal to an input 50b;
  • the switching signal S4 for switching between the internal measuring signal m1 and the external measuring signal m2 can be input via an input 50c; furthermore, an input 5Od for the
  • FIG. 8 shows the test and evaluation circuit 52 according to the invention together with the SSO 1 integrated in a semiconductor component 60, ie. H. as a common integrated circuit 60.
  • the SSO 1 is additionally provided in the integrated circuit.
  • This z. B. only the generated by the oscillator 53 internal measurement signal m1 can be used.
  • the integrated circuit 60 thus has an input terminal 6Od for power supply, an enable input 60a, a clock output 60b, a ground terminal 60c, and an oscillator status output 6Oe for outputting the status output signal S2.
  • the invention is embodied here as an add-on module in an oscillator IC 60.
  • FIG. 9 shows a further embodiment in which the device according to the invention is integrated as a peripheral module in a microcontroller 90.
  • a few conventional devices are initially connected to the internal data bus 91 of the controller 90, in particular an EEPROM 92, a timer / counter or counter 93, an arithmetic logic unit (ALU) 94, an SRAM 95, a program counter 96, a flash program memory 97, an instruction register 98, an instruction decoder 99 for outputting control signals S10, an input output device (IO) 100 , an interrupt unit 101, an analog comparator 102, a control register 103, a status register 104 and a universal serial interface 105, a general purpose register 11 1 and possibly other common facilities of a microcontroller.
  • IO input output device
  • an SSO verification module 110 is additionally provided, which functionally corresponds essentially to the IC 50 from FIG. 7;
  • the internal oscillator 53 can be provided here or else another clock signal present in the microcontroller can be recorded.
  • the SSO clock signal to be examined can be input via an internal SSO of the microcontroller 90 or from an external SSO via a clock input connection 120.
  • FIG. 10 shows an implementation for monitoring the measurement signal m with a "watchdog" -like counter which counts the number of SSO cycles cyclically from A or C and stops at its maximum counter value if it does not return immediately at A or C. is reset. The period from A to C thus forms the measurement period T_m.
  • the counter width in [bit] can be construed as log ⁇ [spread * (f_m-f_mod) + 2 * f_mid * f_R] / [2 * (f_m) 2 ] ⁇ / log (2)
  • the watchdog counter is reset cyclically. If measurement signal m is missing, the watchdog counter runs over. This is recognized and further processed as an error and taken into account in the result or the result output. At time A or C, the watchdog counter reading is checked with respect to a validity range including hysteresis.
  • the curves thus flatten for larger values of R, so a small value of R, preferably between 2 and 7, should be chosen.
  • the measurement frequency f_m is a non-integer multiple of f-mod in order to achieve this. chen that the measuring periods T_m respectively detect different areas of the modulation periods, ie the beginning and end times of the measurement periods T_m are not always in the same phase values of the modulation periods.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

L'invention concerne un procédé et un dispositif de vérification d'un générateur d'impulsions (1) à fréquence modulée, le dispositif comprenant: un dispositif de comptage de cycles (5, 24) pour compter les cycles d'horloge d'un signal d'horloge (f_SSO) du générateur d'impulsions (1, 17, 34) au cours de plusieurs périodes de mesure (T_m) successives qui sont définies notamment par un signal de mesure (m) avec une fréquence de mesure (f_m) et fournir des valeurs de comptage de cycles (z), et un dispositif de comparaison (6, 7, 8) pour recevoir et comparer les valeurs de comptage de cycles (z) entre elles et fournir au moins un signal de sortie (S2, S6) en fonction de la comparaison. Des valeurs maximales et minimales déterminées peuvent notamment être comparées les unes aux autres.
EP09782155A 2008-10-15 2009-08-25 Dispositif et procédé de vérification d'un générateur d'impulsions à fréquence modulée Withdrawn EP2338066A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102008042847A DE102008042847A1 (de) 2008-10-15 2008-10-15 Vorrichtung und Verfahren zur Überprüfung eines frequenzmodulierten Taktgebers
PCT/EP2009/060921 WO2010043439A1 (fr) 2008-10-15 2009-08-25 Dispositif et procédé de vérification d'un générateur d'impulsions à fréquence modulée

Publications (1)

Publication Number Publication Date
EP2338066A1 true EP2338066A1 (fr) 2011-06-29

Family

ID=41402502

Family Applications (1)

Application Number Title Priority Date Filing Date
EP09782155A Withdrawn EP2338066A1 (fr) 2008-10-15 2009-08-25 Dispositif et procédé de vérification d'un générateur d'impulsions à fréquence modulée

Country Status (5)

Country Link
US (1) US8564379B2 (fr)
EP (1) EP2338066A1 (fr)
JP (1) JP5579186B2 (fr)
DE (1) DE102008042847A1 (fr)
WO (1) WO2010043439A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012156676A (ja) * 2011-01-25 2012-08-16 Hitachi Ltd 周波数判定回路および半導体装置
US8542069B2 (en) * 2011-09-23 2013-09-24 Infineon Technologies Ag Method for trimming an adjustable oscillator to match a CAN-bus and a CAN-bus communication controller
CN111289796B (zh) * 2020-03-20 2021-03-30 电子科技大学 一种高比例可再生能源电力系统次同步振荡的检测方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5506545A (en) * 1993-11-09 1996-04-09 Gte Government Systems Corporation Electronic apparatus having low radio frequency interference from controlled excursion noise-modulated system clock signal
US5748670A (en) * 1995-05-25 1998-05-05 Zilog, Inc. Method of demodulating chirp spread spectrum
JP2003207544A (ja) * 2002-01-15 2003-07-25 Mitsubishi Electric Corp Ｉｃ内蔵発振回路のテスト装置
JP2003324350A (ja) * 2002-05-02 2003-11-14 Ricoh Co Ltd 画像形成装置
JP4373267B2 (ja) * 2003-07-09 2009-11-25 株式会社ルネサステクノロジ スプレッドスペクトラムクロック発生器及びそれを用いた集積回路装置
JP4698136B2 (ja) 2003-09-11 2011-06-08 富士通セミコンダクター株式会社 帯域分布検査装置、および帯域分布検査方法
DE102005013593A1 (de) 2005-03-24 2006-09-28 Robert Bosch Gmbh Verfahren zur Dämpfung einer Hochfrequenzabstrahlung eines getakteten Systems
JP4819400B2 (ja) * 2005-05-26 2011-11-24 株式会社リコー クロック生成回路のテスト回路
JP4726585B2 (ja) 2005-09-16 2011-07-20 株式会社リコー Ｅｍｉ低減動作テスト回路とｅｍｉ低減動作テスト方法および半導体装置と電子機器
CN101842986A (zh) * 2007-11-02 2010-09-22 松下电器产业株式会社 扩频时钟产生装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2010043439A1 *

Also Published As

Publication number Publication date
DE102008042847A1 (de) 2010-04-22
WO2010043439A1 (fr) 2010-04-22
US20110140740A1 (en) 2011-06-16
US8564379B2 (en) 2013-10-22
JP2012506033A (ja) 2012-03-08
JP5579186B2 (ja) 2014-08-27

Similar Documents

Publication Publication Date Title
DE2946081A1 (de) Anordnung zur ueberwachung der funktion eines programmierbaren elektronischen schaltkreises
DE102018124351B4 (de) Echtzeit-steigungssteuerungsvorrichtung für einen spannungsregler und verfahren zum betreiben dieser vorrichtung
EP2526431B1 (fr) Procédé et dispositif de contrôle d'un signal de fréquence
DE102010000953A1 (de) System und Verfahren zum Testen einer Leistungsversorgung
EP1915631A1 (fr) Procede et systeme pour controler une premiere valeur de tension
DE4436372A1 (de) Schaltungsanordnung für ein elektronisches Kraftfahrzeug-Regelungssystem
DE102012206870A1 (de) Verfahren und Vorrichtung zum Erkennen einer Manipulation an einer elektrischen Leitung
EP2338066A1 (fr) Dispositif et procédé de vérification d'un générateur d'impulsions à fréquence modulée
DE19808349C2 (de) Sensor für physikalische Parameter
DE102013226429A1 (de) Vorrichtung und Verfahren zur Überwachung eines Zeitgebers
DE102007027070A1 (de) Elektronische Vorrichtung und Verfahren zur chipintegrierten Messung von Jitter
DE3714325A1 (de) Datenschutzvorrichtung fuer einen computer einer brennkraftmaschinensteuerung
WO2018206146A2 (fr) Procédé pour le contrôle automatisé assisté par ordinateur de descriptions
DE102007007339A1 (de) Verfahren und Vorrichtung zum Lokalisieren von Fehlern auf elektronischen Leiterplatten
DE3731097C2 (de) Schaltungsanordnung zur Überwachung einer von zwei Mikroprozessoren gesteuerten Einrichtung, insbesondere einer Kraftfahrzeug-Elektronik
DE3006599C2 (de) Schaltungsanordnung zur Erkennung einer Überschreitung einer vorgebbaren Abweichung der Frequenz eines Gebersignals von einer Sollfrequenz
DE102015210547A1 (de) Festperiodensignalüberwachungsschaltkreis und Verbrauchersteuerungssicherheitssignalerzeugungsschaltkreis
DE102019212970A1 (de) Verfahren und Anordnung zum Erfassen einer durch ein Bordnetz eines Kraftfahrzeugs hervorgerufenen elektromagnetischen Störung
EP2936119B1 (fr) Dispositif de mesure optique
DE102007030589A1 (de) Verfahren und Schaltung zur mehrkanaligen Fehlerbewertung von Mess- oder Prozessgrößen
DE102021106588B4 (de) Überwachungsvorrichtung für einen Prozessortakt mit Unterdrückung von Falschbewertungen aufgrund von Aliasing-Effekten
DE3404019C2 (fr)
DE2903383B1 (de) Testgeraet fuer addressierbare digitale Schaltungen
DE10344004A1 (de) Verfahren und Vorrichtung zur Erzeugung einer internen Zeitbasis für eine Diagnosefunktion für einen Endstufenbaustein
DE102008042894A1 (de) Verfahren und Vorrichtung zum Testen eines Rechnerkerns in einer mindestens zwei Rechnerkerne aufweisenden Recheneinheit

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20110516

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO SE SI SK SM TR

AX Request for extension of the european patent

Extension state: AL BA RS

DAX Request for extension of the european patent (deleted)
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20160301