EP2302703A2 - Procédé de fabrication d'un dispositif électroluminescent semi-conducteur et dispositif électroluminescent semi-conducteur - Google Patents

Procédé de fabrication d'un dispositif électroluminescent semi-conducteur et dispositif électroluminescent semi-conducteur Download PDF

Info

Publication number
EP2302703A2
EP2302703A2 EP10154638A EP10154638A EP2302703A2 EP 2302703 A2 EP2302703 A2 EP 2302703A2 EP 10154638 A EP10154638 A EP 10154638A EP 10154638 A EP10154638 A EP 10154638A EP 2302703 A2 EP2302703 A2 EP 2302703A2
Authority
EP
European Patent Office
Prior art keywords
bonding metal
bonded
major surface
layer
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP10154638A
Other languages
German (de)
English (en)
Other versions
EP2302703A3 (fr
Inventor
Yoshiaki Sugizaki
Akihiro Kojima
Masanobu Ando
Kazuyoshi Furukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of EP2302703A2 publication Critical patent/EP2302703A2/fr
Publication of EP2302703A3 publication Critical patent/EP2302703A3/fr
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape

Definitions

  • Nitride-based LEDs (light-emitting diodes), for example, can be manufactured by epitaxial growth on a sapphire substrate. Thus far, removing the sapphire substrate has been performed in view of increasing light extraction efficiency. In this case, since LED epitaxial layers are very thin, supporting the LED epitaxial layers with a supporting substrate before removing the sapphire substrate has been performed.
  • USP. 7,256,483 discloses a method in which a sapphire substrate and LED epitaxial layers in a wafer state undergo dicing to be fragment, each resulting LED chip is mounted on a supporting substrate, and then the sapphire substrate is removed for each chip by the laser lift-off method.
  • the method since mounting on the supporting substrate and removing the sapphire substrate are performed for each fragment chip, the method is inefficient.
  • a method for manufacturing a semiconductor light-emitting device including forming a semiconductor layer including a light-emitting layer on a major surface of a temporary substrate; forming a first interconnect layer on a second major surface side of the semiconductor layer on a side opposite to a first major surface in contact with the major surface of the temporary substrate; forming a trench penetrating through the first interconnect layer and the semiconductor layer to reach the temporary substrate and dividing the semiconductor layer and the first interconnect layer into a plurality of chips by the trench; forming a second interconnect layer on a major surface of a supporting substrate; opposing the major surface of the temporary substrate and the major surface of the supporting substrate to each other and bonding collectively each divided portion of the first interconnect layer of a plurality of chips to be bonded not adjacent to each other out of the plurality of chips on the temporary substrate, to the second interconnect layer; irradiating interfaces between the first major surfaces of the chips to be bonded to the second interconnect layer and the
  • a semiconductor light-emitting device including: a chip including: a semiconductor layer including: a light-emitting layer; a first major surface extracting light emitted from the light-emitting layer; and a second major surface on a side opposite to the first major surface; and a first interconnect layer provided on the second major surface side of the semiconductor layer; a second interconnect layer bonded to the first interconnect layer; and a supporting substrate supporting the chip bonded to the second interconnect layer formed on a major surface of the supporting substrate and having a larger planar size than the chip, the chip having been selected from chips not adjacent to each other among a plurality of chips formed away from each other on a temporary substrate, having been bonded to the second interconnect layer in a state of being supported with the temporary substrate, and having been transferred to the supporting substrate by separating the temporary substrate by irradiating an interface between the first major surface of the chip and the temporary substrate with laser light.
  • a semiconductor light-emitting device including: a chip including: a semiconductor layer including: a light-emitting layer; a first major surface extracting light emitted from the light-emitting layer; and a second major surface on a side opposite to the first major surface; and a first interconnect layer provided on the second major surface side of the semiconductor layer; a second interconnect layer bonded to the first interconnect layer; and a supporting substrate supporting the chip bonded to the second interconnect layer formed on a major surface of the supporting substrate and having a larger planar size than the chip
  • the semiconductor layer includes: a first semiconductor layer including the light-emitting layer; and a second semiconductor layer including the first major surface and having the first semiconductor layer stacked on a side opposite to the first major surface
  • the first interconnect layer includes: a first bonding metal electrically connected to the first semiconductor layer; a second bonding metal electrically connected to the second semiconductor layer; and a first insulating film provided between the first bonding metal
  • FIG. 1 is a schematic cross-sectional view of a semiconductor light-emitting device according to an embodiment of the invention.
  • FIG. 2 is a schematic view illustrating a planar layout of the main components of the semiconductor light-emitting device.
  • a semiconductor light-emitting device has a structure in which a chip 10 including a light-emitting layer is mounted on a supporting substrate 31 that has a larger planar size than the chip 10.
  • the chip 10 includes semiconductor layers 11 and 12 and an interconnect layer.
  • the semiconductor layer 12 has a structure in which a light-emitting layer (or active layer) is placed between a p-type cladding layer and an n-type cladding layer.
  • the semiconductor layer 11 is n-type, for example, and functions as a lateral-direction pathway of a current.
  • the conductivity type of the semiconductor layer 11 is not limited to n-type but may be p-type.
  • a first major surface of the semiconductor layer 11 functions as a light extraction surface 15.
  • the semiconductor layer 12 is provided on a second major surface on the side opposite to the light extraction surface 15.
  • the semiconductor layer 12 has a smaller planar size than the semiconductor layer 11.
  • the semiconductor layer 12 is formed at the center in the planar direction of the second major surface of the semiconductor layer 11.
  • a p-side electrode 14, an n-side electrode 13, a p-side bonding metal 22, an n-side bonding metal 21, and insulating films 16 and 25 that form a first interconnect layer are provided on a surface of the chip 10 opposite to the light extraction surface 15.
  • the n-side electrode 13 is formed on a portion of the second major surface of the semiconductor layer 11 on which the semiconductor layer 12 is not provided.
  • the p-side electrode 14 is formed on a surface of the semiconductor layer 12 on the side opposite to the surface in contact with the semiconductor layer 11.
  • the n-side bonding metal 21 is provided on a surface of the n-side electrode 13 on the side opposite to the surface in contact with the semiconductor layer 11.
  • the n-side bonding metal 21 is formed so that an end on the side opposite to another end in contact with the n-side electrode 13 may be larger in planar size than the other end.
  • the p-side bonding metal 22 is provided on a surface of the p-side electrode 14 opposite to the surface in contact with the semiconductor layer 12.
  • the p-side bonding metal 22 is formed in a planar shape of a square island, for example, and the n-side bonding metal 21 is formed in a closed planar shape of a frame that surrounds continuously the periphery of the p-side bonding metal 22.
  • the insulating film 16 is provided between the n-side electrode 13 and the p-side electrode 14, and thus the n-side electrode 13 and the p-side electrode 14 are electrically insulated from each other.
  • the insulating film 16 covers the semiconductor layers 11 and 12 between the n-side electrode 13 and the p-side electrode 14.
  • the insulating film 16 is a silicon oxide film, for example.
  • the insulating film 25 is provided between the n-side bonding metal 21 and the p-side bonding metal 22, and thus the n-side bonding metal 21 and the p-side bonding metal 22 are electrically insulated from each other.
  • the insulating film 25 covers the insulating film 16, a part of the surface of the n-side electrode 13, and a part of the surface of the p-side electrode 14.
  • the insulating film 25 is a silicon oxide film, for example.
  • a resin material such as polyimide may be used as the insulating film 25.
  • the semiconductor layer 12 and the p-side electrode 14 may be formed so as to creep under the n-side bonding metal 21 via the insulating film 25.
  • Such structure can make the area of the semiconductor layer 12, i.e., a light-emitting unit larger.
  • bonding metals 32 and 33 and an insulating film 35 are formed as a second interconnect layer.
  • the bonding metals 32 and 33 are not covered with the insulating film 35 but are exposed. Portions of the major surface of the supporting substrate 31 other than the bonding metals 32 and 33 are covered with the insulating film 35.
  • the n-side bonding metal 21 is bonded to the bonding metal 32, and the p-side bonding metal 22 is bonded to the bonding metal 33.
  • a surface of the chip 10 on the side opposite to the light extraction surface 15 is a bonding surface to the second interconnect layer on the supporting substrate 31 side.
  • the n-side bonding metal 21, the p-side bonding metal 22, and the insulating film 25 are exposed at the bonding surface.
  • the bonding surface of the chip 10 that includes the n-side bonding metal 21, the p-side bonding metal 22, and the insulating film 25 is flat over the entire bonding surface.
  • the bonding surface of the second interconnect layer that includes the bonding metals 32 and 33 and the insulating film 35 to the chip 10 is also flat over the entire bonding surface. Therefore, the chip 10 and the second interconnect layer formed on the supporting substrate 31 are bonded at their flat surfaces.
  • Copper, gold, nickel, silver, and the like may be used as the material of the n-side electrode 13, the p-side electrode 14, the n-side bonding metal 21, the p-side bonding metal 22, and the bonding metals 32 and 33 on the supporting substrate 31 side.
  • copper which has a good thermal conductivity and a high migration tolerance, is more preferable.
  • the n-side bonding metal 21 and the bonding metal 32 are preferably a same kind of metal in terms of increasing the bonding strength.
  • the p-side bonding metal 22 and the bonding metal 33 are preferably a same kind of metal.
  • Through-vias are formed in the supporting substrate 31, and a contact electrode 41 is provided in the through-via.
  • the through-vias are formed from the back surface of the supporting substrate 31 on the side opposite to the major surface thereof to reach the bonding metals 32 and 33, and the through-vias connect the bonding metals 32 and 33 and the back surface of the supporting substrate 31.
  • the contact electrodes 41 provided in the through-vias are connected to the bonding metals 32 and 33.
  • a pad 42 connected to the contact electrode 41 is formed on the back surface of the supporting substrate 31.
  • an insulating film is formed on the inner wall of the through-via, and an insulating film is interposed also between the pad 42 and the supporting substrate 31.
  • the semiconductor layer 11 is electrically connected to some pads 42 formed on the back surface of the supporting substrate 31, via the n-side electrode 13, the n-side bonding metal 21, the bonding metal 32, and the contact electrode 41.
  • the semiconductor layer 12 is electrically connected to the other pads 42 formed on the back surface of the supporting substrate 31, via the p-side electrode 14, the p-side bonding metal 22, the bonding metal 33, and the contact electrode 41.
  • a current is supplied to the semiconductor layers 11 and 12 via these conductive materials, and thereby the light-emitting layer emits light.
  • a third interconnect layer may be formed below the bonding metal 32 and the bonding metal 33, i.e., on the supporting substrate 31 side thereof. Forming the third interconnect layer enables the contact electrode 41 to be placed at any position.
  • the contact electrode 41 may be formed on the outside of the region on which the semiconductor chip 10 is mounted, and thereby the pitch of the pad 42 can be widened, which facilitates mounting on a circuit substrate.
  • the side surface of the chip 10 is covered with a protective film 46 having insulating properties.
  • the protective film 46 covers also the insulating film 35 on the major surface of the supporting substrate 31.
  • a phosphor layer 47 is provided on the light extraction surface 15 of the chip 10.
  • the phosphor layer 47 can absorb the light from the light-emitting layer and emit a wavelength-converted light. Accordingly, a mixed light of the light from the light-emitting layer and the wavelength-converted light at the phosphor layer 47 can be emitted.
  • the light-emitting layer is of nitride type
  • blue light from the light-emitting layer and yellow light that is a wavelength-converted light at the yellow phosphor layer 47 for example, can be mixed to obtain the white, the warm white, and the like as a mixed color.
  • the phosphor layer 47 is provided also in the region opposed to the side surface of the chip 10 to cover the side surface of the chip 10 via the protective film 46.
  • the protective film 46 is a film transparent to the light emitted by the light-emitting layer, such as a silicon oxide film. Since the light emitted from the side surface of the chip 10 also enters the phosphor layer 47, the brightness can be increased,
  • the chip 10 described above is formed first on a temporary substrate that is different from the supporting substrate 31, as described below.
  • a plurality of chips 10 are formed on the wafer-shaped temporary substrate.
  • One selected from among them as a chip to be bonded is bonded to the bonding metals 32 and 33 while being supported with the temporary substrate, and in this condition only the chip to be bonded is irradiated with laser light. Thereby, only the chip to be bonded is removed from the temporary substrate and thus transferred to the supporting substrate 31.
  • a semiconductor layer 11 is formed on a major surface of a temporary substrate 1, and a semiconductor layer 12 including a light-emitting layer is formed on a second major surface of the semiconductor layer 11 on the side opposite to the first major surface that is in contact with the temporary substrate 1.
  • the semiconductor layers 11 and 12 may be formed by crystal growth on a sapphire substrate.
  • the semiconductor layer 12 is patterned and is selectively left on the second major surface of the semiconductor layer 11.
  • n-side electrodes 13 are selectively formed on the second major surface of the semiconductor layer (n type semiconductor layer) 11, and p-side electrodes 14 are provided each on a face of the semiconductor layer (p type semiconductor layer) 12 on the side opposite to the surface in contact with the semiconductor layer 11.
  • An insulating film 16 is formed between the semiconductor layer 12 and the n-side electrode 13, and between the p-side electrode 14 and the n-side electrode 13, Further, as illustrated in FIG. 3C , an insulating film 25 that covers the p-side electrode 14, the n-side electrode 13, and the insulating film 16 is formed, and the insulating film 25 is planarized.
  • an opening that reaches the p-side electrode 14, an opening that reaches the n-side electrode 13, an opening for forming a p-side bonding metal 22 itself, and an opening for forming an n-side bonding metal 21 itself are formed in the insulating film 25.
  • a not-illustrated seed metal is formed in a region to which the p-side electrode 14, the n-side electrode 13, and the insulating film 25 are exposed, and electrolytic plating using the seed metal as a current pathway is performed.
  • a metal film 20 that covers the p-side electrode 14, the n-side electrode 13, and the insulating film 25 is formed.
  • a portion connected to the n-side electrode 13 forms the n-side bonding metal 21
  • a portion connected to the p-side electrode 14 forms the p-side bonding metal 22.
  • the metal film 20 is polished by, for example, CMP (chemical mechanical polishing) until the surface of the insulating film 25 is exposed.
  • CMP chemical mechanical polishing
  • a trench 26 is formed in the semiconductor layer 11 and the first interconnect layer to divide the above-described structure formed on the temporary substrate 1 into a plurality of chips 10.
  • the trench 26 penetrates through the insulating film 25 between adjacent n-side bonding metals 21, the insulating film 16s between adjacent n-side electrodes 13, and the semiconductor layer 11 to reach the major surface of the temporary substrate 1.
  • the trench 26 is formed by, for example, RIE (reactive ion etching) using a not-illustrated mask.
  • the trench 26 may be formed by the laser ablation method.
  • the trench 26 is formed in a lattice shape on the temporary substrate 1, for example.
  • the n-side bonding metal 21 in each chip 10 becomes in a closed planar shape of a frame that surrounds continuously the periphery of the island-shaped p-side bonding metal 22, as illustrated in FIG. 2 .
  • FIG. 7A illustrates a schematic plan view of this first wafer W1.
  • the black squares represent the chips 10
  • the white lines between the chips 10 represent the trench 26 described above.
  • the second wafer W2 has a structure in which a second interconnect layer is formed on the major surface of the supporting substrate 31, as illustrated in FIG. 5A .
  • the supporting substrate 31 is a silicon substrate or a glass substrate, for example.
  • the second interconnect layer includes: an insulating film 35 that covers the major surface of the supporting substrate 31; and bonding metals 32 and 33 that are selectively formed on the surface of the insulating film 35.
  • the insulating film 35 is interposed also between the bonding metal 32 and the bonding metal 33; therefore, the bonding metal 32 and the bonding metal 33 are insulated from each other by the insulating film 35.
  • the bonding metal 33 is formed in an island shape like the p-side bonding metal 22 of the first wafer W1, and the bonding metal 32 is formed in a closed planar shape of a frame that surrounds continuously the periphery of the bonding metal 33, like the n-side bonding metal 21 of the first wafer W1.
  • the surfaces of the bonding metals 32 and 33 are exposed on the insulating film 35, and the surfaces of these bonding metals 32 and 33 and the surface of the insulating film 35 between the bonding metals 32 and 33 are planarized.
  • a process of transferring the chip 10 from the temporary substrate 1 to the supporting substrate 31 will now be described.
  • a chip to be bonded 10a out of the plurality of chips 10 on the temporary substrate 1 is transferred to the supporting substrate 31.
  • FIG. 5A illustrates a state in which: the major surface of the temporary substrate 1 and the major surface of the supporting substrate 31 are opposed to each other; and the first wafer W1 and the second wafer W2 are position-adjusted.
  • a n-side bonding metal 21 of the chip to be bonded 10a is opposed to the bonding metal 32 of the second wafer W2, and a p-side bonding metal 22 of the chip to be bonded 10a is opposed to the bonding metal 33 of the second wafer W2.
  • the bonding metal 32 and the n-side bonding metal 21 are bonded, and the bonding metal 33 and the p-side bonding metal 22 are bonded.
  • the metals are bonded by heating while applying suppress strength on the bonding surfaces.
  • the materials are heated to 300°C or higher.
  • the bonding surfaces may be cleaned to be activated and then bonded at normal temperature only by suppress strength, without heating.
  • the bonding surfaces may be cleaned to be activated also in the case where heating is performed, which can increase the bonding strength.
  • a high bonding strength is obtained.
  • the bonding surface of the chip to be bonded 10a including the n-side bonding metal 21, the p-side bonding metal 22, and the insulating film 25 is flat over the entire bonding surface, and the bonding surface of the second wafer W2 including the bonding metals 32 and 33 and the insulating film 35 is also flat over the entire bonding surface. Therefore, the chip to be bonded 10a and the second wafer W2 are bonded at their flat surfaces.
  • the surface of the second wafer W2 opposed to a chip not to be bonded 10b may be made low in a state where the chip to be bonded 10a is bonded to the second wafer W2. This creates a gap 27 between the chip not to be bonded 10b and the second wafer W2, and thereby the chip not to be bonded 10b is not bonded to the second wafer W2.
  • the temporary substrate 1 is stripped by using the laser lift-off method, for example.
  • the laser light is applied toward the semiconductor layer 11 of the chip to be bonded 10a from the back surface side of the temporary substrate 1 opposite to the major surface on which the semiconductor layer 11 is formed,.
  • the laser light has transmission properties to the temporary substrate 1, and has a wavelength at which the laser light is absorbed in the semiconductor layer 11.
  • the semiconductor layer 11 near the interface absorbs the energy of the laser light to be decomposed.
  • the semiconductor layer 11 is GaN
  • it is decomposed into Ga and nitrogen gas.
  • the chip to be bonded 10a is stably fixed onto the supporting substrate 31, which is a rigid body such as silicon or glass, by bonding at the flat surfaces. Further, there is a space at the outer periphery of the chip to be bonded 10a, which forms a way out for the gas mentioned above. Therefore, the chip 10a bonded can be prevented from being broken or crushed by the shock caused by the gas mentioned above.
  • the semiconductor layer 11 that is a GaN layer is epitaxially grown on the temporary substrate 1 that is a sapphire substrate, compressive stresses are easily accumulated in the semiconductor layer 11 that is a GaN layer, due to the difference in coefficient of thermal expansion between the sapphire and the GaN.
  • the temporary substrate 1 is separated from the semiconductor layer 11 and the semiconductor layer 11 is released from the restriction by the temporary substrate 1, then the compressive stresses accumulated in the semiconductor layer 11 are released and the semiconductor layer 11 tends to expand rapidly in the planar direction.
  • the n-side bonding metal 21 and the bonding metal 32 that form a bonding section of the chip 10 on the edge side are formed in a planar shape of a frame, as described above. Therefore, the edge side of the chip 10 is fixed to the supporting substrate 31 evenly without bias in the direction along the edge portion. Accordingly, even if an expansion occurs in the planar direction of the semiconductor layer 11, the chip 10 can be firmly fixed to the supporting substrate 31 in all directions of the edge portion of the chip. Consequently, a large amount of stress acting on the chip 10 locally can be suppressed, and thus the chip 10 can be prevented from getting damaged.
  • n-side electrode 13 and the n-side bonding metal 21 are formed evenly in the direction along the edge portion of the chip 10, a current can be supplied evenly in the planar direction of the chip 10, which serves to improve the light-emission efficiency.
  • the second wafer W2 and the first wafer W1 are separated, as illustrated in FIG. 5C . Thereby, the chips to be bonded 10a are transferred from the temporary substrate 1 to the supporting substrate 31.
  • Chips not to be bonded 10b are separated from the chips to be bonded 10a by the trench 26 and are not bonded to the second wafer W2. Further, the chips not to be bonded 10b are not irradiated with laser light, and the semiconductor layers 11 thereof and the temporary substrate 1 are not separated. Therefore, the chips not to be bonded 10b are not transferred to the second wafer W2 but are left on the temporary substrate 1. The chips 10b left on the temporary substrate 1 are transferred to another supporting substrate 31 by a method like the above.
  • All chips 10 on the temporary substrate 1 illustrated in FIG. 7A are transferred to different supporting substrates 31 multiple courses.
  • the chips 10 on the temporary substrate 1 are transferred to four different supporting substrates 31 by four courses, for example.
  • FIG. 7B illustrates the first wafer W1 after the first chip transfer process.
  • One fourth of all the chips 10 in FIG. 7A have been transferred from the temporary substrate 1 to a supporting substrate 31 as chips to be bonded.
  • a plurality of chips 10 that are not adjacent to each other and are placed at regular intervals on the temporary substrate 1 are collectively bonded to the second interconnect layer of the second wafer W2.
  • the chips 10 bonded to the second interconnect layer are irradiated with laser light, and the temporary substrate 1 is removed from the second wafer W2.
  • the plurality of chips 10 can be collectively transferred from the temporary substrate 1 to the supporting substrate 31.
  • bonding surfaces that includes the bonding metals 32 and 33 are laid out at a pitch corresponding to the chips to be bonded 10a.
  • the whitely-drawn portions of the first wafer W1 illustrated in FIG. 7B from which chips have been removed correspond to the layout of portions of the second wafer W2 where the bonding metals 32 and 33 are formed. Further, the whitely-drawn portions correspond to the layout of the chips 10 in the second wafer W2. Therefore, the arrangement pitch of the chips 10 that are transferred onto the supporting substrate 31 is greater than the arrangement pitch of all the chips 10 that are formed on the temporary substrate 1 illustrated in FIG. 7A .
  • the fragmentation can be performed while keeping the planar size of the supporting substrate 31 larger than the planar size of the chips 10.
  • the light-emitting device thus fragmentized illustrated in FIG. 1
  • the supporting substrate 31 is large, heat radiation properties are high.
  • the reliability and the lifetime of light-emitting device can be improved.
  • FIG. 8A illustrates the first wafer W1 after this second chip transfer.
  • a plurality of chips 10 placed at regular intervals and at an arrangement pitch greater than the arrangement pitch of all the chips 10 that are initially formed on the temporary substrate 1 are collectively bonded to the second interconnect layer of the second wafer W2 as chips to be bonded.
  • the chips 10 bonded to the second interconnect layer are irradiated with laser light, and the temporary substrate 1 is removed from the second wafer W2.
  • the plurality of chips 10 can be collectively transferred from the temporary substrate 1 to the supporting substrate 31.
  • FIG. 8B illustrates the first wafer W1 after this third chip transfer.
  • a plurality of chips 10 placed at regular intervals and at an arrangement pitch greater than the arrangement pitch of all the chips 10 that are initially formed on the temporary substrate 1 are collectively bonded to the second interconnect layer of the second wafer W2 as chips to be bonded.
  • the chips 10 bonded to the second interconnect layer are irradiated with laser light, and the temporary substrate 1 is removed from the second wafer W2.
  • the plurality of chips 10 can be collectively transferred from the temporary substrate 1 to the supporting substrate 31.
  • all the remaining chips 10 illustrated in FIG. 8B are transferred to yet another supporting substrate 31.
  • a plurality of chips 10 placed at regular intervals and at an arrangement pitch greater than the arrangement pitch of all the chips 10 that are initially formed on the temporary substrate 1 are collectively bonded to the second interconnect layer of the second wafer W2 as chips to be bonded.
  • the chips 10 bonded to the second interconnect layer are irradiated with laser light, and the temporary substrate 1 is removed from the second wafer W2.
  • the plurality of chips 10 can be collectively transferred from the temporary substrate 1 to the supporting substrate 31.
  • a plurality of chips 10 can be collectively transferred from the temporary substrate 1 to the supporting substrate 31, and thus this embodiment is efficient. Furthermore, since the chips 10 are transferred to the supporting substrate 31 at a pitch greater than that of all the chips 10 that are initially formed on the temporary substrate 1, the planar size of the supporting substrate 31 can be made larger than the planar size of the chips 10. This facilitates mounting and heat radiation. Since the arrangement pitch of the chips 10 that are initially formed on the temporary substrate 1 is allowed to be small, there is no need to reduce the number of chips 10 obtainable from one first wafer W1.
  • the selected ones from the chips 10 on the temporary substrate 1 that are to be bonded are transferred to the supporting substrate 31.
  • chips 10 located at regular intervals over the entire surface of the temporary substrate 1 may be selected as chips to be bonded, and thereby the chips 10 can be arranged uniformly without uneven distribution over the entire surface of the second wafer W2.
  • the second wafer W2 can be utilized efficiently without wastage.
  • the temporary substrate 1 After the temporary substrate 1 is removed, substances that are generated by the decomposition during the laser lift-off and remain on the light extraction surface 15 of the chip 10 (for example, Ga) are removed by etching. Then, as illustrated in FIG. 6A , the side surface of the chip 10 is covered with a protective film 46. After that, concaves and convexes are formed on the surface of the light extraction surface 15 of the chip 10 to increase light extracting efficiency, as necessary.
  • a phosphor layer 47 is formed on the supporting substrate 31 so as to cover the light extraction surface 15 and the side surface of the chip 10. Since there is no temporary substrate 1 between the light extraction surface 15 and the phosphor layer 47, the light extraction efficiency can be increased. Furthermore, since the phosphor layer 47 is provided also in the region opposed to the side surface of the chip 10, the light emitted from the side surface of the chip 10 also can be used, by using a film transparent to the light emitted by the light-emitting layer (for example, a silicon oxide film) as the protective film 46.
  • a film transparent to the light emitted by the light-emitting layer for example, a silicon oxide film
  • the contact electrode 41 and the pad 42 illustrated in FIG. 1 and the like are formed. Then, portions of the supporting substrate 31 on the outside of the region to which the chip 10 is bonded are cut off. The cut-off lines are formed in a lattice form on the wafer-shaped supporting substrate 31. Thereby, the fragmentized semiconductor light-emitting device illustrated in FIG. 1 is obtained.
  • a third interconnect layer may be formed below the bonding metal 32 and the bonding metal 33, i.e., on the supporting substrate 31 side thereof. Forming the third interconnect layer enables the contact electrode 41 to be placed at any position.
  • the contact electrodes 41 may be formed on the outside of the region on which the semiconductor chip 10 is mounted, and thereby the pitch of the pad 42 can be widened, which facilitates mounting on a circuit substrate.
  • the third interconnect layer may be formed on the undersurface of the supporting substrate 31. In this case, after the contact electrodes 41 are formed below the bonding metals 32 and 33, a structure, which the third interconnect layer electrically connected to the contact electrodes 41 on the under side of the supporting substrate 31 is wire-connected to the pads 42, is obtained.
  • forming the semiconductor layers, the electrodes, the insulating films, and the bonding metals in the first wafer W1 is performed collectively in a wafer state, and forming the bonding metals and the insulating film in the second wafer W2 also is performed collectively in a wafer state. Furthermore, a plurality of chips 10 are collectively transferred from the temporary substrate 1 to the supporting substrate 31. That is, the processes described above before dicing are performed collectively in a wafer state. Therefore, the production is possible at low cost.
  • the first wafer W1 may be processed before or after the second wafer W2.
  • the first wafer W1 and the second wafer W2 may be concurrently processed.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)
  • Led Device Packages (AREA)
EP10154638.0A 2009-09-25 2010-02-25 Procédé de fabrication d'un dispositif électroluminescent semi-conducteur et dispositif électroluminescent semi-conducteur Withdrawn EP2302703A3 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009220435A JP5534763B2 (ja) 2009-09-25 2009-09-25 半導体発光装置の製造方法及び半導体発光装置

Publications (2)

Publication Number Publication Date
EP2302703A2 true EP2302703A2 (fr) 2011-03-30
EP2302703A3 EP2302703A3 (fr) 2014-04-30

Family

ID=43432095

Family Applications (1)

Application Number Title Priority Date Filing Date
EP10154638.0A Withdrawn EP2302703A3 (fr) 2009-09-25 2010-02-25 Procédé de fabrication d'un dispositif électroluminescent semi-conducteur et dispositif électroluminescent semi-conducteur

Country Status (4)

Country Link
US (1) US8367523B2 (fr)
EP (1) EP2302703A3 (fr)
JP (1) JP5534763B2 (fr)
TW (1) TWI419380B (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012130643A1 (fr) * 2011-03-31 2012-10-04 Osram Opto Semiconductors Gmbh Procédé de séparation d'un assemblage de composants
CN109923679A (zh) * 2016-09-22 2019-06-21 奈克斯沃夫有限公司 用于将多个晶种基质设置在载体元件上的方法和带有晶种基质的载体元件

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4724222B2 (ja) 2008-12-12 2011-07-13 株式会社東芝 発光装置の製造方法
JP2012089828A (ja) * 2010-09-22 2012-05-10 Toshiba Corp 半導体装置の製造方法
JP5537446B2 (ja) 2011-01-14 2014-07-02 株式会社東芝 発光装置、発光モジュール、発光装置の製造方法
JP5603793B2 (ja) 2011-02-09 2014-10-08 株式会社東芝 半導体発光装置
JP5603813B2 (ja) 2011-03-15 2014-10-08 株式会社東芝 半導体発光装置及び発光装置
JP5535114B2 (ja) 2011-03-25 2014-07-02 株式会社東芝 発光装置、発光モジュール、発光装置の製造方法
JP5023229B1 (ja) * 2011-04-27 2012-09-12 株式会社東芝 半導体発光素子の製造方法
JP5642623B2 (ja) 2011-05-17 2014-12-17 株式会社東芝 半導体発光装置
CN107706279B (zh) * 2011-06-01 2020-10-30 亮锐控股有限公司 发光器件以及将发光器件附着到支撑衬底的方法
KR20140034262A (ko) * 2011-06-01 2014-03-19 코닌클리케 필립스 엔.브이. 지지 기판에 접합된 발광 디바이스
JP5662277B2 (ja) 2011-08-08 2015-01-28 株式会社東芝 半導体発光装置及び発光モジュール
US8754424B2 (en) 2011-08-29 2014-06-17 Micron Technology, Inc. Discontinuous patterned bonds for semiconductor devices and associated systems and methods
JP2013065726A (ja) 2011-09-16 2013-04-11 Toshiba Corp 半導体発光装置及びその製造方法
JP5725430B2 (ja) * 2011-10-18 2015-05-27 富士電機株式会社 固相接合ウエハの支持基板の剥離方法および半導体装置の製造方法
JP5710532B2 (ja) 2012-03-26 2015-04-30 株式会社東芝 半導体発光装置及びその製造方法
EP2831930B1 (fr) 2012-03-30 2018-09-19 Lumileds Holding B.V. Dispositif électroluminescent semi-conducteur scellé et procédé de fabrication correspondant
FR2992466A1 (fr) * 2012-06-22 2013-12-27 Soitec Silicon On Insulator Procede de realisation de contact pour led et structure resultante
JP6214968B2 (ja) * 2012-08-27 2017-10-18 シチズン時計株式会社 光デバイス
JP2014150196A (ja) * 2013-02-01 2014-08-21 Toshiba Corp 半導体発光装置およびその製造方法
CN109802014B (zh) 2013-07-05 2022-05-31 晶元光电股份有限公司 发光元件及其制造方法
KR20160032236A (ko) * 2013-07-19 2016-03-23 코닌클리케 필립스 엔.브이. 광학 요소를 가지며 기판 캐리어를 갖지 않는 ｐｃ ｌｅｄ
JP6486819B2 (ja) * 2015-12-25 2019-03-20 株式会社ジャパンディスプレイ 表示装置
CN108109950A (zh) * 2016-11-25 2018-06-01 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
CN108666212B (zh) * 2018-05-02 2023-01-10 南方科技大学 一种led芯片制作方法
US11646392B2 (en) * 2020-06-09 2023-05-09 Nichia Corporation Method of manufacturing light-emitting device
TWI773279B (zh) * 2021-04-27 2022-08-01 友達光電股份有限公司 顯示面板

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7256483B2 (en) 2004-10-28 2007-08-14 Philips Lumileds Lighting Company, Llc Package-integrated thin film LED

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5617384A (en) * 1979-07-20 1981-02-19 Tokyo Shibaura Electric Co Production of display device
US8294172B2 (en) * 2002-04-09 2012-10-23 Lg Electronics Inc. Method of fabricating vertical devices using a metal support film
JP2003345267A (ja) * 2002-05-30 2003-12-03 Canon Inc 表示装置及びその製造方法
US7015117B2 (en) * 2003-07-14 2006-03-21 Allegis Technologies, Inc. Methods of processing of gallium nitride
US20050205883A1 (en) * 2004-03-19 2005-09-22 Wierer Jonathan J Jr Photonic crystal light emitting device
US7202141B2 (en) 2004-03-29 2007-04-10 J.P. Sercel Associates, Inc. Method of separating layers of material
JP2007173465A (ja) * 2005-12-21 2007-07-05 Rohm Co Ltd 窒化物半導体発光素子の製造方法
WO2007111008A1 (fr) * 2006-03-28 2007-10-04 Sharp Kabushiki Kaisha Procédé de transfert d'un élément semi-conducteur, procédé de fabrication d'un dispositif semi-conducteur, et dispositif semi-conducteur
TWI305960B (en) * 2006-06-16 2009-02-01 Opto Tech Corp Light emitting diode and method manufacturing the same
US9111950B2 (en) * 2006-09-28 2015-08-18 Philips Lumileds Lighting Company, Llc Process for preparing a semiconductor structure for mounting
JP4866268B2 (ja) * 2007-02-28 2012-02-01 新光電気工業株式会社 配線基板の製造方法及び電子部品装置の製造方法
DE102007043877A1 (de) * 2007-06-29 2009-01-08 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung von optoelektronischen Bauelementen und optoelektronisches Bauelement
KR101346538B1 (ko) * 2007-09-26 2013-12-31 니치아 카가쿠 고교 가부시키가이샤 발광소자 및 그것을 이용한 발광장치
TWI345276B (en) * 2007-12-20 2011-07-11 Chipmos Technologies Inc Dice rearrangement package structure using layout process to form a compliant configuration
JP4724222B2 (ja) 2008-12-12 2011-07-13 株式会社東芝 発光装置の製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7256483B2 (en) 2004-10-28 2007-08-14 Philips Lumileds Lighting Company, Llc Package-integrated thin film LED

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012130643A1 (fr) * 2011-03-31 2012-10-04 Osram Opto Semiconductors Gmbh Procédé de séparation d'un assemblage de composants
US9165816B2 (en) 2011-03-31 2015-10-20 Osram Opto Semiconductors Gmbh Method for singulating a component composite assembly
CN109923679A (zh) * 2016-09-22 2019-06-21 奈克斯沃夫有限公司 用于将多个晶种基质设置在载体元件上的方法和带有晶种基质的载体元件

Also Published As

Publication number Publication date
JP5534763B2 (ja) 2014-07-02
US20110073890A1 (en) 2011-03-31
TW201112459A (en) 2011-04-01
TWI419380B (zh) 2013-12-11
US8367523B2 (en) 2013-02-05
EP2302703A3 (fr) 2014-04-30
JP2011071273A (ja) 2011-04-07

Similar Documents

Publication Publication Date Title
US8367523B2 (en) Method for manufacturing semiconductor light-emitting device and semiconductor light emitting device
US8319246B2 (en) Semiconductor device and method for manufacturing same
US9240520B2 (en) Semiconductor light-emitting device and method for manufacturing same
JP4686625B2 (ja) 半導体発光装置の製造方法
US8987020B2 (en) Semiconductor light-emitting device and method for manufacturing same
EP2360750B1 (fr) Dispositif électroluminescent semi-conducteur et son procédé de fabrication
US9425359B2 (en) Light emitting diode
EP2673813B1 (fr) Dispositif électroluminescent à semi-conducteurs
KR101488379B1 (ko) 발광 다이오드
TW201115729A (en) Thin-film flip-chip series connected LEDs
TW201318236A (zh) 具增大面積之氮化鎵發光二極體及其製造方法
JP5205502B2 (ja) 半導体発光装置
JP4865101B2 (ja) 半導体発光装置
JP4719323B2 (ja) 半導体発光装置の製造方法

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20100225

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO SE SI SK SM TR

AX Request for extension of the european patent

Extension state: AL BA RS

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO SE SI SK SM TR

AX Request for extension of the european patent

Extension state: AL BA RS

RIC1 Information provided on ipc code assigned before grant

Ipc: H01L 33/62 20100101ALI20140327BHEP

Ipc: H01L 33/00 20100101AFI20140327BHEP

Ipc: H01L 33/38 20100101ALN20140327BHEP

17Q First examination report despatched

Effective date: 20150206

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN

18W Application withdrawn

Effective date: 20151230