EP2279511A1 - Mémoire comprenant une barrière tunnel et procédé d'écriture et de lecture d'informations dans cette mémoire - Google Patents

Mémoire comprenant une barrière tunnel et procédé d'écriture et de lecture d'informations dans cette mémoire

Info

Publication number
EP2279511A1
EP2279511A1 EP09749478A EP09749478A EP2279511A1 EP 2279511 A1 EP2279511 A1 EP 2279511A1 EP 09749478 A EP09749478 A EP 09749478A EP 09749478 A EP09749478 A EP 09749478A EP 2279511 A1 EP2279511 A1 EP 2279511A1
Authority
EP
European Patent Office
Prior art keywords
memory
tunnel barrier
information
tunnel
property
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP09749478A
Other languages
German (de)
English (en)
Inventor
Hermann Kohlstedt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Forschungszentrum Juelich GmbH
Original Assignee
Forschungszentrum Juelich GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Forschungszentrum Juelich GmbH filed Critical Forschungszentrum Juelich GmbH
Publication of EP2279511A1 publication Critical patent/EP2279511A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/02—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009—RRAM elements whose operation depends upon chemical change
    • G11C13/0011—RRAM elements whose operation depends upon chemical change comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C23/00—Digital stores characterised by movement of mechanical parts to effect storage, e.g. using balls; Storage elements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8825—Selenides, e.g. GeSe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10—Resistive cells; Technology aspects
    • G11C2213/11—Metal ion trapping, i.e. using memory material including cavities, pores or spaces in form of tunnels or channels wherein metal ions can be trapped but do not react and form an electro-deposit creating filaments or dendrites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50—Resistive cell structure aspects
    • G11C2213/54—Structure including a tunneling barrier layer, the memory effect implying the modification of tunnel barrier conductivity

Definitions

  • the invention relates to a memory and a method for writing and reading information in a memory.
  • DRAM dynamic random access memory
  • resistive memories are currently being researched, in which the information is written by a resistance change of the memory material.
  • These memories promise a much higher data density than DRAMs and offer the perspective of a universal memory, which also replaces the mass storage device, because they can in principle not be designed to be volatile.
  • This memory comprises a tunnel barrier and electrical contacting means for conducting a current through the tunnel barrier.
  • the tunnel barrier is in contact with a memory material which has a memory property.
  • This memory property is variable by a write signal. Due to the contact with the tunnel barrier, a change in the memory property results in a change in the tunneling resistance for the current flowing through the tunnel barrier.
  • the write signal to which the memory material reacts with a change in its memory property may be, for example, an applied electrical voltage or an applied electrical current. However, it can also consist for example in an optical excitation by irradiation with light, such as laser light, or in a temperature increase.
  • the change of the memory characteristic due to the write signal is advantageously reversible, so that the memory can be used as a random access memory (RAM) or as a mass memory. If the change is not reversible, the memory can be used as a read-only memory (ROM), a write-once memory (PROM) or a programmable logic array (PLA).
  • RAM random access memory
  • PROM write-once memory
  • PLA programmable logic array
  • contact is not limited to arrangements in which the tunnel barrier and memory material are mutually distinguishable layers adjacent to one another. Contact is also given, for example, if the storage material is present in the form of inclusions in the tunnel barrier.
  • the memory of the present invention can be made more reproducibly and with less relative dispersion in resistance as compared to prior art resistive memories.
  • the quantum mechanical tunnel resistance is excluded. is used. This depends exponentially on the effective thickness of the tunnel barrier, on the charge density and band structure at the interfaces of the tunnel barrier as well as on the effective mass of the tunneling electrons. It has been recognized that a small and thus well-defined change in the memory property of the memory layer can change the tunneling resistance over a much larger dynamic range than is possible in classical resistive memories. Prior to this dynamic range, the inevitable variations in the manufacturing process fade to a much lower relative variance in resistance values than heretofore practicable in the prior art. Thus, an essential requirement is met, which is placed on a memory to be used in an array of a plurality of nominally identical memory cells.
  • the reproducibility of the production is additionally increased by the fact that changes to the tunnel barrier itself, whose construction and reproducible production are already technically optimized, do not necessarily have to be made.
  • a commercially available tunnel barrier can be covered with a memory material or otherwise brought into contact with this memory material in order to produce the memory according to the invention.
  • the memory material has a memory property whose change leads to a change in the level of the conduction band in the tunnel barrier.
  • This can be effected, for example, with a storage material in which the position of ions as a storage property is variable by applying an electrical voltage (and thus an electric field) as a write signal.
  • the ions in the storage material should be displaced from their lattice sites by lower electrical voltages than ions in the tunnel barrier.
  • the tunneling resistance depends exponentially on the ionic charge density and electric field strength at the interface between the storage material and the tunnel barrier, the ions need only be moved a very short distance (a few nanometers) to effect a large change in tunneling resistance; Accordingly, the memory material can be designed as a very thin layer (between 0.5 nm and 20 nm).
  • the storage material may advantageously be designed as a matrix material, so that the ions can move therein.
  • the effective height of the tunnel barrier, on which the tunneling resistance depends exponentially, is a function of the work function between the tunnel barrier and the material adjacent to it. This work function is determined by the difference in Fermi levels between the tunnel barrier on the one hand and the adjacent material on the other hand.
  • This difference, and hence the tunneling resistance, can be changed by introducing or removing ions at the interface between tunnel barrier and memory material.
  • the barrier height is largely determined by the electronic properties (band structure) at the interface.
  • the presence or absence of ions at the interface is equally important with a change in the material properties and thus also the barrier height.
  • a write voltage between 0.1 V and 3 V via the memory material.
  • voltages of 10V and more were typically required.
  • the lower required writing voltage also makes it possible to change the position of the ions along the entire interface between the storage material and the tunnel barrier.
  • the storage material comprises a solid electrolyte (ionic conductor).
  • ionic conductor This is a material which conducts ions in the solid state at the temperature and electric field strength present in the respective application. This ionic conductivity is always associated with mass transport within the solid.
  • the ionic conductivity of each material but also the physical properties of the tunnel barrier are temperature-dependent, although the temperature dependence of the ionic conductivity usually dominates.
  • the skilled artisan is asked to realize the memory for a given operating temperature. For example, when used in space, the temperatures are very low, when using in or on an engine or a fuel cell, however, very high. Since both the temperature behavior of tunnel barriers made of different materials and the temperature behavior of ionic conductors are well researched and documented, he can make a pre-selection of combinations of tunneling barriers and ionic conductors that function at the desired operating temperature.
  • the functionality will not be a yes-no property, but a gradual property, so that the expert can use the evaluation of failures as an additional tool to achieve success.
  • a material such as Ag 2 S, AgS, Ag 2 O, Ag 2 Se, Ag, GeSbSe, CuO 2 or Pb 4 Cu 17 Clj 3 , can be used as a solid electrolyte.
  • These materials are compatible with common tunneling barriers of, for example, SiO 2 , GaN, Al 2 O 3 , MgO, SrTiO 3, and Si 3 N 4 . Special mention should be made of the particularly good compatibility of Ag 2 O with Si 3 N 4 and of AgGeSbSe with Si 3 N 4 or SiO 2 .
  • the interfaces of the storage material are inert to the tunnel barrier and to the electrical contacting means. That is, no ions are coming through the interfaces through, and there is no chemical reaction of the storage material with adjacent materials.
  • Such an inert boundary surface can be realized, for example, by a combination of materials consisting of a tunnel barrier and a storage material in which the tunnel barrier has essentially only defects which are not accessible to ions from the storage material.
  • the materials can be coordinated so that the defects in the tunnel barrier are smaller than the ionic radii in the storage material.
  • the interfaces can also be designed in other ways as diffusion and / or migration barriers for the ions in the storage material. The potential conditions and the defect density should be such that ions can not enter the tunnel barrier through thermal effects or an electric field.
  • the tunnel barrier comprises an amorphous material.
  • defects only act locally; since there is no regular lattice, there is no mobility along lattice axes for ions. Therefore, the ions from the memory material, if any, are difficult to penetrate into an amorphous material tunnel barrier.
  • Nitrides or other non-oxygen containing compounds are chemically very stable and therefore well suited to be compatible with many ionic conductor materials as tunneling barrier materials.
  • the memory material comprises a further tunnel barrier, the tunnel resistance of which as a memory property is variable by the write signal.
  • This can be effected, for example, by a metal layer which can be displaced by the write signal in the further tunnel barrier.
  • this change in the memory property mediated by the write signal also has an exponential influence on the tunnel resistance: for example, if both tunnel barriers are adjacent to one another and thus form a large tunnel barrier, the metal layer which can be displaced by an electric field as the write signal determines the spatial distribution this total barrier to two sub-barriers. Since the tunneling resistance depends exponentially on the effective barrier thickness, the tunneling resistance is lowest when the total barrier is exactly divided by the metal layer.
  • tunneling resistance is orders of magnitude higher if the metal layer is adjacent to one of the electrical contact means and thus each tunneling electron must traverse the length of the total barrier in one piece. There is a shift between these two extremes the metal layer by just a few nanometers, which can already be set up quickly and reversibly with weak fields in comparison to the write fields previously used for resistive memories. Tunneling barriers are typically between 0.2 nm and 10 nm thick.
  • the memory property of the memory material should be such that it remains stable for at least 100 ns after the omission of the write signal. This time is already sufficient, so that the memory can be used as a volatile memory analogous to today's dynamic RAM (DRAM), which is refreshed regularly. DRAM is typically refreshed at 1ms intervals. If the memory property is stable for a long time (5,000, preferably 50,000 hours), it can also be used as a non-volatile memory. He can then act as a universal memory, which replaces both the previous memory and the previous mass storage.
  • DRAM dynamic RAM
  • the memory property is bistable or multistable. If the memory property can be changed continuously as a function of the strength of the write signal, then analog measured values for further processing in an analog circuit can be temporarily stored, for example, without the information being lost as a result of the discrimination in an analog-to-digital converter.
  • a method for storing information in a memory with a tunnel barrier and for reading out the stored information has been developed.
  • This method is characterized in that, for storing the information, the level of the conduction band edge in the tunnel barrier and / or the spatial division of the tunnel barrier into a plurality of subbranches are changed.
  • To read the information will measured a measure that is a measure of the tunneling probability through the tunnel barrier, such as a tunneling current.
  • the level of the conduction band edge in the tunnel barrier is advantageously changed by a change in an electric field presented at an edge of the tunnel barrier.
  • This electric field can be, for example, the field of ions which are introduced at an interface of the tunnel barrier or subtracted from it.
  • the ions may, for example, be bound in a memory layer adjacent to the tunnel barrier in such a way that they only leave their position occupied when the information is stored until they have been subjected to an opposite write signal.
  • the memory is traversed for storing information with a write current and for reading the information with a read current, wherein the write current is greater than the read current. Then both the storage and the readout can be done with the same drive circuit, wherein only at one point the power must be changed.
  • FIG. 1 shows the schematic structure of an embodiment of the memory according to the invention.
  • This memory has a tunnel barrier 1 and metal electrodes (2 a, 2 b) as contacting means for conducting a current through the tunnel barrier 1.
  • the tunnel barrier 1 is in contact with a storage material 3.
  • This memory material 3 is an electrochemically active layer in which the position of ions is variable by a voltage applied between the metal electrodes (2a, 2b) as a write signal.
  • the interface 4a of the memory material 3 to the tunnel barrier 1 and the interface 4b of the memory material 3 to the metal electrode 2b are designed as impermeable diffusion and / or migration stops for ions.
  • FIG. 2 shows the schematic structure of a modified embodiment of the memory according to the invention.
  • the memory material 3 is here a second tunnel barrier, in which a metal layer 3 a is embedded.
  • This metal layer 3 a can be moved as a whole by a voltage applied between the metal electrodes (2 a, 2 b) as a write signal in the direction of the tunnel barrier 1 or in the direction of the metal electrode 2 b.
  • the tunnel barrier 1 and the memory material 3 taken together form a single tunnel barrier, which is composed of two separated by the metal layer 3a partial barriers:
  • the first sub-barrier extends from the metal electrode 2a to the metal layer 3a
  • the second sub-barrier extends from the metal layer 3a to the metal electrode 2b.
  • the total resistance of the series connection of the two sub-barriers is lowest, if the metal layer 3 a is located at the interface between memory material 3 and tunnel barrier 1. In contrast, the total resistance is greatest when the metal layer 3a is located at the interface between the memory material 3 and the metal electrode 2b.
  • a multiplicity of units (cells) of the memory according to the invention can advantageously be arranged in a "cross-bar array" in order to store large amounts of information,
  • Such an array consists of an arrangement of parallel word lines, which as a rule reside on On the word lines are, preferably in Periodically, applied units of the memory according to the invention.
  • bit lines are applied to the memory units, which are perpendicular to the word lines and interconnect memory units.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

La présente invention concerne une mémoire résistive contenant une barrière tunnel. La barrière tunnel est en contact avec le matériau constitutif de la mémoire qui a une propriété de mémoire variable en fonction d'un signal d'écriture. Une modification de la propriété de mémoire a une forte influence sur la résistance tunnel du fait que la résistance tunnel dépend de manière exponentielle des paramètres de la barrière tunnel, ce qui permet de lire les informations enregistrées dans le matériau constitutif de la mémoire. En tant que couche mémoire peut être utilisé par exemple un électrolyte solide (conducteur d'ions) dont les ions peuvent être mis en mouvement avec la barrière tunnel par rapport à la surface limite sous l'effet du signal d'écriture. La couche mémoire peut aussi être par exemple une autre barrière tunnel dont la résistance tunnel varie sous l'effet du signal d'écriture, par exemple par déplacement d'une couche métallique présente dans cette barrière tunnel. L'invention concerne également un procédé d'enregistrement et de lecture d'informations dans une mémoire.
EP09749478A 2008-05-17 2009-04-17 Mémoire comprenant une barrière tunnel et procédé d'écriture et de lecture d'informations dans cette mémoire Withdrawn EP2279511A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102008024078A DE102008024078A1 (de) 2008-05-17 2008-05-17 Speicher sowie Verfahren zum Schreiben und Auslesen von Information in einem Speicher
PCT/DE2009/000525 WO2009140936A1 (fr) 2008-05-17 2009-04-17 Mémoire comprenant une barrière tunnel et procédé d'écriture et de lecture d'informations dans cette mémoire

Publications (1)

Publication Number Publication Date
EP2279511A1 true EP2279511A1 (fr) 2011-02-02

Family

ID=40869503

Family Applications (1)

Application Number Title Priority Date Filing Date
EP09749478A Withdrawn EP2279511A1 (fr) 2008-05-17 2009-04-17 Mémoire comprenant une barrière tunnel et procédé d'écriture et de lecture d'informations dans cette mémoire

Country Status (6)

Country Link
US (1) US8537590B2 (fr)
EP (1) EP2279511A1 (fr)
JP (1) JP2011523204A (fr)
CN (1) CN102037517A (fr)
DE (1) DE102008024078A1 (fr)
WO (1) WO2009140936A1 (fr)

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US8421048B2 (en) * 2009-07-13 2013-04-16 Seagate Technology Llc Non-volatile memory with active ionic interface region
US8780607B2 (en) 2011-09-16 2014-07-15 Micron Technology, Inc. Select devices for memory cell applications
US9349445B2 (en) 2011-09-16 2016-05-24 Micron Technology, Inc. Select devices for memory cell applications
US9142767B2 (en) 2011-09-16 2015-09-22 Micron Technology, Inc. Resistive memory cell including integrated select device and storage element
US9299926B2 (en) * 2012-02-17 2016-03-29 Intermolecular, Inc. Nonvolatile memory device using a tunnel oxide layer and oxygen blocking layer as a current limiter element
CN109374644B (zh) * 2018-11-09 2021-08-03 中国矿业大学 基于图像识别的隧道衬砌缺陷智能检测模拟实验装置

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Also Published As

Publication number Publication date
CN102037517A (zh) 2011-04-27
US20110051494A1 (en) 2011-03-03
JP2011523204A (ja) 2011-08-04
US8537590B2 (en) 2013-09-17
DE102008024078A1 (de) 2009-12-17
WO2009140936A1 (fr) 2009-11-26

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