EP2143310A1 - Verfahren zur selektiven oberflächenbehandlung von nicht plattenförmigen werkstücken - Google Patents

Verfahren zur selektiven oberflächenbehandlung von nicht plattenförmigen werkstücken

Info

Publication number
EP2143310A1
EP2143310A1 EP08736296A EP08736296A EP2143310A1 EP 2143310 A1 EP2143310 A1 EP 2143310A1 EP 08736296 A EP08736296 A EP 08736296A EP 08736296 A EP08736296 A EP 08736296A EP 2143310 A1 EP2143310 A1 EP 2143310A1
Authority
EP
European Patent Office
Prior art keywords
workpiece
workpieces
surface treatment
treatment
selective surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP08736296A
Other languages
German (de)
English (en)
French (fr)
Inventor
Claus Peter Kluge
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ceramtec GmbH
Original Assignee
Ceramtec GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ceramtec GmbH filed Critical Ceramtec GmbH
Publication of EP2143310A1 publication Critical patent/EP2143310A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0097Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02Electroplating of selected surface areas
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0284Details of three-dimensional rigid printed circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0335Layered conductors or foils
    • H05K2201/0347Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1147Sealing or impregnating, e.g. of pores
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15Position of the PCB during processing
    • H05K2203/1536Temporarily stacked PCBs
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • H05K3/244Finish plating of conductors, especially of copper conductors, e.g. for pads or lands

Definitions

  • the invention relates to a method for the selective surface treatment of a workpiece according to the preamble of claim 1.
  • This method for the selective surface treatment of a plate-shaped workpiece on at least one of two metallic surface sides is characterized in that at least two similar workpieces at one of their first surface sides at least in a partial area sealed to the outside are releasably connected to each other, and that in a treatment phase then the selective surface treatment of not covered by the compound areas of the metallic surface sides.
  • the selective surface treatment of only certain metallizations but not of those metallizations for which no surface treatment is provided takes place in one process step.
  • two multiple substrates, each with their metallizations, for which no surface treatment is provided, having side by a connecting element tightly, but releasably connected to each other, in such a way that the metallizations, for which no surface treatment is provided by a connecting element to the outside are completely covered.
  • the metallizations for which no surface treatment is intended are to be found in that of the connecting element and the ceramic layers of the present invention.
  • the invention has the object of developing a method according to the preamble of claim 1 so that a better cooling and easier distribution of the metallized areas is possible.
  • this object is achieved in that at least the first workpiece is not formed plate-shaped and is provided on at least one side over the entire surface or part of surface with identical or different metallized o- the non-metallized surfaces or cavities or combinations thereof and at the selective surface treatment at least one other metallic coating or another metallic coating is applied. Due to the non-plate-shaped design of the first workpiece, both a better cooling and a better distribution of the metallized areas can be achieved. The better cooling can be achieved by any configuration of the surface. A departure from the plate-shaped design of the workpiece always leads to an enlarged O- ber Structure and thus to an improvement in the cooling and the provision of more floor space.
  • the upper sides and the lower sides of the workpieces are formed such that they each have a surface of different sizes.
  • one of the sides of the first workpiece and / or one of the sides of the other workpieces are formed with a flat surface.
  • At least one of the other workpieces connected to the first workpiece can also be plate-shaped.
  • the selective surface treatment is carried out by chemical and / or electrolytic deposition, or combinations thereof, of at least one metallic coating.
  • the sealed and again detachable connection of the first workpiece with at least one other workpiece takes place in such a way that at least one surface of the first workpiece is covered over the entire area or part of the area by the connection.
  • At least some of the workpieces are made of metal, ceramic, polymers or combinations thereof. Ceramic has proven to be particularly advantageous.
  • At least the first workpiece is a populated or unpopulated electrically non-conductive or almost non-conductive circuit carrier and carries at least one full-area or partial-area metallization on at least one surface.
  • At least the first workpiece but preferably also the other workpieces, a ceramic-metal substrate.
  • a metal-ceramic substrate is known.
  • at least the first workpiece is provided at a location with a metallization, which is connected to the DCB (direct copper bonding) method or AMB (active metal brazing) method with the workpiece.
  • a frame or plate-like connecting element is used for the detachable connection of the first workpiece with at least one other workpiece corresponding to the negative contour of the surface to be covered of the first workpiece, on which the other workpieces using an adhesive and / or adhesive and / or sealing mass and / or be kept under vacuum.
  • a plurality of temporally successive treatment phases of a same or different selective surface treatment are carried out, wherein prior to each treatment phase of the selective surface treatment, the workpieces are sealed to one another at their non-treated surface sides.
  • An inventive embodiment is characterized in that several temporally successive treatment phases of the same or different selective treatment and subtractive processes, such as etching processes, at the uncovered areas are performed.
  • At least two different selective surface treatments are preferably carried out simultaneously or alternately by appropriate geometric arrangement of the workpieces.
  • At least one workpiece is advantageously a ceramic heatsink.
  • Heatsink is a carrier body for electrical or electronic
  • the carrier body is not electrically or nearly non-conductive and the carrier body in one piece with heat is provided off or feeding cooling elements.
  • the carrier body is a circuit board and the cooling elements bores, channels, ribs and / or recesses, which can be acted upon by a heating or cooling medium.
  • the carrier body and / or the cooling element consist for. B. from at least one ceramic component or a composite of different ceramics. Heat sinks are described, for example, in DE 10 2007 014433 A1 or DE 37 09 200 A1.
  • FIG. 1 shows a first workpiece 1 with different metallized regions or metallizations 3.
  • the region 6 which is not to be treated is covered.
  • a single other workpiece 2 is used which likewise has metallizations 3 on its sides. This other workpiece 2 is placed over a sealing element 7 on the non-treated areas 3, that they are covered. The connection is made so that the other workpiece 2 is again removable from the first workpiece 1.
  • the selective surface treatment of the regions not covered by the compound then takes place in a treatment phase.
  • the selective surface treatment is preferably carried out by chemical and / or electrolytic deposition, or combinations thereof, of at least one metallic coating.
  • the first workpiece 1 is not plate-shaped.
  • the other workpiece 2 is not formed plate-shaped. Not plate-shaped means that the tops 4 and the bottoms 5 of the workpieces 1, 2 are formed so that they each have a different surface area.
  • the tops 4 of the first 1 and the other workpiece 2 in this case have a flat surface.
  • the sealed between the first 1 and the other workpiece 2 on the sealing elements 7 sealed space 8 can be provided to improve the holding connection with a negative pressure.
  • the workpieces shown here are made of a ceramic and are a ceramic ceramic metal substrate or heatsink.
  • FIG. 2 shows a first workpiece 1 consisting of a ceramic, which has a flat upper side 4. On this top 4 different metallized areas 3 are applied and the top 4 is a circuit carrier. The underside 5 of the first workpiece 1 has cooling fins 9 and is a heatsink. Heat sinks are described, for example, in DE 10 2007 014433 A1.
  • the non-treated metallizations 6 are covered with other workpieces 2a, 2b, 2c. These other workpieces 2a, 2b, 2c are connected via sealing elements 7 with the first workpiece 1 and with each other.
  • the first workpiece 1 is not plate-shaped and its upper side 4 has a different surface area than its underside. 5
  • the other workpiece 2a is plate-shaped.
  • the other workpieces 2b, 2c are not formed plate-shaped.
  • Both the first workpiece 1 and the other workpieces 2 have metallizations 3 on all their sides. In part, these metallizations 3 are also provided with further metallizations or with components.
  • the other workpiece 2b is also made of a ceramic and has on its sides in each case a recess 10, 1 1 on.
  • the recess 10 is conical and the recess 11 is spherical.
  • the other workpiece 2c is U-shaped. Again, the sealed space is indicated by the reference numeral 8.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Other Surface Treatments For Metallic Materials (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Ceramic Products (AREA)
EP08736296A 2007-04-24 2008-04-17 Verfahren zur selektiven oberflächenbehandlung von nicht plattenförmigen werkstücken Withdrawn EP2143310A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102007019634 2007-04-24
PCT/EP2008/054623 WO2008128943A1 (de) 2007-04-24 2008-04-17 Verfahren zur selektiven oberflächenbehandlung von nicht plattenförmigen werkstücken

Publications (1)

Publication Number Publication Date
EP2143310A1 true EP2143310A1 (de) 2010-01-13

Family

ID=39677408

Family Applications (1)

Application Number Title Priority Date Filing Date
EP08736296A Withdrawn EP2143310A1 (de) 2007-04-24 2008-04-17 Verfahren zur selektiven oberflächenbehandlung von nicht plattenförmigen werkstücken

Country Status (7)

Country Link
US (1) US20100147795A1 (zh)
EP (1) EP2143310A1 (zh)
JP (1) JP5737934B2 (zh)
KR (1) KR20100017314A (zh)
CN (1) CN101690427A (zh)
DE (1) DE102008001218A1 (zh)
WO (1) WO2008128943A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008128949A2 (de) * 2007-04-24 2008-10-30 Ceramtec Ag Verfahren zum herstellen eines verbundes mit zumindest einem nicht plattenförmigen bauteil
DE102009025033A1 (de) 2009-06-10 2010-12-16 Behr Gmbh & Co. Kg Thermoelektrische Vorrichtung und Verfahren zum Herstellen einer thermoelektrischen Vorrichtung
CN106423775B (zh) * 2016-08-31 2019-09-03 河南航天精工制造有限公司 空心工件外表面部分涂覆方法及工装

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020062987A1 (en) * 2000-11-27 2002-05-30 Yoshiyuki Uchinono Multilayer circuit board and method of manufacturing the same

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3930115A (en) * 1971-05-19 1975-12-30 Philips Corp Electric component assembly comprising insulating foil bearing conductor tracks
JPS5842167U (ja) * 1981-09-17 1983-03-19 スズキ株式会社 メツキ装置
DE3709200A1 (de) * 1987-03-20 1988-09-29 Heraeus Gmbh W C Elektronisches bauteil
JPH0554555U (ja) * 1991-12-26 1993-07-20 石川島播磨重工業株式会社 メッキ作業用治具
JPH08274225A (ja) * 1995-03-29 1996-10-18 Toshiba Corp 半導体部品
EP1063873A3 (de) * 1999-06-22 2003-04-23 Dr.-Ing. Jürgen Schulz-Harder Verfahren zum Herstellen von Substraten mit strukturierten Metallisierungen sowie Halte-und Fixierelement zur Verwendung bei dem Verfahren
US20020197492A1 (en) * 2001-06-25 2002-12-26 Ling Hao Selective plating on plastic components
DE10154316A1 (de) * 2001-11-07 2003-05-15 Juergen Schulz-Harder Verfahren zur selektiven Oberflächenbehandlung von plattenförmigen Werkstücken
DE102004033227A1 (de) * 2004-07-08 2006-01-26 Curamik Electronics Gmbh Metall-Keramik-Substrat
JP2007088030A (ja) * 2005-09-20 2007-04-05 Fuji Electric Holdings Co Ltd 半導体装置
TWI449137B (zh) 2006-03-23 2014-08-11 Ceramtec Ag 構件或電路用的攜帶體

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020062987A1 (en) * 2000-11-27 2002-05-30 Yoshiyuki Uchinono Multilayer circuit board and method of manufacturing the same

Also Published As

Publication number Publication date
US20100147795A1 (en) 2010-06-17
KR20100017314A (ko) 2010-02-16
JP5737934B2 (ja) 2015-06-17
WO2008128943A1 (de) 2008-10-30
JP2010530027A (ja) 2010-09-02
CN101690427A (zh) 2010-03-31
DE102008001218A1 (de) 2008-10-30

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