EP2097924A2 - Tranche traitée au niveau de l'extrémité frontale ayant des connexions traversant les puces - Google Patents

Tranche traitée au niveau de l'extrémité frontale ayant des connexions traversant les puces

Info

Publication number
EP2097924A2
EP2097924A2 EP07870039A EP07870039A EP2097924A2 EP 2097924 A2 EP2097924 A2 EP 2097924A2 EP 07870039 A EP07870039 A EP 07870039A EP 07870039 A EP07870039 A EP 07870039A EP 2097924 A2 EP2097924 A2 EP 2097924A2
Authority
EP
European Patent Office
Prior art keywords
vias
semiconductor wafer
layer
forming
electrically conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP07870039A
Other languages
German (de)
English (en)
Other versions
EP2097924A4 (fr
Inventor
John Trezza
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cufer Asset Ltd LLC
Original Assignee
Cufer Asset Ltd LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cufer Asset Ltd LLC filed Critical Cufer Asset Ltd LLC
Publication of EP2097924A2 publication Critical patent/EP2097924A2/fr
Publication of EP2097924A4 publication Critical patent/EP2097924A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to semiconductors and, more particularly, to electrical connections for such devices.
  • Another type of implementation involves forming the through chip connections on a wafer where the devices have been formed, but the back end processing to add the metal interconnect layers has not been completed.
  • transistors that may be very sensitive to processing and need flat and extremely defect-free areas can be formed without the risk of contamination, thereby improving transistor yield while still obtaining the routing benefits because the vias can be formed before the first metal layer is deposited during a back-end process, after the first metal layer is deposited but before the second metal layer is deposited, or more generally, before depositing of any of the "n" layers that may be deposited as part of the back-end processing.
  • FIG. 1 illustrates, in simplified form, a portion of a blank wafer which will be used to illustrate the process
  • FIG. 2 illustrates, in simplified form, the portion of the wafer of FIG. 1 after formation of the vias
  • FIG. 3 illustrates, in simplified form, the vias of FIG. 2 after the simple via and one of the annular vias has been filled with metal;
  • FIG. 4 illustrates, in simplified form, the portion of the wafer of FIG. 1 after front end processing is complete
  • FIG. 5 illustrates, in simplified form, a portion of a front end processed wafer which will be used to illustrate the alternative process
  • FIG. 6 illustrates, in simplified form, the portion of the front end processed wafer after formation of the vias
  • FIG. 7 illustrates, in simplified form, the vias of FIG. 6 after they have been filled with the desired electrically conductive filler material
  • FIG. 8 illustrates, in simplified form, the configuration of FIG. 7 after the metal- 1 layer has been added during back-end processing; and [0018] FIGS. 9A through 9D illustrate the successive steps in a variant approach.
  • the approach straightforwardly involves forming vias in a blank wafer at the locations where they should be relative to devices that would be on the wafer once front end processing is complete, making the vias electrically conductive and then fabricating the devices on the wafer, thereby making the connections between the devices and the through-chip connections by virtue of the device fabrication process.
  • a blank wafer for example, a silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium-arsenide (GaAs), indium phosphide (InP) or other wafer.
  • FIG. 1 illustrates, in simplified form, a cross section of a portion 100 of a blank wafer 102 which will be used to illustrate the process. Note that scales are grossly distorted for simplicity of presentation.
  • FIG. 2 illustrates, in simplified form, the portion 100 of the blank wafer 102 after formation of the vias 202, 204, 206. As shown, the vias in the portion include one simple via 202 and two annular vias 204, 206.
  • the vias do not extend completely through the wafer, but rather stop a short distance from the bottom surface 104 of the wafer to prevent the central post from falling out.
  • the vias are made electrically conductive by filling them with a conductor that can withstand the temperatures and stresses involved in the particular front end processing steps and specifically, device creation.
  • the conductor could be any of Au, Cu, Ni, W, Ti or any other metal or alloy that can withstand the temperatures involved in the CMOS processing.
  • the via can be coated with a layer of dielectric or insulator before filling with the conductor to prevent or insure that the conductor does not short to the substrate.
  • this can involve filling the vias using a vapor deposition process, a plating process or any other process which will result in filling of the vias.
  • the annular vias can be filled with a suitably robust insulator and the central posts can be left intact (i.e. not removed) so that, during front end processing, the central posts can be suitably doped and thereby act as the conductor itself and eliminating the need for any metal at all in such vias.
  • FIG. 3 illustrates, in simplified form, the vias 202, 204, 206 of FIG. 2 after the simple via 202 has been filled with metal 208 and one of the annular vias 202 (which has had its central post removed) and the space left by the removal has also been filled with metal
  • both of the annular vias 204, 206 have been filled with a suitable insulator
  • the bottom surface 104 of the wafer can now be thinned to expose the conductor metal 208 or the bottom of a central post
  • the vias will not extend fully through the wafer, and the region between the bottom of the wafer and the via is maintained at sufficient dimensions so that it can become the device region during front end processing.
  • the wafer can undergo the normal front end and back-end processing and dicing in the conventional manner. Once that processing is complete, the final chip will have the same kind of through-chip connections as it could have had by performing one of the above-incorporated approaches on a fully processed chip but at a much lower risk and, potentially, with a higher yield.
  • FIG. 4 illustrates, in simplified form, the portion of the wafer of FIG. 1 after front end processing is complete.
  • the wafer has become a front- end processed wafer 400 and now includes a doped region 402 where devices can be present.
  • the vias by virtue of their location relative to the devices, are now electrically connected to the appropriate parts of the devices.
  • the approach straightforwardly involves forming devices on the wafer until front end processing is complete, but before one or more phases of the back end processing begins, forming vias in the front-end processed wafers, making the vias electrically conductive and then performing one or more additional back-end processing phases.
  • FIG. 5 illustrates, in simplified form, a portion 500 of a front end processed wafer 502 which will be used to illustrate the alternative process. As shown, the wafer 502 contains formed devices in the doped region 504. However, at this point, back-end processing to add metal interconnect layers has not occurred.
  • vias are formed in the wafer at the appropriate locations for either connecting to or avoiding the devices. Depending upon the particular implementation this can involve formation of the vias using, for example, one of the techniques described in the above-incorporated applications. Alternatively, or additionally, vias can be formed by other processes including, for example, laser drilling.
  • FIG. 6 illustrates, in simplified form, the portion 500 of the front end processed wafer 502 after formation of the vias 602, 604, 606.
  • the vias in the portion 500 include one simple via 602 (which may or may not contain the optional dielectric or insulator coating) and two annular vias 604, 606. Note that, because annular vias are used, the vias do not extend completely through the wafer 502, but rather stop a short distance from the bottom surface 506 of the wafer 502 to prevent the central post from falling out.
  • the vias Once the vias have been formed, they are made electrically conductive by filling them with a conductive fill material.
  • this can involve filling the vias using a vapor deposition process, a plating process or any other process which will result in filling of the vias.
  • the via fill can be the same material as will be used for the metal layer(s) that will be formed., for example aluminum, tungsten or copper, it can be a different material than will be used for formation of the metal layer, for example, gold, silver or nickel, or, in the case where a connection is directly made to a device, a material matching the particular portion of the device to which the via reaches and it will attach, for example, using a polysilicon that matches the gate material of a field effect transistor.
  • FIG. 7 illustrates, in simplified form, the vias 602, 604, 606 of FIG. 6 after they have been filled with the desired electrically conductive filler material 608. Note that, as shown and prior to filling with the conductor, annular vias have been filled with a suitable insulator 610 and the central posts of each of the annular vias 604, 606 have been removed.
  • the bottom surface 506 of the wafer 502 can now be thinned to expose the electrically conductive filler material 608.
  • the thinning (if needed) can occur at some point thereafter.
  • the back-end processing can begin by laying down the first back-end connection layer (referred to herein as the "metal- 1" layer).
  • FIG. 8 illustrates, in simplified form, the configuration of FIG. 7 after the metal-1 layer 800 has been added during back-end processing.
  • the conductive filler material 608 of a given via can connect directly to the metal-1 layer 800. or not, as desired, in the former case, this could simply occur by depositing the metal-1 layer 800 so that a portion of the metal-1 layer 800 directly contacts and overlays the conductive filler material 608 of a via such as shown in FIG. 8.
  • the formation of the metal-1 layer can occur as part of the via filling process, for example, if a plating process is used.
  • the wafer will be patterned with both the routing for the metal-1 layer 800 and the vias to be filled exposed. Thereafter, a seed layer is applied to facilitate plating and then plating occurs. In this manner, the plating "overburden" that forms wherever the seed is, will inherently form the metal-1 layer 800.
  • particular vias can be extended "upwards" through the metalization layers, as needed, to connect to one or more particular metalization layers (e.g. any of metal-2 through metal-N, where "N" is the outermost layer).
  • a further advantageous alternative variant approach can be used, where connections must be made to one or more of the metal-2 through metal-N layers.
  • This variant approach is similar to the immediately preceding approach except that a photoresis can be used to pattern the overburden.
  • One type of photoresist that can be used is a"solid" photoresist that can be used to selectively cover certain vias so that, although all of the vias are formed in the wafer, only those that will connect to the metal-1 layer are left exposed for the first round of plating.
  • Suitable "solid" photoresist materials include, by way of non limiting example, the Riston® dry film photoresist line, commercially available from E. I.
  • du Pont de Nemours & Co or other similar photoresists that rae available in sheets of appropriate thickness.
  • the Riston® dry film photoresist line the Riston® PlateMaster, EtchMaster and TentMaster lines of photoresist can be used.
  • the advantage of a photoresist product like Riston® is that it can be placed on the surface as sheets and it has rigidity. This rigidity means that it can be patterned in such a way that it can cover a via in a way that allows it to be easily re-exposed at a later point in time.
  • FIGS. 9 A through 9D illustrate the successive steps in a variant approach, involving use of a solid photoresist, performed on an example portion 900 of a wafer 902 that already has devices in a device region 904 thereon and has already had vias 906, 908, 910, 912 formed as described herein. [0047] Through use and patterning of the solid photoresist 905, the filling of the vias
  • the first "solid" photoresist 905 layer is removed and a new “solid” photoresist 905 layer is applied to protect the metal-1 layer and vias 910, 912 that will connect to other layers and patterned to expose those vias 908 that will be filled concurrently with the formation of the metal-2 layer, a seed layer is applied and plating is performed to both fill the via and use the plating "overburden" as the metal-2 layer (FIG. 9B).
  • the approach is iteratively repeated for successive metalization layers (FIG.
  • the front end processing can be performed up to the point that a component of a device is added and then the via creation and fill could occur concurrently with creation of the component, for example, the vias can be etched and filled concurrently with the deposition of gate conductors (for the gates of transistors).
  • the front end processing could be completed as above, but the back-end processing would be completed only until the metal-"X" layer (where N is the ultimate total number of layers for the completed integrated circuit chip and 1 ⁇ X ⁇ N) and then the vias would be etched and filled up to that layer.
  • the back-end processing would continue and, optionally, this process could be repeated after some additional number of layers, before the metal-N layer, are completed.
  • the approaches herein also allow the back-end processing to be stopped at an intermediate point for device testing, for example, for simple functionality so that, if any given die is nonfunctional or the overall wafer has an insufficient yield, the processing can be halted or only continue on dies that pass this intermediate testing.

Abstract

L'invention concerne un procédé qui implique la formation de trous d'interconnexion dans une tranche semi-conductrice portant un dispositif, rendant au moins une partie des trous d'interconnexion dans la tranche semi-conductrice portant un dispositif électriquement conductrice, et la réalisation d'un traitement dorsal de la tranche semi-conductrice portant un dispositif de manière à créer des connexions électriques entre un trou d'interconnexion électriquement conducteur et une couche de métallisation. Un procédé alternatif implique la formation de trous d'interconnexion dans une tranche semi-conductrice portant un dispositif, rendant au moins une partie des trous d'interconnexion dans la tranche semi-conductrice portant un dispositif électriquement conductrice, et le traitement de la tranche semi-conductrice portant un dispositif de manière à créer des connexions électriques entre un trou d'interconnexion électriquement conducteur et une couche semi-conductrice conductrice.
EP07870039A 2006-12-29 2007-12-28 Tranche traitée au niveau de l'extrémité frontale ayant des connexions traversant les puces Withdrawn EP2097924A4 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US88267106P 2006-12-29 2006-12-29
PCT/US2007/089061 WO2008083284A2 (fr) 2006-12-29 2007-12-28 Tranche traitée au niveau de l'extrémité frontale ayant des connexions traversant les puces

Publications (2)

Publication Number Publication Date
EP2097924A2 true EP2097924A2 (fr) 2009-09-09
EP2097924A4 EP2097924A4 (fr) 2012-01-04

Family

ID=39589215

Family Applications (1)

Application Number Title Priority Date Filing Date
EP07870039A Withdrawn EP2097924A4 (fr) 2006-12-29 2007-12-28 Tranche traitée au niveau de l'extrémité frontale ayant des connexions traversant les puces

Country Status (5)

Country Link
EP (1) EP2097924A4 (fr)
JP (2) JP2010515275A (fr)
KR (1) KR101088926B1 (fr)
CN (1) CN101663742B (fr)
WO (1) WO2008083284A2 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007044685B3 (de) * 2007-09-19 2009-04-02 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Elektronisches System und Verfahren zur Herstellung eines dreidimensionalen elektronischen Systems
FR2987937B1 (fr) * 2012-03-12 2014-03-28 Altatech Semiconductor Procede de realisation de plaquettes semi-conductrices
JP5925006B2 (ja) * 2012-03-26 2016-05-25 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1351288A1 (fr) * 2002-04-05 2003-10-08 STMicroelectronics S.r.l. Procédé pour fabriquer une interconnexion isolée à travers dans un corps semi-conducteur
US20030200654A1 (en) * 2002-04-25 2003-10-30 Fujitsu Limited Method of manufacturing electronic circuit component
US20050001326A1 (en) * 2003-05-06 2005-01-06 Seiko Epson Corporation Semiconductor device, stacked semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument
US20050101116A1 (en) * 2003-11-10 2005-05-12 Shih-Hsien Tseng Integrated circuit device and the manufacturing method thereof
US20050139954A1 (en) * 2003-12-30 2005-06-30 Pyo Sung G. Radio frequency semiconductor device and method of manufacturing the same
EP1686623A1 (fr) * 2003-10-30 2006-08-02 Japan Science and Technology Agency Dispositif semi-conducteur et son procede de fabrication

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03218653A (ja) * 1989-11-13 1991-09-26 Mitsubishi Electric Corp エアーブリッジ金属配線を具えた半導体装置およびその製造方法
JP3979791B2 (ja) 2000-03-08 2007-09-19 株式会社ルネサステクノロジ 半導体装置およびその製造方法
JP3748844B2 (ja) * 2002-09-25 2006-02-22 Ｎｅｃエレクトロニクス株式会社 半導体集積回路およびそのテスト方法
WO2004064159A1 (fr) * 2003-01-15 2004-07-29 Fujitsu Limited Dispositif a semi-conducteur, appareil a semi-conducteur a montage tridimensionnel, procede de production du dispositif a semi-conducteur
JP4322508B2 (ja) * 2003-01-15 2009-09-02 新光電気工業株式会社 半導体装置の製造方法
SE526366C3 (sv) * 2003-03-21 2005-10-26 Silex Microsystems Ab Elektriska anslutningar i substrat
JP4114660B2 (ja) * 2003-12-16 2008-07-09 セイコーエプソン株式会社 半導体装置の製造方法、半導体装置、回路基板、電子機器
TW200535918A (en) * 2004-03-09 2005-11-01 Japan Science & Tech Agency Semiconductor device and methods for fabricating the same, semiconductor system having laminated structure, semiconductor interposer, and semiconductor system
JP3875240B2 (ja) 2004-03-31 2007-01-31 株式会社東芝 電子部品の製造方法
JP4492196B2 (ja) * 2004-04-16 2010-06-30 セイコーエプソン株式会社 半導体装置の製造方法、回路基板、並びに電子機器
US7249992B2 (en) * 2004-07-02 2007-07-31 Strasbaugh Method, apparatus and system for use in processing wafers
JP2006049557A (ja) * 2004-08-04 2006-02-16 Seiko Epson Corp 半導体装置
CN101714512B (zh) * 2004-08-20 2012-10-10 佐伊科比株式会社 具有三维层叠结构的半导体器件的制造方法
JP4524156B2 (ja) * 2004-08-30 2010-08-11 新光電気工業株式会社 半導体装置及びその製造方法
US7838997B2 (en) * 2005-06-14 2010-11-23 John Trezza Remote chip attachment
US7767493B2 (en) * 2005-06-14 2010-08-03 John Trezza Post & penetration interconnection
US7488680B2 (en) 2005-08-30 2009-02-10 International Business Machines Corporation Conductive through via process for electronic device carriers

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1351288A1 (fr) * 2002-04-05 2003-10-08 STMicroelectronics S.r.l. Procédé pour fabriquer une interconnexion isolée à travers dans un corps semi-conducteur
US20030200654A1 (en) * 2002-04-25 2003-10-30 Fujitsu Limited Method of manufacturing electronic circuit component
US20050001326A1 (en) * 2003-05-06 2005-01-06 Seiko Epson Corporation Semiconductor device, stacked semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument
EP1686623A1 (fr) * 2003-10-30 2006-08-02 Japan Science and Technology Agency Dispositif semi-conducteur et son procede de fabrication
US20050101116A1 (en) * 2003-11-10 2005-05-12 Shih-Hsien Tseng Integrated circuit device and the manufacturing method thereof
US20050139954A1 (en) * 2003-12-30 2005-06-30 Pyo Sung G. Radio frequency semiconductor device and method of manufacturing the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2008083284A2 *

Also Published As

Publication number Publication date
KR101088926B1 (ko) 2011-12-01
CN101663742A (zh) 2010-03-03
JP2013175786A (ja) 2013-09-05
JP2010515275A (ja) 2010-05-06
WO2008083284A3 (fr) 2008-08-21
JP5686851B2 (ja) 2015-03-18
CN101663742B (zh) 2013-11-06
WO2008083284A2 (fr) 2008-07-10
EP2097924A4 (fr) 2012-01-04
KR20090094371A (ko) 2009-09-04

Similar Documents

Publication Publication Date Title
US7687397B2 (en) Front-end processed wafer having through-chip connections
US7453150B1 (en) Three-dimensional face-to-face integration assembly
US7919835B2 (en) Semiconductor device and method for manufacturing the same
EP2255386B1 (fr) Procédé de fabrication d'interconnexions verticales et puce semi-conductrice préparée pour une interconnexion verticale
US7935571B2 (en) Through substrate vias for back-side interconnections on very thin semiconductor wafers
US20120001337A1 (en) Alignment Mark and Method of Formation
US8969200B2 (en) Apparatus and method for integration of through substrate vias
US8163629B2 (en) Metallization for chip scale packages in wafer level packaging
US10262959B2 (en) Semiconductor devices and methods of forming thereof
US20130001746A1 (en) Multi-finger capacitor with reduced series resistance
CN113345857A (zh) 半导体元件及其制备方法
US20110278569A1 (en) Wafer level integration module with interconnects
JP5686851B2 (ja) スルーチップ接続を有するフロントエンドプロセス済ウェハ
US8212331B1 (en) Method for fabricating a backside through-wafer via in a processed wafer and related structure
US10910345B2 (en) Semiconductor device with stacked die device
US8329573B2 (en) Wafer level integration module having controlled resistivity interconnects
US8664025B2 (en) Substrate dicing technique for separating semiconductor dies with reduced area consumption
KR100896841B1 (ko) 반도체 소자 제조시 본드 패드 형성방법
US10134670B2 (en) Wafer with plated wires and method of fabricating same
US20070281460A1 (en) Front-end processed wafer having through-chip connections

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20090619

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC MT NL PL PT RO SE SI SK TR

RIN1 Information on inventor provided before grant (corrected)

Inventor name: TREZZA, JOHN

DAX Request for extension of the european patent (deleted)
A4 Supplementary search report drawn up and despatched

Effective date: 20111201

RIC1 Information provided on ipc code assigned before grant

Ipc: H01L 21/768 20060101AFI20111125BHEP

Ipc: H01L 23/48 20060101ALI20111125BHEP

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN

18W Application withdrawn

Effective date: 20120629