Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
  • G11C7/1045—Read-write mode select circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
  • G11C7/1066—Output synchronization
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
  • G11C7/1093—Input synchronization
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/26—Sensing or reading circuits; Data output circuits

Definitions

• This invention is in the field of flash memory devices, and is more specifically directed to data communications between flash memory devices and memory controllers in electronic systems.
• flash memories are electrically-erasable semiconductor memory devices that can be erased and rewritten in relatively small blocks, rather than on a chip-wide or large-block basis as in previous electrically-erasable programmable read-only memory (EEPROM) devices.
• EEPROM electrically-erasable programmable read-only memory
• flash memory has become especially popular for applications in which non-volatility (i.e., data retention after removal of power) of the stored data is essential, but in which the frequency of rewriting is relatively low.
• Examples of popular applications of flash memory include portable audio players, "SIM" card storage of telephone numbers and phone activity in cellular telephone handsets, "thumbkey” removable storage devices for computers and workstations, storage devices for digital cameras, and the like.
• NAND non-volatile memory
• NOR flash memory refers to the conventional arrangement of a column of memory cells in parallel between a bit line and a source line. Access of a specific cell in a NOR column is made by driving its word line (control gate) active while holding the other cells in the column off, so that the current between the bit line and source line is determined by the state of the accessed cell.
• Memory cells in a column of NAND memory are connected in series between the bit line and the source line.
• Accessing of a specific cell in a NAND column thus requires turning on all of the cells in the column with active word line levels, and applying an intermediate word line level to the cell to be accessed, such that the current between the bit line and source line is, again, determined by the state of the accessed cell.
• the chip area required per bit of NAND flash memory is much reduced from the area per bit of NOR flash memory, primarily because fewer conductors (and therefore contacts) are required for a column of NAND memory relative to NOR memory; in addition, access transistors can be shared among a large number of cells in the NAND arrangement.
• conventional NAND flash memory is conveniently accessed serially, for example by sequentially accessing cells along the columns, rather than as a random access memory as in the case of NOR memory. NAND memory is thus especially well-suited for music and video storage applications
• MLC multilevel program cell
• MLC flash memory with up to eight possible states, or three binary bits, per cell are known.
• the ability to store two or three bits of data on each memory cell immediately doubles or triples the data capacity of a flash memory chip. Examples of MLC flash memory cells and memories including such MLC cells are described in U.S. Patent No. 5,172,338, and U.S. Patent No. 6,747,892 B2, both commonly assigned herewith and incorporated herein by this reference.
• DDR double data rate
• DDR data transfer involves the transfer of one or more data bits (depending on the number of bus lines) synchronously with both the rising and falling edges of the corresponding data strobe, or clock.
• DDR data transfer thus communicates data at twice the data rate of conventional synchronous data transfer, which is synchronous with only one of the clock edges (rising or falling edge).
• conventional DDR dynamic RAMs utilize source -synchronous data strobes, in which the RAM device itself generates the data strobe for reads from the memory (while the external circuitry generates the data strobe for writes to the memory).
• source -synchronous data strobes in which the RAM device itself generates the data strobe for reads from the memory (while the external circuitry generates the data strobe for writes to the memory).
• this doubling of the input/output switching rate increases the power consumption of data transfer, approaching twice that of single-data rate communications.
• DMA Mode is known in the art, for communications to and from a flash memory card, such as a COMPACT FLASH, or CF+, flash memory card.
• Figure 1 illustrates such a conventional flash memory card, constructed and operating according to the well-known standard CF+ and CompactFlash Specification Revision 3.0 (CompactFlash Association, 2004).
• flash memory card 2 which in this example is constructed as a COMPACT FLASH storage card according to this standard, contains one or more flash memory modules 2, and single chip memory controller 4.
• Flash memory module 4 communicates data to and from memory controller 6 over bus data_I/O, and receives and issues control signals to and from memory controller 6 over control bus Ctrl.
• the data transfer approach described in the above-referenced Toshiba datasheet corresponds to these communications over the data_I/O and Ctrl buses between flash memory module 4 and memory controller 6.
• Memory controller 6 communicates with a host device (e.g., digital camera, digital audio player, personal computer, etc.) over host interface HOST IF.
• host device e.g., digital camera, digital audio player, personal computer, etc.
• the above-referenced CF+ and CompactFlash Specification describes communications over host interface HOST IF, including according to the Ultra DMA Mode ("UDMA").
• UDMA communications are carried out in a special operating mode, initiated by the driving of a signal on a control line (UDMARQ) by the agent (host or memory card 2) that desires such communication.
• UDMARQ Ultra DMA Mode
• UDMA data transfers are source -synchronous, in that the agent (memory card 2 or host system) that is placing the data onto bus HOST IF is also issuing the data strobe signal.
• agent memory card 2 or host system
• data strobe signal both rising and falling edges of the strobe signal are used in the transfer of data under the UDMA mode of operation.
• legacy data communications can also be carried out, to provide backward-compatibility with conventional data transfer standards.
• a first aspect of this invention may be implemented into a flash memory device having a multiple -mode data interface.
• the data interface presents or receives data synchronously with an externally-generated data strobe, with one bit per conductor communicated in each cycle of the strobe.
• the data interface is source-synchronous, with a data bit or word synchronous with strobe edges of both polarities (rising and falling).
• a reduced voltage swing is provided for the advanced mode, to reduce power consumption.
• the legacy operating mode continues to be used for command and control communications; data time-out and other automated control functions are provided for the advanced operating mode.
• a second aspect of this invention may be implemented into a flash memory device having a multiple -mode data interface.
• the data interface presents or receives data synchronously with an externally-generated data strobe, with one bit per conductor communicated in each cycle of the strobe.
• the data interface is source -synchronous, with a data bit or word synchronous with either a rising or falling edge of a strobe signal that is at twice the frequency of the legacy mode strobe.
• a reduced voltage swing is provided for the advanced mode, to reduce power consumption.
• a third aspect of this invention may be implemented into a flash memory device having a multiple -mode data interface.
• the data interface presents or receives data synchronously with an externally-generated data strobe, with one bit per conductor communicated in each cycle of the strobe.
• a write enable strobe signal issued to the memory by a controller clocks each data word presented by the controller to the flash memory; in a read operation in this legacy mode, a read enable strobe signal issued to the memory by the controller clocks each data word presented by the flash memory to the controller.
• the data interface is source-synchronous, with a data bit or word synchronous with strobe edges of both of the read and write enable strobes.
• the flash memory device issues the read and write strobes, at differing phase from one another, to clock alternating output data words.
• the controller issues the read and write strobes, at differing phase from one another, to clock alternating input data words into the memory.
• a reduced voltage swing is provided for the advanced mode, to reduce power consumption.
• Figure 1 is a block electrical diagram of a conventional memory card.
• Figure 2 is an electrical diagram, in block form, of a memory module constructed according to the preferred embodiment of the invention.
• Figure 3 is an electrical diagram, in block form, of the memory module of
• Figure 2 implemented into a system or subsystem in combination with a single-chip memory controller, according to the preferred embodiment of the invention.
• Figures 4a through 4d are timing diagrams illustrating the operation of the flash memory module of Figures 2 and 3 in a normal operating mode, and in the communication of commands, according to the preferred embodiment of the invention.
• Figures 5a and 5b are flow diagrams illustrating the operation of advanced mode read data transfers and write data transfers, respectively, according to the preferred embodiments of the invention.
• Figures 6a through 6e are timing diagrams illustrating signals involved in the operations of Figures 5 a and 5b according to a first preferred embodiment of the invention.
• Figure 7 is a flow diagram illustrating the operation of advanced mode data transfers according to a second preferred embodiment of the invention.
• Figures 8a through 8e are timing diagrams illustrating signals involved in the operations of Figures 5 a and 5b according to a second preferred embodiment of the invention.
• Figures 9a through 9e are timing diagrams illustrating signals involved in the operations of Figures 5 a and 5b according to a third preferred embodiment of the invention. DETAILED DESCRIPTION OF THE INVENTION
• the present invention will be described in connection with its preferred embodiment, namely as implemented into a flash memory module, and a subsystem including such a flash memory module, and method of operating the same. More specifically, this exemplary flash memory module is described as a multi-level cell (MLC) flash memory of the NAND type, as it is contemplated that this invention will be particularly useful in connection with such flash memories, in order to enable the use of solid-state non-volatile memory for mass data storage in computer systems. However, it is contemplated that this invention will be useful and beneficial in other applications involving non -volatile solid-state memories of various types. Accordingly, it is to be understood that the following description is provided by way of example only, and is not intended to limit the true scope of this invention as claimed.
• MLC multi-level cell
• Figure 2 illustrates an exemplary construction of flash memory device (or module) 10 constructed according to a preferred embodiment of the invention. It is contemplated that flash memory device 10 will typically be constructed into a single integrated circuit, and as such may be interfaced with any one of a number of memory controllers or memory controller logic, as will be described in further detail below. It is also contemplated that the architecture of flash memory device 10 illustrated in Figure 2 is merely an example presented for purposes of comprehending this invention, and that those skilled in the art having reference to this specification can readily realize this invention in connection with flash memory devices of architectures varying from that shown in Figure 2.
• flash memory array 12 includes electrically programmable and erasable memory cells arranged in rows and columns, as known in the art. While a single array 12 is shown in Figure 2, it is of course contemplated that array 12 may be realized as multiple sub-arrays, each having a separate instance of peripheral circuitry, such as part or all of the address, data, or control circuitry described in further detail below relative to the example of Figure 2. It is contemplated that those skilled in the art having reference to this specification will be readily able to realize this invention in connection with such multiple sub-array architectures.
• the memory cells of array 12 are floating-gate metal -oxide- semiconductor (MOS) transistors, constructed so that each such transistor, corresponding to one memory cell, can be electrically programmed and also electrically erased.
• the memory cells of array 12 are multi-level cells (MLC), in that they may be programmed to more than two data states (i.e., to any of more than two threshold voltages), so that each such cell stores a multiple-bit digital value.
• MLC multi-level cells
• these memory cells are preferably arranged in the well-known NAND fashion, such that the cells are typically not randomly accessed but are rather accessed serially, as useful for mass storage applications.
• this invention may also be used in connection with binary memory cells (i.e., storing only a single digital bit), and in connection with NOR arrangements of the memory cells.
• common input/output terminals 1/01 through I/On are provided, and connected to input/output control circuit 20.
• the operation of flash memory device 10 is controlled in large part by the receipt and execution of commands, communicated as digital words over input/output terminals I/Ol through I/On, and executed by control logic 18.
• input/output control circuit 20 receives control commands, address values, and input data, and presents status information and output data, via its driver and receiver circuitry that communicate with input/output terminals I/Ol through I/ On.
• input/output control circuit 20 receives power supply voltage V CC _ R and drives input/output terminals I/Ol through I/On with logic levels based upon that voltage.
• this power supply voltage V CC -R is at a lower voltage than that used in conventional flash memory devices, so that the power consumption resulting from data transfers at input/output terminals I/Ol through I/On is reduced, even at higher switching rates.
• Control logic 18 also receives this power supply voltage V CC -R based upon which it will drive output control signals at the lower voltages from read enable terminal RE_, among others.
• Input/output control circuit 20 forwards command information to command register 24, for decoding and execution by control logic 18, as it controls the operation of flash memory device 10. Status information is stored by control logic 18 in status register 23, in the conventional manner. Address values received at input/output terminals 1/01 through I/On by input/output control circuit 20 are buffered in address register 22; the row portion of such addresses is decoded by row decoder 11 and the column portion is decoded by column decoder 15 (each of which typically includes an address buffer), to effect selection of the desired cell or cells in array 12, in the conventional manner.
• Input/output control circuit 20 is also in bidirectional communication with data register 14, via bus DATA BUS, to forward data to be written to data register 14, and to receive output data from data register 14, depending upon the direction of the data transfer to be executed.
• Control logic 18 also receives various direct control signals from external to flash memory device 12, including, for example, lines for the signals of chip enable CE_, command latch enable CLE, address latch enable ALE, write enable WE_, read enable RE_, and write protect line WP_.
• the command latch enable CLE and address latch enable ALE signals indicate whether a command or address is being presented on input/output terminals I/Ol through I/On, while the write enable WE_ and read enable RE_ signals serve as the data strobes in write and read operations, respectively.
• the write enable WE_ signal is an input to flash memory device 10. Accordingly, for the transfer of data into flash memory device 10 via input/output terminals I/Ol through I/On, the write data strobe conveyed as the write enable WE_ signal is always sourced by a device external to flash memory device 10, typically by the source of the incoming data itself.
• the read enable RE_ signal is bidirectional. In a normal operating mode, the external device that is the destination of data being read from flash memory array 12 is the source of the read data strobe, which is then conveyed as an input to flash memory device 10 as the read enable RE_ signal.
• control logic 18 issues the read data strobe as the read enable RE_ signal, synchronous with data read from flash memory array 12 and communicated via data register 14, I/O control circuit 20 and input/output terminals I/Ol through I/On.
• Figure 3 illustrates an implementation of flash memory device (or module)
• flash memory card 25 includes at least flash memory device 10 itself and also controller 30.
• Controller 30 provides and manages an external interface HOST IF to a host system, such as a high-performance digital camera, a personal computer, or a portable device such as a digital audio player or cellular telephone handset or the like; interface HOST IF may also correspond to a set of external terminals of flash memory card 25 constructed as a general purpose card that may be inserted into any one of a wide range of host systems, as known in the art. It is contemplated that interface HOST IF may operate according to a conventional standard interface as known in the art currently, or as may be developed in connection with future flash memory interface standards or proprietary interface protocols.
• this invention will be especially beneficial in providing high speed data transfer, such as in the data transfer rate critical application of a high-performance digital still camera. It is further contemplated that the high data transfer rates provided by this invention can also enable the use of flash memory as a solid-state mass storage device in a personal computer, replacing magnetic disk drives. As such, it is contemplated that interface HOST IF will best have high-speed data transfer capability, for example as contemplated by the UDMA standard mentioned above in the Background of the Invention.
• flash memory device 10 is coupled to controller 30 in a manner consistently with the terminals shown in Figure 2.
• an input/output bus is formed by signal lines 1/01 through I/On, corresponding to similarly named terminals of flash memory device 10.
• a control bus CTRL couples controller 30 to flash memory device 10, and includes signal lines connected to the ALE, CLE, WP_, and CE_ terminals shown in Figure 2. It is contemplated that other control lines and terminals may also be provided for communication between flash memory device 10 and controller 30, and as such control bus CTRL is illustrated as a bidirectional bus, even though the ALE, CLE, WP_, and CE_ terminals are shown in Figure 2 as inputs to flash memory device 10.
• Figure 3 illustrates two control lines, RE_ and WE_, separately from control bus CTRL, for the sake of clarity of this description.
• line WE_ carries the data strobe in write operations (data written from controller 30 to flash memory device 10), and as such is connected to terminal WE_ of flash memory device ( Figure 2).
• the data strobe on line WE_ is sourced by controller 30 in each of the operating modes.
• Line RE_ carries the data strobe for read operations (data read from flash memory 10 and communicated to controller 30), and as such is connected to terminal RE_ of flash memory device 10 ( Figure 2).
• line RE_ is bidirectional, with the source of the read data strobe depending on the current operating mode of flash memory device 10.
• controller 30 sources the read data strobe, in response to which flash memory device 10 maintains as valid data it presents on signal lines I/Ol through I/On.
• flash memory device 10 sources the read data strobe on line RE_ for data transfer from flash memory device 10 to controller 30.
• commands communicated by controller 30 over signal lines I/Ol through I/On are synchronous with a read data strobe source on signal line RE_, regardless of the operating mode in which flash memory device 10 is transferring data to controller 30.
• controller 30 will be constructed substantially according to conventional flash memory controller architectures, as known in the art, modified as necessary to effect the operations described in this specification in connection with the initiation, operation, and termination of read operations in the advanced operating mode of flash memory device 10 according to the preferred embodiment of the invention. It is also contemplated that the logic hardware, program instructions, or combination thereof for implementing these advanced operating mode functions within controller 30 will be apparent to those skilled in the art having reference to this specification. As such, it is further contemplated that those skilled readers will be readily able to implement such modifications of controller 30, as best appropriate for a particular realization, without undue experimentation.
• power supply voltage V CC R is connected to, and biases, each of flash memory device 10 and controller 25.
• This power supply voltage V CC _ R is at a lower voltage than that used in conventional flash memory devices and controllers, so that the power consumption resulting from data transfers and transitions over input/output lines I/Ol through I/On and the various control lines is reduced, even at higher switching rates as will be described below.
• this power supply voltage may be at a nominal voltage of about 1.80 volts, within a range from about 1.60 volts to about 2.00 volts, which is substantially lower than the conventional standard nominal power supply voltage of 3.30 volts, within a specification range of between 2.70 volts and 3.60 volts.
• flash memory device 10 in combination with controller 30 in memory card 25, according to a normal operating mode and also a command communication mode, will now be described. It is contemplated that these operating modes will substantially correspond to conventional flash memory interface protocols for modern flash memory devices, and as such these operating modes will serve as a "legacy" input/output protocol for flash memory device 10 according to the preferred embodiment of the invention.
• Figure 4a illustrates the communication of a command from controller 30 to flash memory device 10.
• controller 30 driving command latch enable signal CLE to a high active state, and address latch enable signal ALE to a low inactive state, signifying that a command, rather than an address, will be communicated on input/output lines 1/01 through I/On.
• Chip enable signal CE_ is taken active low, enabling flash memory device 10 in the conventional manner; as known in the art, if multiple flash memory devices 10 are provided within card 25, individual chip enable signals CE_ can be used by controller 30 as it selects the desired one of the flash memory devices 10 for communication.
• the digital word presented by controller 30 on input/output lines 1/01 through I/On, corresponding to command CMD as shown in Figure 4a, is strobed by controller 30 issuing an active low pulse on write enable line WE_; the rising edge of the pulse on line WE_ causes I/O control circuit 20 to receive and latch in the command CMD, eventually reaching command register 24 ( Figure 2). Controller 30 can then return the command latch enable signal CLE to an inactive low state, terminating the command operation.
• multiple word commands, or multiple single -word commands can be communicated sequentially in this manner, with command latch enable line CLE held high for the duration of such communications.
• One command that is communicated in the manner illustrated in Figure 4a is a command (e.g., command 0OH for a read operation; command 1OH for a serial data input program, or write, operation) indicating that a memory address will be communicated by controller 30 to flash memory device 10.
• Figure 4b illustrates the timing of the communication of such an address by controller 30 to flash memory device, in a normal and command operating mode according to the preferred embodiment of the invention. As such, the operation illustrated in Figure 4b follows the communication of a command 0OH, according to the sequence of Figure 4a, indicating the imminent transmission of a memory address in the next signal sequence.
• controller 30 drives command latch enable signal CLE inactive low, and drives address latch enable signal ALE high, indicating to flash memory device 10 that an address value will be communicated (rather than a command value) on input/output lines I/Ol through I/On.
• the chip enable signal CE_ is also driven active low, indicating that controller 30 is selecting flash memory device 10 as the recipient of this address information.
• controller 30 issues active low pulses of the write enable signal WE_, each pulse indicating a portion of the address value then presented by controller 30 on input/output lines I/Ol through I/On.
• this address information is synchronous with the rising edge (i.e., end of the active low pulse) of write enable signal WE_, such that flash memory 10 can use this edge to latch the then-current state of input/output lines I/Ol through I/On into address register 22 ( Figure 2) as a portion of the desired memory address.
• the memory address extends over multiple words (the width of which is defined by the number n of input/output lines I/Ol through I/On).
• the memory address includes four address words ADDO through ADD3 that are presented synchronously with successive active low pulses of write enable signal WE_.
• controller 30 can perform a write of data to flash memory device 10, or a read of data therefrom.
• Figure 4c illustrates the signals communicated to effect a write operation, according to this preferred embodiment of the invention, and in a normal operating mode (i.e., a "legacy" mode).
• this data write operation is a write of data to data register 14.
• a write to data register command e.g., command value 80H
• controller 30 can perform a write of data to flash memory device 10, or a read of data therefrom.
• Figure 4c illustrates the signals communicated to effect a write operation, according to this preferred embodiment of the invention, and in a normal operating mode (i.e., a "legacy" mode).
• this data write operation is a write of data to data register 14.
• a write to data register command e.g., command value 80H
• controller 30 drives command latch enable signal CLE and address latch enable signal ALE both inactive low, indicating to flash memory device 10 that input data to be written (i.e., neither a command nor an address value) will be communicated on input/output lines I/Ol through I/On.
• chip enable signal CE_ is also driven active low for this operation.
• Controller 30 then issues active low pulses of the write enable signal WE_ along with each byte or word of data presented on input/output lines I/Ol through I/On.
• the valid input data is presented synchronous with the rising edge of write enable signal WE_ at the end of each pulse.
• flash memory device 10 latches the then-current state of input/output lines I/Ol through I/On, corresponding to a word or byte of input data, either into data latch within I/O control circuit 20, or directly (or eventually, as the case may be) over bus DATA BUS to data register 14.
• Figure 4c illustrates the communication of four words D 1n (O) through D in (3) over input/output lines I/Ol through I/On, synchronous with four pulses of write enable signal. WE_.
• Figure 4d illustrates the operation of controller 30 and flash memory device
• a data read operation from flash memory device 10 to controller 30 in a normal operating ("legacy") mode according to the preferred embodiment of the invention.
• a command sequence e.g., as shown in Figure 4a
• an address sequence e.g., as shown in Figure 4b
• One or more write operations may also have been previously carried out before this read (i.e., in which case, if the read is to the same address as has just been written, this read would serve as a verify of the previous write), or a write operation (e.g., as shown in Figure 4c) may be performed after this read operation, in the form of a read- modify -write sequence to the same memory address.
• controller 30 In response to the communication of an address prior to a read, the contents of the memory cells corresponding to that address are sensed, and forwarded to data register 14. As such, the read operation of Figure 4d is a read of the current comments of data register 14. And in order to effect this read operation, controller 30 issues the appropriate command (e.g., command EOh) in a command operation in the manner described above relative to Figure 4a.
• command EOh e.g., command EOh
• controller 30 has driven command latch enable signal CLE and address latch enable signal ALE both inactive low, and has driven chip enable signal CE_ active low. Controller 30 indicates a desired read operation by taking write enable signal WE_ inactive high. In this data read operation, flash memory device 10 outputs data words D ou t in response to falling edges of active low pulses of read enable signal RE_, as generated by controller 30.
• controller 30 is able to synchronize the receipt of data from flash memory device 10 by issuing an active low pulse of read enable signal RE_, and then waiting a specified access time (permitting flash memory device 10 to effect some or all of the operations involved in sensing the states of its memory cells, and in forwarding the sensed states to its data register 14 and out to input/output lines I/Ol through I/On. Controller 30 can then latch into its input buffer the data states of input/output lines I/Ol through I/On to receive the data from flash memory device 10.
• controller 30 can read the contents of status register 24 in this normal operating mode by issuing a specific status command (e.g., command code 70H) following the timing of Figure 4a, and receiving the contents of status register 24 over input/output lines I/Ol through I/On in response to its issuing of an active low pulse of read enable signal RE_.
• a specific status command e.g., command code 70H
• one data word or byte (referred to as "data word” in the following description) is communicated for each cycle of write enable signal WE_ or read enable signal RE_, as the case may be. And as evident from these
• controller 30 controls and sources both the write enable signal WE_ and the read enable signal RE_ in this normal operating mode.
• controller 30 has sufficient time, according to conventional flash memory timing requirements and performance, to itself issue its read data strobe (read enable signal WE ) and to receive and latch the read data.
• this level of performance may not necessarily be sufficient for high-speed use of flash memory device
• this "legacy" mode of operation may not be able to keep up with the high speed external interface mode from controller 30 to the host system, such as under the UDMA interface protocol mentioned above.
• flash memory device 10 provides an advanced, higher performance, read and write operating mode
• controller 30 is constructed to take advantage of that advanced mode.
• the operation of flash memory device 10 and controller 30 in utilizing this advanced mode will now be described in detail, in connection with the flow diagrams of Figure 5 a and 5b, and the timing diagrams of Figures 6a through 6e.
• FIGs 5 a and 6a through 6c illustrate the operation of flash memory device 10 in performing a data read operation (i.e., from flash memory device 10 to controller 30, in flash memory card 25).
• a data read operation i.e., from flash memory device 10 to controller 30, in flash memory card 25.
• flash memory device 10 and controller 30 are powered-up, which places both of these devices into the normal operating mode (process 42), as described above relative to Figures 4a through 4d.
• process 44 read and write operations (if any) in this normal mode are carried out in this normal operating ("legacy") mode.
• Entry into the advanced read operating mode begins with process 46, in which controller 30 issues a memory address value to flash memory device 10 according to the normal operating mode, as described above relative to Figure 4b.
• the memory address issued by controller 30 in process 46 is the initial memory address from which data will be read in this advanced operating mode, and preferably follows the transmission of the corresponding read address input command as described above.
• controller 30 issues an "initiate data transfer", or "IDT", command sequence to flash memory device 10.
• IDT initiate data transfer
• an "IDT” command is issued by controller 30 to flash memory device to initiate the advanced data transfer mode in process 48.
• This command is issued in a similar manner as the issuing of commands described above relative to Figure 4a, with controller 30 driving chip enable signal CE_ active low, address latch enable signal ALE inactive low, and command latch enable signal CLE active high.
• the rising edge of an active low pulse of write enable signal WE_ serves as the data strobe for the IDT command value IDT CMD (which is a binary word having a value different from other assigned command values) driven onto input/output lines I/Ol through I/On by controller 30.
• controller 30 After a specified time following write enable signal WE_ being taken high, controller 30 places input/output lines I/Ol through I/On into a high -impedance state. And, after another elapsed time t re ⁇ following the rising edge of the write enable signal WE_, when strobing in the IDT command, controller 30 then also releases control of its read enable signal RE_, permitting control logic 18 of flash memory device 10 to drive the state of corresponding line RE_ (without risking data contention with controller 30).
• flash memory device 10 begins executing high-speed mode read data transfer process 50. As shown in Figure 6a, this read data transfer process begins with flash memory device 10 issuing the first valid output data word D ou t(0), following the elapse of a non-zero access time after the rising edge of write enable signal WE_. Once it presents this first output data word D ou t(0), flash memory device 10 then begins issuing active pulses of read enable signal RE_, synchronous with additional output data words D out (l ) et seq.
• one data word Dout(£) is issued synchronously with each edge, falling and rising, of the read enable signal RE_ driven by flash memory device 10 itself.
• each output data word D out (&) follows its strobe edge by a non-zero access time; alternatively, each read enable signal RE_ edge may be issued (or delayed to be issued) to controller 30 within its corresponding valid data word D O ut(&).
• the rate at which flash memory device 10 presents data to controller 30 via input/ output lines I/Ol through I/On, in this advanced mode is substantially faster than the data rate in the normal operating mode ( Figure 4d), approaching twice the data rate in typical realizations.
• This higher data rate is in part enabled by permitting flash memory device 10 to issue the read data strobe edges of read enable signal RE_, which eliminates the propagation delay and necessary timing windows that would be involved if controller 30 were issuing these read data strobe edges.
• the output data rate is 25 MHz (i.e., a data transition every 40 nsec); in the worst case of a given input/output line VOk making a data transition in each cycle, flash memory device 10 would be required to charge the capacitance of input/output line VOk at a frequency of 12.5 MHz. Assuming a typical line capacitance of 65 pF for this input/output line VOk, the current consumption, in milliamperes, for one input/output line VOk can be calculated from:
• the current consumed in driving read enable signal RE_ will be twice that of current I k , as it must charge its corresponding conductor for every transition.
• the bus voltage is substantially reduced from this conventional 3.3v bus level, for example to a bus voltage of about 1.8 volts, defining the nominal voltage swing at about 1.80 volts.
• an example of the minimum high output level voltage V O H-R limit may be about 1.44 volts (80% of the nominal power supply voltage) and an example of the maximum low output level voltage V OL R ma y be about 0.36 volts (20% of the nominal power supply voltage).
• these voltages are based on a power supply voltage that is nominally at 1.80 volts, and which is permitted to range from about 1.60 volts to about 2.0 volts.
• This current consumption, per input/output line, is thus not much different for the advanced operating mode, while providing twice the data rate.
• read enable signal RE_ is operating at the same frequency as in the normal operating mode (but clocking one data word with each edge, rather than only with the rising edge). But its voltage swing is of course also reduced, as it is also operating at the 1.8 volt bus voltage; as such, its current consumed is the same as that for one of the input/output lines.
• the overall current consumed in the advanced operating mode for this example, again assuming eight input/output lines 1/01 through 1/08, will therefore be:
• the advanced read data transfer is executed at these lower bus voltages (relative to conventional flash memory devices)
• the current consumed in the advanced mode is no worse than that consumed by conventional flash memory devices in the normal operating mode.
• the lower bus voltage is used in both the advanced mode and the normal operating mode, as well as for other operations including the communication of commands and address value.
• flash memory device 10 consumes less power, in its transfer of data, than conventional flash memory devices.
• command and address signals are communicated in the normal operating mode.
• the bus voltage for the communication of these signals is also preferably maintained at the lower bus voltage (e.g., 1.8 volts), providing additional reduction in the power consumption of flash memory card 25.
• flash memory device 10 is capable of responding to a suspend request from controller 30. It is contemplated, according to this invention, that a suspend of the read data transfer may be deemed necessary by controller 30 for any one of a number of reasons, for example if its internal receive data buffer is full. As such, decision 51 of Figure 5a determines whether such a suspend is required. If not, the high-speed read data transfer continues in process 56, in the manner described above relative to Figure 6a.
• controller 30 requires a suspend of the read data transfer (decision 51 is
• FIG. 6b illustrates such a suspend operation, occurring during a read data transfer in the advanced mode (i.e., after the mode has been invoked and the data transfer has begun).
• controller 30 requests the data transfer suspend by asserting address latch enable signal ALE during the data transfer from flash memory device 10 to controller 30.
• flash memory device 10 suspends read enable signal RE_ (either when at a low level as shown, or at a high level), and thus delays the issuing of a next data word after read enable signal RE_ is suspended.
• one or two additional data words, and the corresponding edges of read enable signal RE may be driven by flash memory device 10 after address latch enable signal ALE is driven active high to request the suspend.
• controller 30 has asserted address latch enable signal ALE during output data word D ou t(4), and flash memory device 10 responds by holding further transitions of read enable signal RE_ and of input/output lines I/Ol through I/On during output data word D out (6).
• This suspension of further data transfer continues until controller 30 executes process 54 to inactivate address latch enable signal ALE, thus ending the suspend.
• the suspend state is ended upon controller 30 taking address latch enable signal ALE to an inactive low state.
• this transition of address latch enable signal ALE serves as the read data strobe for the next output data word from flash memory device 10, namely data word D out (7) in this example.
• flash memory device 10 again generates the read strobe signal by asserting transitions of read enable signal RE_ as shown.
• the next transition of read enable signal RE_ in this example, is the strobe for the second output data word D out (8) following the end of the suspend period.
• the advanced mode read data transfer continues, in process 56, as shown in Figure 6b.
• the advanced mode read data transfer continues until such time as controller 30 wishes to terminate the transfer, which it indicates to flash memory device 10 in processes 58, 59.
• this transfer will be terminated upon controller 30 determining that the end of a page within flash memory device 10 is being reached, although the transfer may also be terminated by controller 30 for other reasons (e.g., upon receiving all of the desired data for the operation).
• controller 30 to terminate this data transfer, controller 30 first issues a suspend in process 58, for example by asserting an active high level of address latch enable signal ALE as described above.
• Figure 6c illustrates this example of the termination processes 58, 59, within which is shown the transition of address latch enable signal ALE during the advanced read data transfer operation.
• This suspend operation of process 58 is transformed into termination of the advanced read data transfer by controller 30 performing process 59 during the suspend operation.
• process 59 may be performed after flash memory device 10 itself determines that its output data has reached the end of a page, in which case flash memory device 10 itself maintains read enable signal RE_ at its last level, and maintains the current (i.e., last) output data word on input/output lines I/Ol through I/On; in this case, address latch enable signal ALE will remain inactive low.
• this data transfer is terminated by controller 30 asserting an active high level on command latch enable signal CLE while address latch enable signal ALE is active high.
• flash memory device 10 controls its output drivers to place input/output lines 1/01 through I/On into a high impedance state, and also releases its control of the conductor corresponding to read enable signal RE_, in both cases permitting controller 30 to take control of these lines when appropriate, while avoiding data contention issues.
• controller 30 will drive an inactive high level on the corresponding line once it takes control of the read enable signal RE_, causing a transition as shown; if the suspend and terminate operations occurred with read enable signal RE_ already at a high level, there would of course be no transition on this line.
• Flash memory device 10 then returns to the normal operating mode ("legacy" mode), passing control back to process 44 in the flow diagram of Figure 5a.
• a new advanced mode read data transfer will require another instance of initiate process 48, according to this preferred embodiment of the invention.
• an advanced, high performance, mode is also provided for the transfer of data from controller 30 to flash memory device 10, in other words for write data transfer operations.
• flash memory device 10 begins from the normal operating mode, as entered in process 60.
• normal mode operations if any
• controller 30 issues an address value to flash memory device 10, in this normal operating mode as described above relative to Figure 4b.
• controller 66 initiates the advanced data transfer mode in similar fashion as performed for the advanced read data transfer described above relative to Figure 6a.
• the write data transfer in this advanced mode will be executed, through process 66, substantially identically as was the read data transfer.
• the command value IDT CMD issued in process 66 is the same for both the read and write data transfer operations.
• separate command values may be assigned for the two operations, relative to one another.
• controller 30 and flash memory device 10 carry out the advanced write data transfer.
• Figure 6d illustrates the timing of signals in an example of this operation, including process 66 in which the combination of command value IDT CMD, an active high level for command latch enable CLE, and an active low pulse for write enable signal WE_ are issued by controller 30 to flash memory device 10, thus initiating the advanced mode data transfer.
• address latch enable signal ALE is maintained at an inactive low level
• chip enable signal CE_ is maintained active low.
• read enable signal RE_ (not shown in Figure 6d) will be held inactive high by controller 30 throughout.
• write data transfer process 68 remains under the full control of controller 30, in this embodiment of the invention, the latency between the issuing of the command IDT CMD and the beginning of the write data transfer can be much shorter than that prior to the first output data word in the read data transfer ( Figure 6a).
• a specified time elapses between the rising edge of the pulse of write enable signal WE_ corresponding to the initiation command IDT CMD, and the falling edge of the first pulse of write enable signal WE_ corresponding to the first input data word D m (0) as shown.
• both the falling and rising edges of write enable signal WE_ serve as write data strobes, asserted by controller 30.
• this permits controller 30 to issue a new valid write data word D m (k) onto input/output lines I/Ol through I/On synchronously with each edge of write enable signal WE_.
• the write data transfer rate in this advanced mode can approach twice the data rate of a normal operating mode write operation, for the same write enable signal WE_ frequency.
• suspend decision 69 is also performed throughout the advanced mode write data transfer. Typically, the need for a write suspend is determined solely by controller 30, it being contemplated that flash memory device 10 can receive input data at this data rate without buffer overflow, etc. If no suspend is necessary (decision 69 is NO), the data transfer continues in process 72. If controller 30 requires it (decision 69 is YES), the suspend of the write data transfer is effected in process 70. In this example, suspend process 70 is effected simply by controller 30 extending the state of write enable signal WE_ as long as necessary.
• This suspension may be performed in either state (write enable signal WE_ held high or held low);
• Figure 6d illustrates suspend process 70 during the duration of write data word D m (2), in which write enable signal WE_ is held low.
• controller 30 does not issue additional write data words D 1n (A:) during suspend process 70.
• the end of the suspend period is effected merely by controller 30 driving a transition of write enable signal WE_, together with the next valid write data word D m (3) in the example shown in Figure 6d, to continue the write data transfer (process 72).
• the voltage levels of the data and control signals are preferably at a lower voltage level than the conventional levels, for example with a 1.8 volt "swing" between the high and low logic levels.
• this lower voltage bus will maintain the power consumed by this advanced write data transfer mode at or below that consumed in conventional flash memory systems operating in the normal operating mode, at half the data rate.
• controller 30 asserts address latch enable signal ALE to an active high level in process 74 to suspend the transfer, and then asserts command latch enable signal CLE to an active high level (while maintaining address latch enable signal ALE high) in process 76, which then terminates the write data transfer.
• Figure 6e illustrates the timing of the various signals in terminating a write data transfer.
• Write enable signal WE_ is either held at a high level as shown in Figure 6e, or taken to a high level from a low level after the last data word D m (5) (in this example) has been latched.
• the normal operating mode of flash memory device 10 and controller 30 is then again entered.
• the normal operating mode is effectively a "default" operating mode, considering that the execution of a command is required to invoke the advanced mode, and considering that the operation of flash memory device 10 returns to the normal operating mode at the termination of the data transfer (i.e., without requiring execution of a command).
• flash memory device 10 may be configured so that execution of a command is required to enter both the advanced data transfer mode and the normal operating mode, such that once flash memory device 10 is in the advanced data transfer mode, it will remain in that mode until a command to return to the normal operating mode is issued by controller 30 and executed by flash memory device 10.
• execution of a command is required to enter both the advanced data transfer mode and the normal operating mode, such that once flash memory device 10 is in the advanced data transfer mode, it will remain in that mode until a command to return to the normal operating mode is issued by controller 30 and executed by flash memory device 10.
• the "default" operating mode of flash memory device 10 may be the advanced data transfer mode, such that all data transfers are performed in the advanced mode unless a command is issued by controller 30 to place flash memory device 10 into the normal operating mode. According to this alternative embodiment of the invention, once flash memory device 10 is in the normal operating mode, completion of the data transfer will result in flash memory device 10 returning to the advanced data transfer mode.
• FIG. 7 illustrates the operation of flash memory device 10 according to this alternative preferred embodiment of the invention, in which the advanced data transfer mode is effectively a "default" mode.
• process 80 flash memory device 10 and controller 30 are powered-up, or otherwise complete a reset operation, and enter the advanced operating mode in process 82, effectively as a default condition, without requiring issuance or execution of a command.
• process 84 read and write operations are carried out in the advanced data transfer operating mode, effectively as described above relative to Figures 6b through 6d.
• suspend operations and the like may be carried out as described above relative to Figure 6c, for example; it is further contemplated that other operations, such as address, command, and status communication operations, may still follow the normal operating mode approach if desired.
• flash memory card 25 prepares for a normal, or "legacy", data transfer by controller 30 issuing an address value to flash memory device 10, indicating the memory location at which the normal operating mode transfer is to begin.
• controller 30 issues a command sequence to initiate the normal operating mode; it is contemplated that this command sequence will substantially correspond to that described above relative to Figure 6a, with the command sequence itself preferably operating according to the normal operating mode (contemplated that the command code value is a single byte value).
• flash memory device 10 performs a normal operating mode read or write data transfer operation, for example as described above relative to Figures 4c and 4d, depending upon the direction of the data transfer.
• controller 30 preferably issues both the read data strobe and the write data strobe clock signals, as described above.
• the normal operating mode is exited upon completion of the data transfer.
• termination of the data transfer by controller 30 issuing a suspend signal (e.g., an active level on the address latch enable signal) in process 92, followed by controller 30 terminating the transfer in process 93 (e.g., by issuing an active level of the command latch enable signal).
• a suspend signal e.g., an active level on the address latch enable signal
• controller 30 terminating the transfer in process 93 (e.g., by issuing an active level of the command latch enable signal).
• control returns to process 84, in which the advanced data transfer mode is again entered, and read and write data transfer operations carried out as desired in process 84.
• flash memory device 10 and controller 30 are in the normal operating ("legacy") mode following power -up. As such, read and write operations (if any) in this normal mode are carried out as desired by the user. Entry into the advanced operating mode for a read operation is then performed by controller 30 issuing a memory address value, corresponding to the initial memory address from which data will be read in this advanced operating mode, to flash memory device 10 in the normal operating mode. As before, this memory address is placed on input/output lines I/Ol through I/On in combination with an active level on the address latch enable signal. ALE.
• controller 30 issues an "initiate data transfer", or “IDT”, command sequence to flash memory device 10 as before, by chip enable signal CE_ active low, address latch enable signal ALE inactive low, and command latch enable signal CLE active high.
• Figure 8a illustrates this operation.
• the rising edge of an active low pulse of write enable signal WE_ serves as the data strobe for the IDT command value IDT CMD (which is a binary word having a value different from other assigned command values) driven onto input/output lines I/Ol through I/On by controller 30.
• controller 30 places input/output lines I/Ol through I/On into a high-impedance state.
• flash memory device 10 will take control of, and drive, the read enable strobe signal RE_. Accordingly, as shown in Figure 8a, upon time t re ⁇ elapsing after the rising edge of the write enable signal WE_ that strobes the IDT command, controller 30 releases control of its read enable signal RE_. Control logic 18 of flash memory device 10 can then drive the state of corresponding line RE_ without contending with controller 30. Flash memory device 10 then begins performing the high-speed, advanced mode, read data transfer.
• flash memory device 10 presents the data from the addressed memory cells at a higher data rate than in the legacy mode, in combination with a higher frequency read enable signal RE_ than is available in the legacy mode.
• flash memory device 10 may present the output data at input/output lines I/O in this advanced mode at twice the frequency at which data is presented in the legacy mode, in combination with its driving of the read enable signal RE_ at twice the frequency of that signal in the legacy mode.
• the advanced mode data rate and the frequency of read enable signal RE_ can be as high as 50 MHz. Because flash memory device 10 is itself sourcing read enable signal RE_ and also the data words, the frequencies with which these signals are produced by flash memory device 10 is not under the direct control of controller 30.
• FIG. 8a illustrates this advanced mode read operation.
• the read data transfer process begins with flash memory device 10 issuing the first valid output data word D out(O), following the elapse of a non-zero access time after the rising edge of write enable signal WE_. After the first output data word D out (0), flash memory device 10 then begins issuing active pulses of read enable signal RE_, synchronous with additional output data words D ou t(l) et seq. According to this preferred embodiment of the invention, one data word D out (A:) is issued synchronously with each full cycle of the read enable signal RE_.
• the falling edge of read enable signal RE_ is the signal edge with which the data words are synchronous; of course, the rising edge of read enable signal RE_ ⁇ i.e., read enable signal "RE”) may instead be the operative edge.
• each output data word D out (A:) follows its corresponding falling edge of read enable signal RE_ by a non-zero access time.
• each falling edge of read enable signal RE_ may be issued (or delayed to be issued) to controller 30 within its corresponding valid data word D out (&).
• the rate at which flash memory device 10 presents data to controller 30 via input/output lines I/Ol through I/On, in this advanced mode is substantially faster than the data rate in the normal operating mode ( Figure 4d), approaching twice the data rate in typical realizations.
• This higher data rate is in part enabled by permitting flash memory device 10 to issue the read data strobe edges of read enable signal RE_, which eliminates the propagation delay and necessary timing windows that would be involved if controller 30 were issuing these read data strobe edges.
• this increased data rate at input/output lines 1/01 through I/On is attained without dramatically increasing the power consumption of flash memory device 10 and controller 30, by using a reduced voltage swing of the data signal (and of read enable signal RE_, if desired).
• the nominal voltage swing of these lines is substantially reduced from this conventional 3.3v bus level, for example to a nominal voltage swing at about 1.80 volts.
• this second preferred embodiment of the invention involves only slightly more power consumption than that of the first preferred embodiment of the invention.
• the charging frequency for input/output lines I/Ol through I/On will be 25 MHz according to this preferred embodiment of the invention.
• the current h consumed for a single input/output line ⁇ J0k can thus be calculated:
• read enable signal RE_ is operating at twice the frequency as in the normal operating mode and in the first preferred embodiment of the invention, and as such its current consumption will be twice that of a single input/output line VOk:
• the current consumed for conventional data transfer, for the case of a sixteen -bit I/O bus, would be, following the description above:
• this current level is attained at a lower voltage swing (1.8 volts versus 3.3 volts) for the input/output signals.
• the power consumed in this advanced operating mode is substantially lower than that consumed in conventional flash memory cards.
• the power consumed in a conventional sixteen I/O flash memory in the normal operating mode will be about 160 mW (3.3 volts times 48.62 mA), while the power consumed by the example of the preferred embodiment of the invention described above will be about 95 mW (1.8 volts times 52.65 mA).
• This substantial reduction in power consumption is attained in combination with a substantial improvement in data transfer rate, approaching doubling of the data rate for large bursts.
• controller 30 may issue a suspend request to flash memory device 10, for example if its input buffer (from flash memory device 10) fills.
• a suspend request to flash memory device 10
• input buffer from flash memory device 10
• the suspend request is made by controller 30 asserting an active high level on address latch enable signal ALE during a high-speed read transfer.
• flash memory device 10 suspends read enable signal RE_ (either when at a high level as shown, or at a low level), delaying the next cycle of read enable signal RE_.
• controller 30 has asserted address latch enable signal ALE during output data word D out (4), and flash memory device 10 responds by holding further cycles of read enable signal RE_ and transitions at input/output lines I/Ol through I/On during output data word D ou t(6).
• FIG. 8c illustrates the termination of the advanced mode, high-speed read data transfer according to this preferred embodiment of the invention.
• controller 30 terminates the high-speed data transfer by first issuing a suspend request by asserting an active high level of address latch enable signal ALE.
• controller 30 terminates the data transfer operation by asserting an active high level on command latch enable signal CLE while address latch enable signal ALE is active high.
• flash memory device 10 causes its output drivers to place input/output lines I/Ol through I/On into a high impedance state, and also releases its control of the conductor corresponding to read enable signal RE_. Controller 30 may now take control of these lines if appropriate for the next operation.
• controller 30 maintaining read enable signal RE_ (not shown in Figure 8d) inactive high throughout the write operation.
• RE_ read enable signal
• a specified time is then permitted to elapse between the rising edge of the pulse of write enable signal WE_ with the initiation command IDT CMD, and the falling edge of the first pulse of write enable signal WE_ corresponding to the first input data word D 1n (O)-
• the frequency of cycles of write enable signal WE_ is increased, for example to twice the frequency of that used in writes in the normal mode. Falling edges of write enable signal WE_ serve as write data strobes in this example.
• write enable signal WE_ is asserted by controller 30, in combination with the data values driven by controller 30 on input/output lines I/Ol through I/On. As shown in Figure 8d, controller 30 issues a new valid write data word D 1n (A:) onto input/output lines I/Ol through I/On synchronously with each falling edge of write enable signal WE_.
• the write data transfer rate in this advanced mode can approach twice the data rate of a normal operating mode write operation.
• the maximum write data transfer rate, and write enable signal frequency is 25 MHz in the normal mode
• the data transfer rate and write enable signal frequency may be increased to as high as 50 MHz in the advanced mode according to this second preferred embodiment of the invention.
• Flash memory device 10 is constructed, according to this embodiment of the invention, so that it can receive and process data at that higher rate.
• controller 30 may use an actual write enable signal frequency and data rate at a frequency lower than the maximum (e.g., 50 MHz), depending on the system application and the rate at which controller 30 is itself processing data.
• a suspend may be inserted into the advanced mode write data transfer.
• controller
• the voltage levels of the data and control signals are preferably at a lower voltage level than the conventional levels, for example with a 1.8 volt "swing" between the high and low logic levels.
• this lower voltage bus will maintain the power consumed by this advanced write data transfer mode at or below that consumed in conventional flash memory systems operating in the normal operating mode, at half the data rate.
• the advanced mode write data transfer is performed identically as the termination of an advanced read data transfer according to this second preferred embodiment of the invention. Termination of the advanced mode is performed by controller 30 driving address latch enable signal ALE to an active high level to suspend the write transfer, during which time controller 30 asserts command latch enable signal CLE to an active high level (while maintaining address latch enable signal ALE high) to terminate the write data transfer.
• Write enable signal WE_ is either held at or taken to a high level after the last data word D in (5) (in this example) has been latched.
• the advanced, or high-speed, data transfer mode of operation is carried out in an alternative manner, by permitting the use of higher frequency strobe signals to increase the data rate. It is contemplated that this operation, according to the second preferred embodiment of the invention, may be more compatible with the desired operation in some flash memory applications.
• both of the read enable RE_ signal and the write enable WE_ signal are bidirectional.
• the external device that is the destination of data being read from flash memory array 12 is the source of the read data strobe, which is then conveyed as an input to flash memory device 10 as the read enable RE_ signal.
• the external device that is providing the input data sources the write data strobe as the write enable WE_ signal, synchronously with the placing of the input data at input terminals I/Ol through I/On.
• control logic 18 issues two read data strobes, phase-shifted from one another, with one of the read data strobes being the read enable RE_ signal and the other being the write enable WE_ signal.
• An edge, or transition, of each of these signals will be synchronous with data read from flash memory array 12 and communicated via data register 14, I/O control circuit 20 and input/output terminals I/Ol through I/On.
• write operations will be carried out in the advanced operating mode by using both the read enable RE_ signal and the write enable WE_ signal as write data strobes, issued by the data source to flash memory device 10.
• line RE_ carries the data strobe for legacy mode read operations (data read from flash memory 10 and communicated to controller 30), and as such is connected to terminal RE_ of flash memory device 10 ( Figure 2).
• line RE_ is bidirectional, with the source of the read data strobe depending on the current operating mode of flash memory device 10. In a normal operating mode, controller 30 sources the read data strobe, in response to which flash memory device 10 maintains as valid data it presents on signal lines I/Ol through
• flash memory device 10 sources the read data strobe on line RE_ for data transfer from flash memory device 10 to controller 30. And as will also be described in detail below, controller 30 will also strobe line RE_ during advanced mode write operations. Therefore, similarly as line WE_, control line RE_ is involved in both read and write operations in the advanced data transfer mode according to the preferred embodiments of this invention, to provide a second phase-shifted strobe signal that is used to strobe alternating data words in both read and write operations.
• commands communicated by controller 30 over signal lines I/Ol through I/On are synchronous with a read data strobe source on signal line RE_, regardless of the operating mode in which flash memory device 10 is transferring data to controller 30.
• flash memory device 10 provides an advanced, higher performance, read and write operating mode
• controller 30 is constructed to take advantage of that advanced mode.
• the operation of flash memory device 10 and controller 30 in utilizing this advanced mode according to this third preferred embodiment of this invention will now be described in detail, in connection with the flow diagrams of Figure 5a and 5b, and the timing diagrams of Figures 9a through 9e.
• FIGs 5 a and 9a through 9c illustrate the operation of flash memory device 10 in performing a data read operation (i.e., from flash memory device 10 to controller 30, in flash memory card 25).
• a data read operation i.e., from flash memory device 10 to controller 30, in flash memory card 25.
• flash memory device 10 and controller 30 are powered-up, which places both of these devices into the normal operating mode (process 42), as described above relative to Figures 4a through 4d.
• process 44 read and write operations (if any) in this normal mode are carried out in this normal operating ("legacy") mode.
• Entry into the advanced read operating mode begins with process 46, in which controller 30 issues a memory address value to flash memory device 10 according to the normal operating mode, as described above relative to Figure 4b.
• the memory address issued by controller 30 in process 46 is the initial memory address from which data will be read in this advanced operating mode, and preferably follows the transmission of the corresponding read address input command as described above.
• controller 30 issues an "initiate data transfer", or "IDT", command sequence to flash memory device 10.
• IDT initiate data transfer
• an "IDT read” command is issued by controller 30 to flash memory device 10 to initiate the advanced data transfer mode in process 48.
• This command is issued in a similar manner as the issuing of commands described above relative to Figure 4a, with controller 30 driving chip enable signal CE_ active low, address latch enable signal ALE inactive low, and command latch enable signal CLE active high.
• the rising edge of an active low pulse of write enable signal WE_ serves as the data strobe for the IDT command value IDT RD CMD (which is a binary word having a value different from other assigned command values) driven onto input/output lines I/Ol through I/On by controller 30.
• controller 30 After a specified time following write enable signal WE_ being taken high, controller 30 places input/output lines I/Ol through I/On into a high -impedance state. And, after another elapsed time t re ⁇ following the rising edge of the write enable signal WE_, when strobing in the IDT read command, controller 30 then also releases control of its read enable signal RE_, permitting control logic 18 of flash memory device 10 to drive the state of corresponding lines RE_ and WE_ (without risking data contention with controller 30).
• the direction of the advanced mode data transfer ⁇ i.e., either a write or a read
• the direction of the advanced mode data transfer is established by the value of the IDT command upon entry into the advanced data transfer mode, which permits both of the read enable RE_ and write enable WE_ signals to be used in the data transfer itself, as will be described below.
• the entry into the advanced data transfer mode, and the indication of whether a read or write operation in this mode is to be carried out, may be communicated from controller 30 to flash memory device 10 in other ways.
• a particular sequence of transitions of control signals ⁇ e.g., on one or more of the lines of control bus CTRL including one or more of the signal lines connected to the ALE, CLE, WP_, and CE_ lines, along with the read enable RE_ and write enable WE_ signals).
• flash memory device 10 begins executing a high-speed mode read data transfer process 50. As shown in Figure 9a, this read data transfer process begins with flash memory device 10 issuing the first valid output data word D out (0), following the elapse of a non-zero access time after the rising edge of write enable signal WE_.
• flash memory device 10 begins issuing active pulses of both read enable signal RE_ and write enable signal WE_, synchronous with alternating ones of additional output data words D ou t(l) et seq.
• read enable signal RE_ and write enable signal WE_ are out-of-phase with one another, with the same edge of each ⁇ e.g., falling edge in this example, although of course rising edges may alternatively be used) clocking a corresponding data word.
• write enable signal WE_ is 180° out of phase with read enable signal RE_ in this advanced mode read operation.
• each output data word D out (£) follows its corresponding strobe edge by a non-zero access time; alternatively, each read enable signal RE_ and write enable signal WE_ falling edge may be issued (or delayed to be issued) to controller 30 within its corresponding valid data word D out (£).
• the rate at which flash memory device 10 presents data to controller 30 via input/output lines I/Ol through I/On, in this advanced mode is substantially faster than the data rate in the normal operating mode ( Figure 4d), approaching twice the data rate in typical realizations.
• This higher data rate is in part enabled by permitting flash memory device 10 to issue the read data strobe edges of read enable signal RE_ and write enable signal WE_, which eliminates the propagation delay and necessary timing windows that would be involved if controller 30 were issuing these read data strobe edges.
• the frequency of falling strobe edges for these two signals can approach twice that of a single signal.
• the write enable signal WE_ is available for use in this read operation, because the direction of the data transfer is set by the IDT read command value.
• this power consumption is greatly reduced by reducing the voltage swing of the output signals on input/output lines I/Ol through I/On as will now be described.
• the bus voltage is substantially reduced from this conventional 3.3v bus level, for example to a bus voltage of about 1.8 volts, defining the nominal voltage swing at about 1.80 volts.
• an example of the minimum high output level voltage VOH-R limit may be about 1.44 volts
• V OL - R ma Y (80% of the nominal power supply voltage) and an example of the maximum low output level voltage V OL - R ma Y be about 0.36 volts (20% of the nominal power supply voltage).
• these voltages are based on a power supply voltage that is nominally at 1.80 volts, and which is permitted to range from about 1.60 volts to about
• the current consumed in the advanced mode is no worse than that consumed by conventional flash memory devices in the normal operating mode.
• the lower bus voltage is used in both the advanced mode and the normal operating mode, as well as for other operations including the communication of commands and address value. As such, flash memory device 10 consumes less power, in its transfer of data, than conventional flash memory devices.
• command and address signals are communicated in the normal operating mode.
• the bus voltage for the communication of these signals is also preferably maintained at the lower bus voltage (e.g., 1.8 volts), providing additional reduction in the power consumption of flash memory card 25.
• flash memory device 10 is capable of responding to a suspend request from controller 30. It is contemplated, according to this invention, that a suspend of the read data transfer may be deemed necessary by controller 30 for any one of a number of reasons, for example if its internal receive data buffer is full. As such, decision 51 of Figure 5a determines whether such a suspend is required. If not, the high-speed read data transfer continues in process 56, in the manner described above relative to Figure 9a.
• controller 30 requires a suspend of the read data transfer (decision 51 is
• FIG. 9b illustrates such a suspend operation, occurring during a read data transfer in the advanced mode (i.e., after the mode has been invoked and the data transfer has begun).
• controller 30 requests the data transfer suspend by asserting address latch enable signal ALE during the data transfer from flash memory device 10 to controller 30.
• flash memory device 10 suspends read enable signal RE_ and write enable signal WE_ (either when at a low level or a high level, as shown), and thus delays the issuing of a next data word after read enable signal RE_ and write enable signal WE_ are suspended.
• one or two additional data words, and the corresponding edges of read enable signal RE_ and write enable signal WE_, may be driven by flash memory device 10 after address latch enable signal ALE is driven active high to request the suspend.
• controller 30 has asserted address latch enable signal ALE during output data word D out (4), and flash memory device 10 responds by holding further transitions of read enable signal RE_, write enable signal WE_, and input/output lines I/Ol through I/On during output data word D ou t(6).
• the next operative transition of write enable signal WE_ in this example is the strobe for the second output data word D ou t(8) following the end of the suspend period, and the next operate transition of read enable signal RE_ is the strobe for the third output data word D out (9) after the suspend period.
• the advanced mode read data transfer continues, in process 56, as shown in Figure 9b.
• the advanced mode read data transfer continues until such time as controller 30 wishes to terminate the transfer, which it indicates to flash memory device 10 in processes 58, 59.
• this transfer will be terminated upon controller 30 determining that the end of a page within flash memory device 10 is being reached, although the transfer may also be terminated by controller 30 for other reasons (e.g., upon receiving all of the desired data for the operation).
• controller 30 to terminate this data transfer, controller 30 first issues a suspend in process 58, for example by asserting an active high level of address latch enable signal ALE as described above.
• Figure 9c illustrates this example of the termination processes 58, 59, within which is shown the transition of address latch enable signal ALE during the advanced read data transfer operation.
• This suspend operation of process 58 is transformed into termination of the advanced read data transfer by controller 30 performing process 59 during the suspend operation.
• process 59 may be performed after flash memory device 10 itself determines that its output data has reached the end of a page, in which case flash memory device 10 itself maintains read enable signal RE_ and write enable signal WE_ at their last levels, and maintains the current (i.e., last) output data word on input/output lines I/Ol through I/On; in this case, address latch enable signal ALE will remain inactive low.
• this data transfer is terminated by controller 30 asserting an active high level on command latch enable signal CLE while address latch enable signal ALE is active high.
• flash memory device 10 controls its output drivers to place input/output lines I/Ol through I/On into a high impedance state, and also releases its control of the conductor corresponding to read enable signal RE_ and write enable signal WE_, in both cases permitting controller 30 to take control of these lines when appropriate, while avoiding data contention issues.
• controller 30 will drive an inactive high level on the corresponding line once it takes control of the read enable signal RE_, and write enable signal WE_ causing a transition as shown; if the suspend and terminate operations occurred with either or both of these signals already at a high level, there would of course be no transition on that line.
• Flash memory device 10 then returns to the normal operating mode
• an advanced, high performance, mode is also provided for the transfer of data from controller 30 to flash memory device 10, in other words for write data transfer operations.
• flash memory device 10 begins from the normal operating mode, as entered in process 60.
• normal mode operations if any may first be carried out, in process 62.
• controller 30 issues an address value to flash memory device 10, in this normal operating mode as described above relative to Figure 4b.
• controller 66 initiates the advanced data transfer mode in similar fashion as performed for the advanced read data transfer described above relative to Figure 9a.
• the write data transfer in this advanced mode will be executed, through process 66, substantially identically as was the read data transfer, except with a different command value IDT WR CMD, to indicate that the advanced mode data transfer is a write operation (controller 30 to flash memory device 10) rather than a read.
• This different value permits both of the write enable signal WE_ and the read enable signal RE_ to be used within the write transfer itself, as will be described below.
• controller 30 and flash memory device 10 carry out the advanced write data transfer.
• Figure 9d illustrates the timing of signals in an example of this operation, including process 66 in which the combination of command value IDT WR CMD, an active high level for command latch enable CLE, and an active low pulse for write enable signal WE_ are issued by controller 30 to flash memory device 10, thus initiating the advanced mode data transfer.
• address latch enable signal ALE is maintained at an inactive low level
• chip enable signal CE_ is maintained active low.
• read enable signal RE_ (not shown in Figure 9d) will be held inactive high by controller 30 throughout.
• the latency between the issuing of the command IDT WR CMD and the beginning of the write data transfer can be much shorter than that prior to the first output data word in the read data transfer ( Figure 9a).
• a specified time elapses between the rising edge of the pulse of write enable signal WE_ corresponding to the initiation command IDT WR CMD, and the falling edge of the first pulse of write enable signal WE_ (or read enable signal RE) corresponding to the first input data word D m (0) as shown.
• write enable signal WE_ and read enable signal RE_ serve as write data strobes, asserted by controller 30.
• rising edges of these signals may alternatively be used.
• the data transfer rate in this write operation is increased by write enable signal WE_ and read enable signal
• RE_ having an out-of-phase relationship with one another, preferably a 180° phase relationship to maximize the data transfer rate.
• this permits controller 30 to issue a new valid write data word D 1n (A:) onto input/output lines I/Ol through I/On synchronously with each falling edge of both write enable signal WE_ and read enable signal RE_.
• the write data transfer rate in this advanced mode can approach twice the data rate of a normal operating mode write operation, for the same frequency of write enable signal WE_ and read enable signal RE_ as in the normal, legacy, operating mode.
• suspend decision 69 may also be performed in the advanced mode write data transfer.
• the need for a write suspend is determined solely by controller 30, it being contemplated that flash memory device 10 can receive input data at this data rate without buffer overflow, etc. If no suspend is necessary (decision 69 is NO), the data transfer continues in process 72. If controller 30 requires it (decision 69 is YES), the suspend of the write data transfer is effected in process 70. In this example, suspend process 70 is effected simply by controller 30 extending the state of write enable signal WE_ and read enable signal RE_ as long as necessary.
• This suspension may be performed in either state (write enable signal WE_ and read enable signal RE_ held high or held low);
• Figure 9d illustrates suspend process 70 during the duration of write data word D in (2), in which write enable signal WE_ is held low and read enable signal RE_ is held high.
• controller 30 does not issue additional write data words D m (k) during suspend process 70.
• the end of the suspend period is effected merely by controller 30 driving a falling edge transition of write enable signal WE_ or read enable signal RE_, together with the next valid write data word D m (3) in the example shown in Figure 9d, to continue the write data transfer (process 72).
• the voltage levels of the data and control signals are preferably at a lower voltage level than the conventional levels, for example with a 1.8 volt "swing" between the high and low logic levels.
• this lower voltage bus will maintain the power consumed by this advanced write data transfer mode at or below that consumed in conventional flash memory systems operating in the normal operating mode, at half the data rate.
• controller 30 asserts address latch enable signal ALE to an active high level in process 74 to suspend the transfer, and then asserts command latch enable signal CLE to an active high level (while maintaining address latch enable signal ALE high) in process 76, which then terminates the write data transfer.
• Figure 9e illustrates the timing of the various signals in terminating a write data transfer.
• Write enable signal WE_ and read enable signal RE_ are either held at or driven to a high level as shown in Figure 9e, after the last data word D in (5) (in this example) has been latched.
• the normal operating mode of flash memory device 10 and controller 30 is then again entered.
• the normal operating mode is effectively a "default" operating mode, considering that the execution of a command is required to invoke the advanced mode, and considering that the operation of flash memory device 10 returns to the normal operating mode at the termination of the data transfer (i.e., without requiring execution of a command).
• flash memory device 10 may be configured so that execution of a command is required to enter both the advanced data transfer mode and the normal operating mode, such that once flash memory device 10 is in the advanced data transfer mode, it will remain in that mode until a command to return to the normal operating mode is issued by controller 30 and executed by flash memory device 10.
• execution of a command is required to enter both the advanced data transfer mode and the normal operating mode, such that once flash memory device 10 is in the advanced data transfer mode, it will remain in that mode until a command to return to the normal operating mode is issued by controller 30 and executed by flash memory device 10.
• the "default" operating mode of flash memory device 10 may be the advanced data transfer mode, such that all data transfers are effected in the advanced mode unless a command is issued by controller 30 to place flash memory device 10 into the normal operating mode. It is contemplated that, in this case, some indication of whether a read or a write advanced mode operation can be made by controller 30, to permit both the read and write enable signals to strobe data as discussed above. According to this alternative embodiment of the invention, once flash memory device 10 is in the normal operating mode, completion of the data transfer will result in flash memory device 10 returning to the advanced data transfer mode.
• Flash memory device 10, controller 30, and flash memory card 25 thus provide important advantages over conventional devices and systems.
• This invention enables high data transfer rates, approaching double the data rate of conventional devices and systems, while still providing command and signal compatibility with "legacy" devices that do not have the advanced capability.
• the lower bus voltage signals involved in the advanced data transfer mode maintain the overall device and system current and power consumption at near, or even below, that of conventional flash memory devices and systems.
• this invention can especially be beneficial in those digital system applications in which data transfer rates are especially critical.
• One such application is in high-performance digital still cameras.
• the image resolution (and thus the data captured per image) now exceeds 10 megapixels, with up to 12.4 megapixel cameras now available on the market.
• the data transfer rate from the image sensor to flash memory is critical, however, as this data transfer rate is a direct factor in rate at which images can be captured, commonly experienced as "shutter lag" by the camera user.
• the camera user is concerned primarily with the absolute delay encountered (i.e., independent of the amount of data acquired in each image), as the image resolution increases, this load on the data transfer rate is exacerbated.

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• 2007
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